SPRZ429M July 2014 – February 2021 AM5726 , AM5728 , AM5729
Usability of ECC Feature in the DDR Controller is Limited
High
For ECC-enabled DDR regions, only quanta-sized, quanta-aligned writes are allowed (16-bit quanta for 16-bit DDR data bus, and 32-bit quanta for 32-bit DDR data bus).
For the Arm and DSP as initiators, if the caches are appropriately enabled, it is possible to ensure full quanta, aligned writes. However, for other initiators in the device (for example, EMAC, USB, 3D, 2D, IVA, PCIe, SATA, DMA, MMC, and so forth) it is difficult and in many cases impossible to ensure full quanta, aligned writes under all scenarios and use cases. The software and drivers would need to be partitioned such that the drivers for these initiators only utilize non-ECC protected memory regions. This requires significant modifications to the operating system and drivers that are neither implemented in the TI Processor SDK nor supported.
Disable ECC
Or
Partition the EMIF1 memory range into ECC protected and non-ECC protected regions. For the ECC protected region, ensure that all DDR write accesses are a multiple of quanta size and are quanta aligned. This requires modifications to the operating system and drivers that TI does not implement nor support.
SR 2.0, 1.1
AM572x: 2.0, 1.1