SPRZ357P August   2011  – June 2020 F28M35E20B , F28M35H22C , F28M35H52C , F28M35H52C-Q1 , F28M35M22C , F28M35M52C

 

  1.   F28M35x Concerto MCUs Silicon Errata Silicon Revisions E, B, A, 0
    1. 1 Introduction
    2. 2 Device and Development Support Tool Nomenclature
    3. 3 Device Markings
    4. 4 Usage Notes and Known Design Exceptions to Functional Specifications
      1. 4.1 Usage Notes
        1. 4.1.1  PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt Mask Clear
        2. 4.1.2  FPU32 and VCU Back-to-Back Memory Accesses
        3. 4.1.3  Caution While Using Nested Interrupts
        4. 4.1.4  PBIST: PBIST Memory Test Feature is Deprecated
        5. 4.1.5  HWBIST: Cortex-M3 HWBIST Feature is Deprecated
        6. 4.1.6  HWBIST: C28x HWBIST Feature Support is Restricted to TI-Supplied Software
        7. 4.1.7  Flash Tools: Device Revision Requires a Flash Tools Update
        8. 4.1.8  EPI: New Feature Addition to EPI Module
        9. 4.1.9  EPI: ALE Signal Polarity
        10. 4.1.10 EPI: CS0/CS1 Swap
        11. 4.1.11 Major Device Revision
      2. 4.2 Known Design Exceptions to Functional Specifications
    5. 5 Documentation Support
  2.   Trademarks
  3.   Revision History

4.1.10 EPI: CS0/CS1 Swap

Revision(s) Affected: A, B, E

On revision A silicon onwards, if the following conditions are true:

  • both EPADR and ERADR are not 0x0
  • the ECADR field is 0x0
  • the EPI is configured for dual-chip selects

then,

  • CS0 is asserted for either address range defined by ERADR
  • CS1 is asserted for either address range defined by EPADR

This has been changed from revision 0 silicon, where, in the same configuration,

  • CS0 is asserted for either address range defined by EPADR
  • CS1 is asserted for either address range defined by ERADR.

Table 3. CS0/CS1 Swap

SILICON REVISION CHIP SELECT MODE ERADR EPADR ECADR CS0 CS1
0 Dual-chip select 0x1 or 0x2 0x1 or 0x2 0x0 EPADR defined address range (0xA000.0000 or 0xC000.0000) ERADR defined address range (0x6000.0000 or 0x8000.0000)
A and onwards Dual-chip select 0x1 or 0x2 0x1 or 0x2 0x0 ERADR defined address range (0x6000.0000 or 0x8000.0000) EPADR defined address range (0xA000.0000 or 0xC000.0000)