SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
DLL Observable Register Upper
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| Instance Name | Physical Address |
|---|---|
| FSS0 | 0FC4 00C0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| DLL_OBSERVABLE_UPPER_RESV2_FLD | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| DLL_OBSERVABLE_UPPER_RESV2_FLD | DLL_OBSERVABLE_UPPER_TX_DECODER_OUTPUT_FLD | ||||||
| R | R | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| DLL_OBSERVABLE_UPPER_RESV1_FLD | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DLL_OBSERVABLE_UPPER_RESV1_FLD | DLL_OBSERVABLE__UPPER_RX_DECODER_OUTPUT_FLD | ||||||
| R | R | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:23 | DLL_OBSERVABLE_UPPER_RESV2_FLD | R | 0h | Reserved |
| 22:16 | DLL_OBSERVABLE_UPPER_TX_DECODER_OUTPUT_FLD | R | 0h | Holds the encoded value for the TX delay line for this slice. |
| 15:7 | DLL_OBSERVABLE_UPPER_RESV1_FLD | R | 0h | Reserved |
| 6:0 | DLL_OBSERVABLE__UPPER_RX_DECODER_OUTPUT_FLD | R | 0h | Holds the encoded value for the RX delay line for this slice. |