SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
PHY DLL Master Control Register
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| Instance Name | Physical Address |
|---|---|
| FSS0 | 0FC4 00B8h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| PHY_MASTER_CONTROL_RESV3_FLD | PHY_MASTER_LOCK_MODE_FLD | ||||||
| R | R/W | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_MASTER_BYPASS_MODE_FLD | PHY_MASTER_PHASE_DETECT_SELECTOR_FLD | PHY_MASTER_CONTROL_RESV2_FLD | PHY_MASTER_NB_INDICATIONS_FLD | ||||
| R/W | R/W | R | R/W | ||||
| 1h | 0h | 0h | 0h | ||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_MASTER_CONTROL_RESV1_FLD | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_MASTER_CONTROL_RESV1_FLD | PHY_MASTER_INITIAL_DELAY_FLD | ||||||
| R | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:25 | PHY_MASTER_CONTROL_RESV3_FLD | R | 0h | Reserved |
| 24 | PHY_MASTER_LOCK_MODE_FLD | R/W | 0h | Determines if the initiator delay line locks on a full cycle or half cycle of delay. |
| 23 | PHY_MASTER_BYPASS_MODE_FLD | R/W | 1h | Controls the bypass mode of the initiator and target DLLs. |
| 22:20 | PHY_MASTER_PHASE_DETECT_SELECTOR_FLD | R/W | 0h | Selects the number of delay elements to be inserted between the phase detect flip-flops. |
| 19 | PHY_MASTER_CONTROL_RESV2_FLD | R | 0h | Reserved |
| 18:16 | PHY_MASTER_NB_INDICATIONS_FLD | R/W | 0h | Holds the number of consecutive increment or decrement indications. |
| 15:7 | PHY_MASTER_CONTROL_RESV1_FLD | R | 0h | Reserved |
| 6:0 | PHY_MASTER_INITIAL_DELAY_FLD | R/W | 0h | This value is the initial delay value for the DLL. |