SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
PHY Configuration Register
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| Instance Name | Physical Address |
|---|---|
| FSS0 | 0FC4 00B4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| PHY_CONFIG_RESYNC_FLD | PHY_CONFIG_RESET_FLD | PHY_CONFIG_RX_DLL_BYPASS_FLD | PHY_CONFIG_RESV2_FLD | ||||
| W | W | R/W | R | ||||
| 0h | 1h | 0h | 0h | ||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_CONFIG_RESV2_FLD | PHY_CONFIG_TX_DLL_DELAY_FLD | ||||||
| R | R/W | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_CONFIG_RESV1_FLD | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_CONFIG_RESV1_FLD | PHY_CONFIG_RX_DLL_DELAY_FLD | ||||||
| R | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | PHY_CONFIG_RESYNC_FLD | W | 0h | This bit is used for re-synchronisation delay lines to update them with values from TX DLL Delay and RX DLL Delay fields. |
| 30 | PHY_CONFIG_RESET_FLD | W | 1h | DLL Reset bit: This bit is used for reset of Delay Lines by software. |
| 29 | PHY_CONFIG_RX_DLL_BYPASS_FLD | R/W | 0h | RX DLL Bypass: This field determines id RX DLL is bypassed. |
| 28:23 | PHY_CONFIG_RESV2_FLD | R | 0h | Reserved |
| 22:16 | PHY_CONFIG_TX_DLL_DELAY_FLD | R/W | 0h | TX DLL Delay: This field determines the number of delay elements to insert on data path between ref_clk and spi_clk. |
| 15:7 | PHY_CONFIG_RESV1_FLD | R | 0h | Reserved |
| 6:0 | PHY_CONFIG_RX_DLL_DELAY_FLD | R/W | 0h | RX DLL Delay: This field determines the number of delay elements to insert on data path between ref_clk and rx_dll_clk. |