SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Flash Command Read Data Register (Lower)
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| Instance Name | Physical Address |
|---|---|
| FSS0 | 0FC4 00A0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| DATA_FLD | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| DATA_FLD | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| DATA_FLD | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DATA_FLD | |||||||
| R | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:0 | DATA_FLD | R | 0h | This is the data that is returned by the flash device for any status or configuration read operation carried out by triggering the event in the control register. The register will be valid when the polling bit in the control register is low. |