SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Flash Command Control Register
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| Instance Name | Physical Address |
|---|---|
| FSS0 | 0FC4 0090h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| CMD_OPCODE_FLD | |||||||
| R/W | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| ENB_READ_DATA_FLD | NUM_RD_DATA_BYTES_FLD | ENB_COMD_ADDR_FLD | ENB_MODE_BIT_FLD | NUM_ADDR_BYTES_FLD | |||
| R/W | R/W | R/W | R/W | R/W | |||
| 0h | 0h | 0h | 0h | 0h | |||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| ENB_WRITE_DATA_FLD | NUM_WR_DATA_BYTES_FLD | NUM_DUMMY_CYCLES_FLD | |||||
| R/W | R/W | R/W | |||||
| 0h | 0h | 0h | |||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| NUM_DUMMY_CYCLES_FLD | FLASH_CMD_CTRL_RESV1_FLD | STIG_MEM_BANK_EN_FLD | CMD_EXEC_STATUS_FLD | CMD_EXEC_FLD | |||
| R/W | R | R/W | R | W | |||
| 0h | 0h | 0h | 0h | 0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:24 | CMD_OPCODE_FLD | R/W | 0h | Command Opcode: The command opcode field should be setup before triggering the command. For example, 0x20 maps to SubSector Erase. Writing to the execute field [bit 0] of this register launches the command. NOTE : Using this approach to issue commands to the device will make use of the instruction type of the device instruction configuration register. If this field is set to 2'b00, then the command opcode, command address, command dummy bytes and command data will all be transferred in a serial fashion. If this field is set to 2'b01, then the command opcode, command address, command dummy bytes and command data will all be transferred in parallel using DQ0 and DQ1 pins. If this field is set to 2'b10, then the command opcode, command address, command dummy bytes and command data will all be transferred in parallel using DQ0, DQ1, DQ2 and DQ3 pins. |
| 23 | ENB_READ_DATA_FLD | R/W | 0h | Read Data Enable: Set to 1 if the command specified in the command opcode field [bits 31:24] requires read data bytes to be received from the device. |
| 22:20 | NUM_RD_DATA_BYTES_FLD | R/W | 0h | Number of Read Data Bytes: Up to 8 data bytes may be read using this command. Set to 0 for 1 byte and 7 for 8 bytes. |
| 19 | ENB_COMD_ADDR_FLD | R/W | 0h | Command Address Enable: Set to 1 if the command specified in bits 31:24 requires an address. This should be setup before triggering the command via Writing a 1 to the execute field. |
| 18 | ENB_MODE_BIT_FLD | R/W | 0h | Mode Bit Enable: Set to 1 to ensure the mode bits as defined in the Mode Bit Configuration register are sent following the address bytes. |
| 17:16 | NUM_ADDR_BYTES_FLD | R/W | 0h | Number of Address Bytes: Set to the number of address bytes required [the address itself is programmed in the FLASH COMMAND ADDRESS REGISTERS]. This should be setup before triggering the command via bit 0 of this register. 2'b00 : 1 address byte 2'b01 : 2 address bytes 2'b10 : 3 address bytes 2'b11 : 4 address bytes |
| 15 | ENB_WRITE_DATA_FLD | R/W | 0h | Write Data Enable: Set to 1 if the command specified in the command opcode field requires write data bytes to be sent to the device. |
| 14:12 | NUM_WR_DATA_BYTES_FLD | R/W | 0h | Number of Write Data Bytes: Up to 8 Data bytes may be written using this command Set to 0 for 1 byte, 7 for 8 bytes. |
| 11:7 | NUM_DUMMY_CYCLES_FLD | R/W | 0h | Number of Dummy cycles: Set to the number of dummy cycles required. This should be setup before triggering the command via the execute field of this register. |
| 6:3 | FLASH_CMD_CTRL_RESV1_FLD | R | 0h | Reserved |
| 2 | STIG_MEM_BANK_EN_FLD | R/W | 0h | STIG Memory Bank enable bit. |
| 1 | CMD_EXEC_STATUS_FLD | R | 0h | Command execution in progress. |
| 0 | CMD_EXEC_FLD | W | 0h | Execute the command. |