SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Flash Command Control Memory Register
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| Instance Name | Physical Address |
|---|---|
| FSS0 | 0FC4 008Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| FLASH_COMMAND_CTRL_MEM_RESV1_FLD | MEM_BANK_ADDR_FLD | ||||||
| R | R/W | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| MEM_BANK_ADDR_FLD | FLASH_COMMAND_CTRL_MEM_RESV2_FLD | NB_OF_STIG_READ_BYTES_FLD | |||||
| R/W | R | R/W | |||||
| 0h | 0h | 0h | |||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| MEM_BANK_READ_DATA_FLD | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| FLASH_COMMAND_CTRL_MEM_RESV3_FLD | MEM_BANK_REQ_IN_PROGRESS_FLD | TRIGGER_MEM_BANK_REQ_FLD | |||||
| R | R | W | |||||
| 0h | 0h | 0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:29 | FLASH_COMMAND_CTRL_MEM_RESV1_FLD | R | 0h | Reserved |
| 28:20 | MEM_BANK_ADDR_FLD | R/W | 0h | The address of the Memory Bank which data will be read from. |
| 19 | FLASH_COMMAND_CTRL_MEM_RESV2_FLD | R | 0h | Reserved |
| 18:16 | NB_OF_STIG_READ_BYTES_FLD | R/W | 0h | It defines the number of read bytes for the extended STIG. |
| 15:8 | MEM_BANK_READ_DATA_FLD | R | 0h | Last requested data from the STIG Memory Bank. |
| 7:2 | FLASH_COMMAND_CTRL_MEM_RESV3_FLD | R | 0h | Reserved |
| 1 | MEM_BANK_REQ_IN_PROGRESS_FLD | R | 0h | Memory Bank data request in progress. |
| 0 | TRIGGER_MEM_BANK_REQ_FLD | W | 0h | Trigger the Memory Bank data request. |