SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Indirect Read Transfer Watermark Register
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| Instance Name | Physical Address |
|---|---|
| FSS0 | 0FC4 0064h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| LEVEL_FLD | |||||||
| R/W | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| LEVEL_FLD | |||||||
| R/W | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| LEVEL_FLD | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| LEVEL_FLD | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:0 | LEVEL_FLD | R/W | 0h | Watermark Value: This represents the minimum fill level of the SRAM before a DMA peripheral access is permitted. When the SRAM fill level passes the watermark, an interrupt is also generated. This field can be disabled by Writing a value of all zeroes. |