SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Write Protection Control Register
Return to Summary Table
| Instance Name | Physical Address |
|---|---|
| FSS0 | 0FC4 0058h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| WR_PROT_CTRL_RESV_FLD | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| WR_PROT_CTRL_RESV_FLD | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| WR_PROT_CTRL_RESV_FLD | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| WR_PROT_CTRL_RESV_FLD | ENB_FLD | INV_FLD | |||||
| R | R/W | R/W | |||||
| 0h | 0h | 0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:2 | WR_PROT_CTRL_RESV_FLD | R | 0h | Reserved |
| 1 | ENB_FLD | R/W | 0h | Write Protection Enable Bit: When set to 1, any AHB write access with an address within the protection region defined in the lower and upper write protection registers is rejected. An AHB error response is generated and an interrupt source triggered. When set to 0, the protection region is disabled. |
| 0 | INV_FLD | R/W | 0h | Write Protection Inversion Bit: When set to 1, the protection region defined in the lower and upper write protection registers is inverted meaning it is the region that the system is permitted to write to. When set to 0, the protection region defined in the lower and upper write protection registers is the region that the system is not permitted to write to. |