SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Interrupt Status Register: The status fields in this register are set when the described event occurs and the interrupt is enabled in the mask register. When any of these bit fields are set, the interrupt output is asserted high. The fields are each cleared by writing a 1 to the field. Note that bit fields 6 thru 10 are only valid when legacy SPI mode is active.
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| Instance Name | Physical Address |
|---|---|
| FSS0 | 0FC4 0040h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| IRQ_STAT_RESV_FLD | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| IRQ_STAT_RESV_FLD | ECC_FAIL_FLD | TX_CRC_CHUNK_BRK_FLD | RX_CRC_DATA_VAL_FLD | RX_CRC_DATA_ERR_FLD | |||
| R | R/W1TC | R/W1TC | R/W1TC | R/W1TC | |||
| 0h | 0h | 0h | 0h | 0h | |||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| IRQ_STAT_RESV1_FLD | STIG_REQ_INT_FLD | POLL_EXP_INT_FLD | INDRD_SRAM_FULL_FLD | RX_FIFO_FULL_FLD | RX_FIFO_NOT_EMPTY_FLD | TX_FIFO_FULL_FLD | TX_FIFO_NOT_FULL_FLD |
| R | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RECV_OVERFLOW_FLD | INDIRECT_XFER_LEVEL_BREACH_FLD | ILLEGAL_ACCESS_DET_FLD | PROT_WR_ATTEMPT_FLD | INDIRECT_READ_REJECT_FLD | INDIRECT_OP_DONE_FLD | UNDERFLOW_DET_FLD | MODE_M_FAIL_FLD |
| R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:20 | IRQ_STAT_RESV_FLD | R | 0h | Reserved |
| 19 | ECC_FAIL_FLD | R/W1TC | 0h | ECC failure This interrupt informs the system that Flash Device reported ECC error. |
| 18 | TX_CRC_CHUNK_BRK_FLD | R/W1TC | 0h | TX CRC chunk was broken This interrupt informs the system that program page SPI transfer was discontinued somewhere inside the chunk. |
| 17 | RX_CRC_DATA_VAL_FLD | R/W1TC | 0h | RX CRC data valid New RX CRC data was captured from Flash Device |
| 16 | RX_CRC_DATA_ERR_FLD | R/W1TC | 0h | RX CRC data error CRC data from Flash Device does not correspond to the one dynamically calculated by the controller. |
| 15 | IRQ_STAT_RESV1_FLD | R | 0h | Reserved |
| 14 | STIG_REQ_INT_FLD | R/W1TC | 0h | The controller is ready for getting another STIG request. |
| 13 | POLL_EXP_INT_FLD | R/W1TC | 0h | The maximum number of programmed polls cycles is expired |
| 12 | INDRD_SRAM_FULL_FLD | R/W1TC | 0h | Indirect Read Partition overflow: Indirect Read Partition of SRAM is full and unable to immediately complete indirect operation |
| 11 | RX_FIFO_FULL_FLD | R/W1TC | 0h | Small RX FIFO full: Current FIFO status can be ignored in non-SPI legacy mode 0 : FIFO is not full 1 : FIFO is full |
| 10 | RX_FIFO_NOT_EMPTY_FLD | R/W1TC | 0h | Small RX FIFO not empty: Current FIFO status can be ignored in non-SPI legacy mode 0 : FIFO has less than RX THRESHOLD entries, 1 : FIFO has >= THRESHOLD entries |
| 9 | TX_FIFO_FULL_FLD | R/W1TC | 0h | Small TX FIFO full: Current FIFO status can be ignored in non-SPI legacy mode 0 : FIFO is not full, 1 : FIFO is full |
| 8 | TX_FIFO_NOT_FULL_FLD | R/W1TC | 0h | Small TX FIFO not full: Current FIFO status can be ignored in non-SPI legacy mode 0 : FIFO has >= THRESHOLD entries, 1 : FIFO has less than THRESHOLD entries |
| 7 | RECV_OVERFLOW_FLD | R/W1TC | 0h | Receive Overflow: This should only occur in Legacy SPI mode. Set if an attempt is made to push the RX FIFO when it is full. This bit is reset only by a system reset and cleared only when this register is read. If a new push to the RX FIFO occurs coincident with a register read this flag will remain set. 0 : no overflow has been detected. 1 : an overflow has occurred. |
| 6 | INDIRECT_XFER_LEVEL_BREACH_FLD | R/W1TC | 0h | Indirect Transfer Watermark Level Breached |
| 5 | ILLEGAL_ACCESS_DET_FLD | R/W1TC | 0h | Illegal AHB access has been detected. AHB wrapping bursts and the use of SPLIT/RETRY accesses will cause this error interrupt to trigger. |
| 4 | PROT_WR_ATTEMPT_FLD | R/W1TC | 0h | Write to protected area was attempted and rejected. |
| 3 | INDIRECT_READ_REJECT_FLD | R/W1TC | 0h | Indirect operation was requested but could not be accepted. Two indirect operations already in storage. |
| 2 | INDIRECT_OP_DONE_FLD | R/W1TC | 0h | Indirect Operation Complete: Controller has completed last triggered indirect operation |
| 1 | UNDERFLOW_DET_FLD | R/W1TC | 0h | Underflow Detected: 0 : no underflow has been detected 1 : underflow is detected and an attempt to transfer data is made when the small TX FIFO is empty. This may occur when AHB write data is being supplied too slowly to keep up with the requested write operation This bit is reset only by a system reset and cleared only when the register is read. |
| 0 | MODE_M_FAIL_FLD | R/W1TC | 0h | Mode M Failure: Mode M failure indicates the voltage on pin n_ss_in is inconsistent with the SPI mode. Set =1 if n_ss_in is low in initiator mode [multi-initiator contention]. These conditions will clear the spi_enable bit and disable the SPI. This bit is reset only by a system reset and cleared only when this register is read. 0 : no mode fault has been detected 1 : a mode fault has occurred |