SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Write Completion Control Register: This register defines how the controller will poll the device following a write transfer
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| Instance Name | Physical Address |
|---|---|
| FSS0 | 0FC4 0038h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| POLL_REP_DELAY_FLD | |||||||
| R/W | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| POLL_COUNT_FLD | |||||||
| R/W | |||||||
| 1h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| ENABLE_POLLING_EXP_FLD | DISABLE_POLLING_FLD | POLLING_POLARITY_FLD | WR_COMP_CTRL_RESV1_FLD | POLLING_BIT_INDEX_FLD | |||
| R/W | R/W | R/W | R | R/W | |||
| 0h | 0h | 0h | 0h | 0h | |||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| OPCODE_FLD | |||||||
| R/W | |||||||
| 5h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:24 | POLL_REP_DELAY_FLD | R/W | 0h | Defines additional delay for maintain Chip Select de-asserted during auto-polling phase |
| 23:16 | POLL_COUNT_FLD | R/W | 1h | Defines the number of times the controller should expect to see a true result from the polling in successive reads of the device register. |
| 15 | ENABLE_POLLING_EXP_FLD | R/W | 0h | Set to '1' for enabling auto-polling expiration. |
| 14 | DISABLE_POLLING_FLD | R/W | 0h | This switches off the automatic polling function |
| 13 | POLLING_POLARITY_FLD | R/W | 0h | Defines the polling polarity. If '1', then the write transfer to the device will be complete if the polled bit is equal to '1'. If '0', then the write transfer to the device will be complete if the polled bit is equal to '0'. |
| 12:11 | WR_COMP_CTRL_RESV1_FLD | R | 0h | Reserved |
| 10:8 | POLLING_BIT_INDEX_FLD | R/W | 0h | Defines the bit index that should be polled. A value of 010 means that bit 2 of the returned data will be polled for.A value of 111 means that bit 7 of the returned data will be polled for. |
| 7:0 | OPCODE_FLD | R/W | 5h | Defines the opcode that should be issued by the controller when it is automatically polling for device program completion. This command is issued followed all device write operations. By default, this will poll the standard device STATUS register using opcode 0x05 |