SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Indirect AHB Address Trigger Register
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| Instance Name | Physical Address |
|---|---|
| FSS0 | 0FC4 001Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| ADDR_FLD | |||||||
| R/W | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| ADDR_FLD | |||||||
| R/W | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| ADDR_FLD | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ADDR_FLD | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:0 | ADDR_FLD | R/W | 0h | This is the base address that will be used by the AHB controller. When the incoming AHB read access address matches a range of addresses from this trigger address to the trigger address + 15, then the AHB request will be completed by fetching data from the Indirect Controllers SRAM. |