SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Read Data Capture Register
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| Instance Name | Physical Address |
|---|---|
| FSS0 | 0FC4 0010h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RD_DATA_RESV3_FLD | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RD_DATA_RESV3_FLD | DDR_READ_DELAY_FLD | ||||||
| R | R/W | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RD_DATA_RESV2_FLD | DQS_ENABLE_FLD | ||||||
| R | R/W | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RD_DATA_RESV1_FLD | SAMPLE_EDGE_SEL_FLD | DELAY_FLD | BYPASS_FLD | ||||
| R | R/W | R/W | R/W | ||||
| 0h | 0h | 0h | 1h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:20 | RD_DATA_RESV3_FLD | R | 0h | Reserved |
| 19:16 | DDR_READ_DELAY_FLD | R/W | 0h | DDR read delay: Delay the transmitted data by the programmed number of ref_clk cycles.This field is only relevant when DDR Read Command is executed. Otherwise can be ignored. |
| 15:9 | RD_DATA_RESV2_FLD | R | 0h | Reserved |
| 8 | DQS_ENABLE_FLD | R/W | 0h | DQS enable bit: If enabled, signal from DQS input is driven into RX DLL and is used for data capturing in PHY Mode rather than internally generated gated ref_clk.. |
| 7:6 | RD_DATA_RESV1_FLD | R | 0h | Reserved |
| 5 | SAMPLE_EDGE_SEL_FLD | R/W | 0h | Sample edge selection: Choose edge on which data outputs from flash memory will be sampled |
| 4:1 | DELAY_FLD | R/W | 0h | Read Delay: Delay the read data capturing logic by the programmed number of ref_clk cycles |
| 0 | BYPASS_FLD | R/W | 1h | Bypass the adapted loopback clock circuit |