SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The procedure in Table 12-24 configures the MCASP pins for MCASP functionality.
| Step | Register/Bit Field/Programming Model | Value |
|---|---|---|
| Configure module different pins to have MCASP functionality. | MCASP_PFUNC[31-0] | 0x0 |
| Configure the MCASP pins as outputs: AFSX AHCLKX ACLKX Desired i-th MCASP data pin AXRi is configured as an output for DIT-transmission. | MCASP_PDIR[28] AFSX; MCASP_PDIR[27] AHCLKX; MCASP_PDIR[26] ACLKX; MCASP_PDIR[i] AXRi | 0x1 0x1 0x1 0x1 |