SPRUIE9D May   2017  â€“ May 2024 DRA74P , DRA75P , DRA76P , DRA77P

 

  1.   1
  2.   Read This First
    1.     Support Resources
    2.     About This Manual
    3.     Information About Cautions and Warnings
    4.     Register, Field, and Bit Calls
    5.     Coding Rules
    6.     Flow Chart Rules
    7.     Glossary
    8.     Export Control Notice
    9.     DRA75xP, DRA74xP, DRA77xP, DRA76xP MIPI® Disclaimer
    10.     Trademarks
  3. 1 Introduction
    1. 1.1 DRA75xP, DRA74xP, DRA77xP, DRA76xP Overview
    2. 1.2 DRA75xP, DRA74xP, DRA77xP, DRA76xP Environment
    3. 1.3 DRA75xP, DRA74xP, DRA77xP, DRA76xP Description
      1. 1.3.1  MPU Subsystem
      2. 1.3.2  DSP Subsystems
      3. 1.3.3  EVE Subsystems
      4. 1.3.4  Imaging Subsystem
      5. 1.3.5  Camera Interface Subsystem
      6. 1.3.6  IPU Subsystems
      7. 1.3.7  IVA-HD Subsystem
      8. 1.3.8  Display Subsystem
      9. 1.3.9  Video Processing Subsystem
      10. 1.3.10 Video Capture
      11. 1.3.11 3D GPU Subsystem
      12. 1.3.12 BB2D Subsystem
      13. 1.3.13 On-Chip Debug Support
      14. 1.3.14 Power, Reset, and Clock Management
      15. 1.3.15 On-Chip Memory
      16. 1.3.16 Memory Management
      17. 1.3.17 External Memory Interfaces
      18. 1.3.18 System and Connectivity Peripherals
        1. 1.3.18.1 System Peripherals
        2. 1.3.18.2 Media Connectivity Peripherals
        3. 1.3.18.3 Car Connectivity Peripherals
        4. 1.3.18.4 Audio Connectivity Peripherals
        5. 1.3.18.5 Serial Control Peripherals
        6. 1.3.18.6 Radio Accelerators
    4. 1.4 DRA75xP, DRA74xP, DRA77xP, DRA76xP Family
    5. 1.5 DRA75xP, DRA74xP, DRA77xP, DRA76xP Device Identification
    6. 1.6 DRA75xP, DRA74xP, DRA77xP, DRA76xP Package Characteristics Overview
  4. 2 Memory Mapping
    1. 2.1 Introduction
    2. 2.2 L3_MAIN Memory Map
      1. 2.2.1 L3_INSTR Memory Map
    3. 2.3 L4 Memory Map
      1. 2.3.1 L4_CFG Memory Map
      2. 2.3.2 L4_WKUP Memory Map
    4. 2.4 L4_PER Memory Map
      1. 2.4.1 L4_PER1 Memory Space Mapping
      2. 2.4.2 L4_PER2 Memory Map
      3. 2.4.3 L4_PER3 Memory Map
    5. 2.5 MPU Memory Map
    6. 2.6 IPU Memory Map
    7. 2.7 DSP Memory Map
    8. 2.8 EVE Memory Map
    9. 2.9 TILER View Memory Map
  5. 3 Power, Reset, and Clock Management
    1. 3.1  Device Power Management Introduction
      1. 3.1.1 Device Power-Management Architecture Building Blocks
        1. 3.1.1.1 Clock Management
          1. 3.1.1.1.1 Module Interface and Functional Clocks
          2. 3.1.1.1.2 65
          3. 3.1.1.1.3 Module-Level Clock Management
          4. 3.1.1.1.4 Clock Domain
          5. 3.1.1.1.5 Clock Domain-Level Clock Management
          6. 3.1.1.1.6 Clock Domain HW_AUTO Mode Sequences
          7. 3.1.1.1.7 Clock Domain Sleep/Wake-up
          8. 3.1.1.1.8 Clock Domain Dependency
            1. 3.1.1.1.8.1 Static Dependency
            2. 3.1.1.1.8.2 Dynamic Dependency
            3. 3.1.1.1.8.3 Wake-Up Dependency
        2. 3.1.1.2 Power Management
          1. 3.1.1.2.1 Power Domain
          2. 3.1.1.2.2 Module Logic and Memory Context
          3. 3.1.1.2.3 Power Domain Management
        3. 3.1.1.3 Voltage Management
          1. 3.1.1.3.1 Voltage Domain
          2. 3.1.1.3.2 Voltage Domain Management
          3. 3.1.1.3.3 AVS Overview
            1. 3.1.1.3.3.1 AVS Class 0 (SmartReflexâ„¢) Voltage Control
      2. 3.1.2 Power-Management Techniques
        1. 3.1.2.1 Standby Leakage Management
        2. 3.1.2.2 Dynamic Voltage and Frequency Scaling
        3. 3.1.2.3 Dynamic Power Switching
        4. 3.1.2.4 Adaptive Voltage Scaling
        5. 3.1.2.5 Adaptive Body Bias
        6. 3.1.2.6 SR3-APG (Automatic Power Gating)
        7. 3.1.2.7 Combining Power-Management Techniques
          1. 3.1.2.7.1 DPS Versus SLM
    2. 3.2  PRCM Subsystem Overview
      1. 3.2.1 Introduction
      2. 3.2.2 Power-Management Framework Features
    3. 3.3  PRCM Subsystem Environment
      1. 3.3.1 External Clock Signals
      2. 3.3.2 External Boot Signals
      3. 3.3.3 External Reset Signals
      4. 3.3.4 External Voltage Inputs
    4. 3.4  PRCM Subsystem Integration
      1. 3.4.1 Device Power-Management Layout
      2. 3.4.2 Power-Management Scheme, Reset, and Interrupt Requests
        1. 3.4.2.1 Power Domain
        2. 3.4.2.2 Resets
        3. 3.4.2.3 PRCM Interrupt Requests
        4. 3.4.2.4 107
    5. 3.5  Reset Management Functional Description
      1. 3.5.1 Overview
        1. 3.5.1.1 PRCM Reset Management Functional Description
          1. 3.5.1.1.1 Power-On Reset
          2. 3.5.1.1.2 Warm Reset
        2. 3.5.1.2 PRM Reset Management Functional Description
      2. 3.5.2 General Characteristics of Reset Signals
        1. 3.5.2.1 Scope
        2. 3.5.2.2 Occurrence
        3. 3.5.2.3 Source Type
        4. 3.5.2.4 Retention Type
      3. 3.5.3 Reset Sources
        1. 3.5.3.1 Global Reset Sources
        2. 3.5.3.2 Local Reset Sources
      4. 3.5.4 Reset Logging
      5. 3.5.5 Reset Domains
      6. 3.5.6 Reset Sequences
        1. 3.5.6.1  MPU Subsystem Power-On Reset Sequence
        2. 3.5.6.2  MPU Subsystem Warm Reset Sequence
        3. 3.5.6.3  MPU Subsystem Reset Sequence on Sleep and Wake-Up Transitions From RETENTION State
        4. 3.5.6.4  IVA Subsystem Power-On Reset Sequence
        5. 3.5.6.5  IVA Subsystem Software Warm Reset Sequence
        6. 3.5.6.6  DSP1 Subsystem Power-On Reset Sequence
        7. 3.5.6.7  DSP1 Subsystem Software Warm Reset Sequence
        8. 3.5.6.8  DSP2 Subsystem Power-On Reset Sequence
        9. 3.5.6.9  DSP2 Subsystem Software Warm Reset Sequence
        10. 3.5.6.10 IPU1 Subsystem Power-On Reset Sequence
        11. 3.5.6.11 IPU1 Subsystem Software Warm Reset Sequence
        12. 3.5.6.12 IPU2 Subsystem Power-On Reset Sequence
        13. 3.5.6.13 IPU2 Subsystem Software Warm Reset Sequence
        14. 3.5.6.14 EVE1 Subsystem Power-On Reset Sequence
        15. 3.5.6.15 EVE1 Subsystem Software Warm Reset Sequence
        16. 3.5.6.16 EVE2 Subsystem Power-On Reset Sequence
        17. 3.5.6.17 EVE2 Subsystem Software Warm Reset Sequence
        18. 3.5.6.18 Global Warm Reset Sequence
    6. 3.6  Clock Management Functional Description
      1. 3.6.1 Overview
      2. 3.6.2 External Clock Inputs
        1. 3.6.2.1 FUNC_32K_CLK Clock
        2. 3.6.2.2 High-Frequency System Clock Input
        3. 3.6.2.3 External Reference Clock Input
      3. 3.6.3 Internal Clock Sources and Generators
        1. 3.6.3.1  PRM Clock Source
        2. 3.6.3.2  CM Clock Source
          1. 3.6.3.2.1 CM_CORE_AON Clock Generator
          2. 3.6.3.2.2 CM_CORE_AON_CLKOUTMUX Overview
          3. 3.6.3.2.3 CM_CORE_AON_TIMER Overview
          4. 3.6.3.2.4 CM_CORE_AON_MCASP Overview
        3. 3.6.3.3  Generic DPLL Overview
          1. 3.6.3.3.1 Generic APLL Overview
          2. 3.6.3.3.2 DPLLs Output Clocks Parameters
          3. 3.6.3.3.3 Enable Control, Status, and Low-Power Operation Mode
          4. 3.6.3.3.4 DPLL Power Modes
          5. 3.6.3.3.5 DPLL Recalibration
          6. 3.6.3.3.6 DPLL Output Power Down
        4. 3.6.3.4  DPLL_PER Description
          1. 3.6.3.4.1 DPLL_PER Overview
          2. 3.6.3.4.2 DPLL_PER Synthesized Clock Parameters
          3. 3.6.3.4.3 DPLL_PER Power Modes
          4. 3.6.3.4.4 DPLL_PER Recalibration
        5. 3.6.3.5  DPLL_CORE Description
          1. 3.6.3.5.1 DPLL_CORE Overview
          2. 3.6.3.5.2 DPLL_CORE Synthesized Clock Parameters
          3. 3.6.3.5.3 DPLL_CORE Power Modes
          4. 3.6.3.5.4 DPLL_CORE Recalibration
        6. 3.6.3.6  DPLL_ABE Description
          1. 3.6.3.6.1 DPLL_ABE Overview
          2. 3.6.3.6.2 DPLL_ABE Synthesized Clock Parameters
          3. 3.6.3.6.3 DPLL_ABE Power Modes
          4. 3.6.3.6.4 DPLL_ABE Recalibration
          5. 3.6.3.6.5 Fractional M-factor
        7. 3.6.3.7  DPLL_MPU Description
          1. 3.6.3.7.1 DPLL_MPU Overview
          2. 3.6.3.7.2 DPLL_MPU Tactical Clocking Adjustment
          3. 3.6.3.7.3 DPLL_MPU Synthesized Clock Parameters
          4. 3.6.3.7.4 DPLL_MPU Power Modes
          5. 3.6.3.7.5 DPLL_MPU Recalibration
        8. 3.6.3.8  DPLL_IVA Description
          1. 3.6.3.8.1 DPLL_IVA Overview
          2. 3.6.3.8.2 DPLL_IVA Synthesized Clock Parameters
          3. 3.6.3.8.3 DPLL_IVA Power Modes
          4. 3.6.3.8.4 DPLL_IVA Recalibration
        9. 3.6.3.9  DPLL_USB Description
          1. 3.6.3.9.1 DPLL_USB Overview
          2. 3.6.3.9.2 DPLL_USB Synthesized Clock Parameters
          3. 3.6.3.9.3 DPLL_USB Power Modes
          4. 3.6.3.9.4 DPLL_USB Recalibration
        10. 3.6.3.10 DPLL_EVE Description
          1. 3.6.3.10.1 DPLL_EVE Overview
          2. 3.6.3.10.2 DPLL_EVE Synthesized Clock Parameters
          3. 3.6.3.10.3 DPLL_EVE Power Modes
          4. 3.6.3.10.4 DPLL_EVE Recalibration
        11. 3.6.3.11 DPLL_DSP Description
          1. 3.6.3.11.1 DPLL_DSP Overview
          2. 3.6.3.11.2 DPLL_DSP Synthesized Clock Parameters
          3. 3.6.3.11.3 DPLL_DSP Power Modes
          4. 3.6.3.11.4 DPLL_DSP Recalibration
        12. 3.6.3.12 DPLL_GMAC Description
          1. 3.6.3.12.1 DPLL_GMAC Overview
          2. 3.6.3.12.2 DPLL_GMAC Synthesized Clock Parameters
          3. 3.6.3.12.3 DPLL_GMAC Power Modes
          4. 3.6.3.12.4 DPLL_GMAC Recalibration
        13. 3.6.3.13 DPLL_GPU Description
          1. 3.6.3.13.1 DPLL_GPU Overview
          2. 3.6.3.13.2 DPLL_GPU Synthesized Clock Parameters
          3. 3.6.3.13.3 DPLL_GPU Power Modes
          4. 3.6.3.13.4 DPLL_GPU Recalibration
        14. 3.6.3.14 DPLL_DDR Description
          1. 3.6.3.14.1 DPLL_DDR Overview
          2. 3.6.3.14.2 DPLL_DDR Synthesized Clock Parameters
          3. 3.6.3.14.3 DPLL_DDR Power Modes
          4. 3.6.3.14.4 DPLL_DDR Recalibration
        15. 3.6.3.15 DPLL_PCIE_REF Description
          1. 3.6.3.15.1 DPLL_PCIE_REF Overview
          2. 3.6.3.15.2 DPLL_PCIE_REF Synthesized Clock Parameters
          3. 3.6.3.15.3 DPLL_PCIE_REF Power Modes
        16. 3.6.3.16 APLL_PCIE Description
          1. 3.6.3.16.1 APLL_PCIE Overview
          2. 3.6.3.16.2 APLL_PCIE Synthesized Clock Parameters
          3. 3.6.3.16.3 APLL_PCIE Power Modes
      4. 3.6.4 Clock Domains
        1. 3.6.4.1  CD_WKUPAON Clock Domain
          1. 3.6.4.1.1 Overview
          2. 3.6.4.1.2 Clock Domain Modes
          3. 3.6.4.1.3 Clock Domain Dependency
            1. 3.6.4.1.3.1 Wake-Up Dependency
          4. 3.6.4.1.4 Clock Domain Module Attributes
        2. 3.6.4.2  CD_DSP1 Clock Domain
          1. 3.6.4.2.1 Overview
          2. 3.6.4.2.2 Clock Domain Modes
          3. 3.6.4.2.3 Clock Domain Dependency
            1. 3.6.4.2.3.1 Static Dependency
            2. 3.6.4.2.3.2 Dynamic Dependency
          4. 3.6.4.2.4 Clock Domain Module Attributes
        3. 3.6.4.3  CD_DSP2 Clock Domain
          1. 3.6.4.3.1 Overview
          2. 3.6.4.3.2 Clock Domain Modes
          3. 3.6.4.3.3 Clock Domain Dependency
            1. 3.6.4.3.3.1 Static Dependency
            2. 3.6.4.3.3.2 Dynamic Dependency
          4. 3.6.4.3.4 Clock Domain Module Attributes
        4. 3.6.4.4  CD_CUSTEFUSE Clock Domain
          1. 3.6.4.4.1 Overview
          2. 3.6.4.4.2 Clock Domain Modes
          3. 3.6.4.4.3 Clock Domain Dependency
          4. 3.6.4.4.4 Clock Domain Module Attributes
        5. 3.6.4.5  CD_MPU Clock Domain
          1. 3.6.4.5.1 Overview
          2. 3.6.4.5.2 Clock Domain Modes
          3. 3.6.4.5.3 Clock Domain Dependency
            1. 3.6.4.5.3.1 Static Dependency
            2. 3.6.4.5.3.2 Dynamic Dependency
          4. 3.6.4.5.4 Clock Domain Module Attributes
        6. 3.6.4.6  CD_L4PER1 Clock Domain
          1. 3.6.4.6.1 Overview
          2. 3.6.4.6.2 Clock Domain Modes
          3. 3.6.4.6.3 Clock Domain Dependency
            1. 3.6.4.6.3.1 Dynamic Dependency
            2. 3.6.4.6.3.2 Wake-Up Dependency
          4. 3.6.4.6.4 Clock Domain Module Attributes
        7. 3.6.4.7  CD_L4PER2 Clock Domain
          1. 3.6.4.7.1 Overview
          2. 3.6.4.7.2 Clock Domain Modes
          3. 3.6.4.7.3 Clock Domain Dependency
            1. 3.6.4.7.3.1 Dynamic Dependency
            2. 3.6.4.7.3.2 Wake-Up Dependency
          4. 3.6.4.7.4 Clock Domain Module Attributes
        8. 3.6.4.8  CD_L4PER3 Clock Domain
          1. 3.6.4.8.1 Overview
          2. 3.6.4.8.2 Clock Domain Modes
          3. 3.6.4.8.3 Clock Domain Dependency
            1. 3.6.4.8.3.1 Dynamic Dependency
            2. 3.6.4.8.3.2 Wake-Up Dependency
          4. 3.6.4.8.4 Clock Domain Module Attributes
        9. 3.6.4.9  CD_L4SEC Clock Domain
          1. 3.6.4.9.1 Overview
          2. 3.6.4.9.2 Clock Domain Modes
          3. 3.6.4.9.3 Clock Domain Dependency
            1. 3.6.4.9.3.1 Static Dependency
            2. 3.6.4.9.3.2 Dynamic Dependency
          4. 3.6.4.9.4 Clock Domain Module Attributes
          5. 3.6.4.9.5 289
        10. 3.6.4.10 CD_L3INIT Clock Domain
          1. 3.6.4.10.1 Overview
          2. 3.6.4.10.2 Clock Domain Modes
          3. 3.6.4.10.3 Clock Domain Dependency
            1. 3.6.4.10.3.1 Static Dependency
            2. 3.6.4.10.3.2 Dynamic Dependency
            3. 3.6.4.10.3.3 Wake-Up Dependency
          4. 3.6.4.10.4 Clock Domain Module Attributes
        11. 3.6.4.11 CD_IVA Clock Domain
          1. 3.6.4.11.1 Overview
          2. 3.6.4.11.2 Clock Domain Modes
          3. 3.6.4.11.3 Clock Domain Dependency
            1. 3.6.4.11.3.1 Static Dependency
            2. 3.6.4.11.3.2 Dynamic Dependency
          4. 3.6.4.11.4 Clock Domain Module Attributes
        12. 3.6.4.12 CD_GPU Description
          1. 3.6.4.12.1 Overview
          2. 3.6.4.12.2 Clock Domain Modes
          3. 3.6.4.12.3 Clock Domain Dependency
            1. 3.6.4.12.3.1 Static Dependency
            2. 3.6.4.12.3.2 Dynamic Dependency
          4. 3.6.4.12.4 Clock Domain Module Attributes
        13. 3.6.4.13 CD_EMU Clock Domain
          1. 3.6.4.13.1 Overview
          2. 3.6.4.13.2 Clock Domain Modes
          3. 3.6.4.13.3 Clock Domain Dependency
            1. 3.6.4.13.3.1 Dynamic Dependency
          4. 3.6.4.13.4 Clock Domain Module Attributes
        14. 3.6.4.14 CD_DSS Clock Domain
          1. 3.6.4.14.1 Overview
          2. 3.6.4.14.2 Clock Domain Modes
          3. 3.6.4.14.3 Clock Domain Dependency
            1. 3.6.4.14.3.1 Static Dependency
            2. 3.6.4.14.3.2 Dynamic Dependency
            3. 3.6.4.14.3.3 Wake-Up Dependency
          4. 3.6.4.14.4 Clock Domain Module Attributes
        15. 3.6.4.15 CD_L4_CFG Clock Domain
          1. 3.6.4.15.1 Overview
          2. 3.6.4.15.2 Clock Domain Modes
          3. 3.6.4.15.3 Clock Domain Dependency
            1. 3.6.4.15.3.1 Dynamic Dependency
          4. 3.6.4.15.4 Clock Domain Module Attributes
        16. 3.6.4.16 CD_L3_INSTR Clock Domain
          1. 3.6.4.16.1 Overview
          2. 3.6.4.16.2 Clock Domain Modes
          3. 3.6.4.16.3 Clock Domain Dependency
          4. 3.6.4.16.4 Clock Domain Module Attributes
        17. 3.6.4.17 CD_L3_MAIN1 Clock Domain
          1. 3.6.4.17.1 Overview
          2. 3.6.4.17.2 Clock Domain Modes
          3. 3.6.4.17.3 Clock Domain Dependency
            1. 3.6.4.17.3.1 Dynamic Dependency
          4. 3.6.4.17.4 Clock Domain Module Attributes
        18. 3.6.4.18 CD_EMIF Clock Domain
          1. 3.6.4.18.1 Overview
          2. 3.6.4.18.2 Clock Domain Modes
          3. 3.6.4.18.3 Clock Domain Dependency
          4. 3.6.4.18.4 Clock Domain Module Attributes
        19. 3.6.4.19 CD_IPU Clock Domain
          1. 3.6.4.19.1 Overview
          2. 3.6.4.19.2 Clock Domain Modes
          3. 3.6.4.19.3 Clock Domain Dependency
            1. 3.6.4.19.3.1 Static Dependency
            2. 3.6.4.19.3.2 Dynamic Dependency
          4. 3.6.4.19.4 Clock Domain Module Attributes
        20. 3.6.4.20 CD_IPU1 Clock Domain
          1. 3.6.4.20.1 Overview
          2. 3.6.4.20.2 Clock Domain Modes
          3. 3.6.4.20.3 Clock Domain Dependency
            1. 3.6.4.20.3.1 Static Dependency
            2. 3.6.4.20.3.2 Dynamic Dependency
          4. 3.6.4.20.4 Clock Domain Module Attributes
        21. 3.6.4.21 CD_IPU2 Clock Domain
          1. 3.6.4.21.1 Overview
          2. 3.6.4.21.2 Clock Domain Modes
          3. 3.6.4.21.3 Clock Domain Dependency
            1. 3.6.4.21.3.1 Static Dependency
            2. 3.6.4.21.3.2 Dynamic Dependency
          4. 3.6.4.21.4 Clock Domain Module Attributes
        22. 3.6.4.22 CD_DMA Clock Domain
          1. 3.6.4.22.1 Overview
          2. 3.6.4.22.2 Clock Domain Modes
          3. 3.6.4.22.3 Clock Domain Dependency
            1. 3.6.4.22.3.1 Static Dependency
            2. 3.6.4.22.3.2 Dynamic Dependency
          4. 3.6.4.22.4 Clock Domain Module Attributes
        23. 3.6.4.23 CD_ATL Clock Domain
          1. 3.6.4.23.1 Overview
          2. 3.6.4.23.2 Clock Domain Modes
          3. 3.6.4.23.3 Clock Domain Module Attributes
        24. 3.6.4.24 CD_CAM Clock Domain
          1. 3.6.4.24.1 Overview
          2. 3.6.4.24.2 Clock Domain Modes
          3. 3.6.4.24.3 Clock Domain Dependency
            1. 3.6.4.24.3.1 Static Dependency
            2. 3.6.4.24.3.2 Dynamic Dependency
          4. 3.6.4.24.4 Clock Domain Module Attributes
          5. 3.6.4.24.5 387
        25. 3.6.4.25 CD_GMAC Clock Domain
          1. 3.6.4.25.1 Overview
          2. 3.6.4.25.2 Clock Domain Modes
          3. 3.6.4.25.3 Clock Domain Dependency
            1. 3.6.4.25.3.1 Static Dependency
            2. 3.6.4.25.3.2 Dynamic Dependency
          4. 3.6.4.25.4 Clock Domain Module Attributes
        26. 3.6.4.26 CD_VPE Clock Domain
          1. 3.6.4.26.1 CD_VPE Overview
          2. 3.6.4.26.2 Clock Domain Modes
          3. 3.6.4.26.3 Clock Domain Dependency
            1. 3.6.4.26.3.1 Wake-Up Dependency
          4. 3.6.4.26.4 Clock Domain Module Attributes
        27. 3.6.4.27 CD_EVE1 Clock Domain
          1. 3.6.4.27.1 CD_EVE1 Overview
          2. 3.6.4.27.2 Clock Domain Modes
          3. 3.6.4.27.3 Clock Domain Dependency
            1. 3.6.4.27.3.1 Wake-Up Dependency
          4. 3.6.4.27.4 Clock Domain Module Attributes
        28. 3.6.4.28 CD_EVE2 Clock Domain
          1. 3.6.4.28.1 CD_EVE2 Overview
          2. 3.6.4.28.2 Clock Domain Modes
          3. 3.6.4.28.3 Clock Domain Dependency
            1. 3.6.4.28.3.1 Wake-Up Dependency
          4. 3.6.4.28.4 Clock Domain Module Attributes
        29. 3.6.4.29 CD_EVE3 Clock Domain
          1. 3.6.4.29.1 CD_EVE3 Overview
          2. 3.6.4.29.2 415
          3. 3.6.4.29.3 Clock Domain Modes
          4. 3.6.4.29.4 Clock Domain Dependency
            1. 3.6.4.29.4.1 Wake-Up Dependency
          5. 3.6.4.29.5 Clock Domain Module Attributes
        30. 3.6.4.30 CD_RTC Clock Domain
          1. 3.6.4.30.1 CD_RTC Overview
          2. 3.6.4.30.2 Clock Domain Modes
          3. 3.6.4.30.3 Clock Domain Dependency
            1. 3.6.4.30.3.1 Wake-Up Dependency
          4. 3.6.4.30.4 Clock Domain Module Attributes
        31. 3.6.4.31 CD_PCIE Clock Domain
          1. 3.6.4.31.1 CD_PCIE Overview
          2. 3.6.4.31.2 Clock Domain Modes
          3. 3.6.4.31.3 Clock Domain Dependency
            1. 3.6.4.31.3.1 Wake-Up Dependency
          4. 3.6.4.31.4 Clock Domain Module Attributes
    7. 3.7  Power Management Functional Description
      1. 3.7.1  PD_WKUPAON Description
        1. 3.7.1.1 Power Domain Modes
          1. 3.7.1.1.1 Logic and Memory Area Power Modes
      2. 3.7.2  PD_DSP1 Description
        1. 3.7.2.1 Power Domain Modes
          1. 3.7.2.1.1 Logic and Memory Area Power Modes
          2. 3.7.2.1.2 Logic and Memory Area Power Modes Control and Status
      3. 3.7.3  PD_DSP2 Description
        1. 3.7.3.1 Power Domain Modes
          1. 3.7.3.1.1 Logic and Memory Area Power Modes
          2. 3.7.3.1.2 Logic and Memory Area Power Modes Control and Status
      4. 3.7.4  PD_CUSTEFUSE Description
        1. 3.7.4.1 Power Domain Modes
          1. 3.7.4.1.1 Logic and Memory Area Power Modes
          2. 3.7.4.1.2 Logic and Memory Area Power Modes Control and Status
      5. 3.7.5  PD_MPU Description
        1. 3.7.5.1 Power Domain Modes
          1. 3.7.5.1.1 Logic and Memory Area Power Modes
          2. 3.7.5.1.2 Logic and Memory Area Power Modes Control and Status
          3. 3.7.5.1.3 Power State Override
      6. 3.7.6  PD_IPU Description
        1. 3.7.6.1 Power Domain Modes
          1. 3.7.6.1.1 Logic and Memory Area Power Modes
          2. 3.7.6.1.2 Logic and Memory Area Power Modes Control and Status
      7. 3.7.7  PD_L3INIT Description
        1. 3.7.7.1 Power Domain Modes
          1. 3.7.7.1.1 Logic and Memory Area Power Modes
          2. 3.7.7.1.2 Logic and Memory Area Power Modes Control and Status
      8. 3.7.8  PD_L4PER Description
        1. 3.7.8.1 Power Domain Modes
          1. 3.7.8.1.1 Logic and Memory Area Power Modes
          2. 3.7.8.1.2 Logic and Memory Area Power Modes Control and Status
      9. 3.7.9  PD_IVA Description
        1. 3.7.9.1 Power Domain Modes
          1. 3.7.9.1.1 Logic and Memory Area Power Modes
          2. 3.7.9.1.2 Logic and Memory Area Power Modes Control and Status
      10. 3.7.10 PD_GPU Description
        1. 3.7.10.1 Power Domain Modes
          1. 3.7.10.1.1 Logic and Memory Area Power Modes
          2. 3.7.10.1.2 Logic and Memory Area Power Modes Control and Status
      11. 3.7.11 PD_EMU Description
        1. 3.7.11.1 Power Domain Modes
          1. 3.7.11.1.1 Logic and Memory Area Power Modes
          2. 3.7.11.1.2 Logic and Memory Area Power Modes Control and Status
      12. 3.7.12 PD_DSS Description
        1. 3.7.12.1 Power Domain Modes
          1. 3.7.12.1.1 Logic and Memory Area Power Modes
          2. 3.7.12.1.2 Logic and Memory Area Power Mode Control and Status
      13. 3.7.13 PD_CORE Description
        1. 3.7.13.1 Power Domain Modes
          1. 3.7.13.1.1 Logic and Memory Area Power Modes
          2. 3.7.13.1.2 Logic and Memory Area Power Mode Control and Status
      14. 3.7.14 PD_CAM (Physical PD_COREAON) Description
        1. 3.7.14.1 Power Domain Modes
          1. 3.7.14.1.1 Logic and Memory Area Power Modes
          2. 3.7.14.1.2 Logic and Memory Area Power Mode Control and Status
      15. 3.7.15 PD_MPUAON Description
        1. 3.7.15.1 Power Domain Modes
      16. 3.7.16 PD_MMAON Description
        1. 3.7.16.1 Power Domain Modes
      17. 3.7.17 PD_COREAON Description
        1. 3.7.17.1 Power Domain Modes
      18. 3.7.18 PD_VPE Description
        1. 3.7.18.1 Power Domain Modes
          1. 3.7.18.1.1 Logic and Memory Area Power Modes
          2. 3.7.18.1.2 Logic and Memory Area Power Modes Control and Status
      19. 3.7.19 PD_EVE1 Description
        1. 3.7.19.1 Power Domain Modes
          1. 3.7.19.1.1 Logic and Memory Area Power Modes
          2. 3.7.19.1.2 Logic and Memory Area Power Modes Control and Status
      20. 3.7.20 PD_EVE2 Description
        1. 3.7.20.1 Power Domain Modes
          1. 3.7.20.1.1 Logic and Memory Area Power Modes
          2. 3.7.20.1.2 Logic and Memory Area Power Modes Control and Status
      21. 3.7.21 PD_EVE3 Description
        1. 3.7.21.1 Power Domain Modes
          1. 3.7.21.1.1 Logic and Memory Area Power Modes
          2. 3.7.21.1.2 Logic and Memory Area Power Modes Control and Status
      22. 3.7.22 PD_RTC Description
        1. 3.7.22.1 Power Domain Modes
          1. 3.7.22.1.1 Logic and Memory Area Power Modes
    8. 3.8  Voltage-Management Functional Description
      1. 3.8.1 Overview
      2. 3.8.2 Voltage-Control Architecture
      3. 3.8.3 Internal LDOs Control
        1. 3.8.3.1 VDD_MPU_L, VDD_CORE_L, and VDD_IVAHD_L, VDD_GPU_L, VDD_DSPEVE_L Control
          1. 3.8.3.1.1 Adaptive Voltage Scaling
            1. 3.8.3.1.1.1 SmartReflex in the Device
        2. 3.8.3.2 Memory LDOs
        3. 3.8.3.3 ABB LDOs Control
        4. 3.8.3.4 ABB LDO Programming Sequence
          1. 3.8.3.4.1 ABB LDO Enable Sequence
          2. 3.8.3.4.2 ABB LDO Disable Sequence (Entering in Bypass Mode)
        5. 3.8.3.5 BANDGAPs Control
      4. 3.8.4 DVFS
    9. 3.9  Device Low-Power States
      1. 3.9.1 Device Wake-Up Source Summary
      2. 3.9.2 Wakeup Upon Global Warm Reset
      3. 3.9.3 Global Warm Reset During a Device Wake-Up Sequence
      4. 3.9.4 I/O Management
        1. 3.9.4.1 Isolation / Wakeup Sequence
          1. 3.9.4.1.1 Software-Controlled I/O Isolation
    10. 3.10 PRCM Module Programming Guide
      1. 3.10.1 DPLLs Low-Level Programming Models
        1. 3.10.1.1 Global Initialization
          1. 3.10.1.1.1 Surrounding Module Global Initialization
          2. 3.10.1.1.2 DPLL Global Initialization
            1. 3.10.1.1.2.1 Main Sequence – DPLL Global Initialization
            2. 3.10.1.1.2.2 Subsequence – Recalibration Parameter Configuration
            3. 3.10.1.1.2.3 Subsequence – Synthesized Clock Parameter Configuration
            4. 3.10.1.1.2.4 Subsequence – Output Clock Parameter Configuration
        2. 3.10.1.2 DPLL Output Frequency Change
      2. 3.10.2 Clock Management Low-Level Programming Models
        1. 3.10.2.1 Global Initialization
          1. 3.10.2.1.1 Surrounding Module Global Initialization
          2. 3.10.2.1.2 Clock Management Global Initialization
            1. 3.10.2.1.2.1 Main Sequence – Clock Domain Global Initialization
            2. 3.10.2.1.2.2 Subsequence – Slave Module Clock-Management Parameters Configuration
        2. 3.10.2.2 Clock Domain Sleep Transition and Troubleshooting
        3. 3.10.2.3 Enable/Disable Software-Programmable Static Dependency
      3. 3.10.3 Power Management Low-Level Programming Models
        1. 3.10.3.1 Global Initialization
          1. 3.10.3.1.1 Surrounding Module Global Initialization
          2. 3.10.3.1.2 Power Management Global Initialization
            1. 3.10.3.1.2.1 Main Sequence – Power Domain Global Initialization and Setting
        2. 3.10.3.2 Forced Memory Area State Change With Power Domain ON
        3. 3.10.3.3 Forced Power Domain Low-Power State Transition
    11. 3.11 560
    12. 3.12 PRCM Software Configuration for OPP_PLUS
    13. 3.13 PRCM Register Manual
      1. 3.13.1  PRCM Instance Summary
      2. 3.13.2  CM_CORE_AON__CKGEN Registers
        1. 3.13.2.1 CM_CORE_AON__CKGEN Register Summary
        2. 3.13.2.2 CM_CORE_AON__CKGEN Register Description
      3. 3.13.3  CM_CORE_AON__DSP1 Registers
        1. 3.13.3.1 CM_CORE_AON__DSP1 Register Summary
        2. 3.13.3.2 CM_CORE_AON__DSP1 Register Description
      4. 3.13.4  CM_CORE_AON__DSP2 Registers
        1. 3.13.4.1 CM_CORE_AON__DSP2 Register Summary
        2. 3.13.4.2 CM_CORE_AON__DSP2 Register Description
      5. 3.13.5  CM_CORE_AON__EVE1 Registers
        1. 3.13.5.1 CM_CORE_AON__EVE1 Register Summary
        2. 3.13.5.2 CM_CORE_AON__EVE1 Register Description
      6. 3.13.6  CM_CORE_AON__EVE2 Registers
        1. 3.13.6.1 CM_CORE_AON__EVE2 Register Summary
        2. 3.13.6.2 CM_CORE_AON__EVE2 Register Description
      7. 3.13.7  CORE_AON__EVE3 Registers
        1. 3.13.7.1 CM_CORE_AON__EVE3 Register Summary
        2. 3.13.7.2 CM_CORE_AON__EVE3 Register Description
      8. 3.13.8  CM_CORE_AON__INSTR Registers
        1. 3.13.8.1 CM_CORE_AON__INSTR Register Summary
        2. 3.13.8.2 CM_CORE_AON__INSTR Register Description
      9. 3.13.9  CM_CORE_AON__IPU Registers
        1. 3.13.9.1 CM_CORE_AON__IPU Register Summary
        2. 3.13.9.2 CM_CORE_AON__IPU Register Description
      10. 3.13.10 CM_CORE_AON__MPU Registers
        1. 3.13.10.1 CM_CORE_AON__MPU Register Summary
        2. 3.13.10.2 CM_CORE_AON__MPU Register Description
      11. 3.13.11 CM_CORE_AON__OCP_SOCKET Registers
        1. 3.13.11.1 CM_CORE_AON__OCP_SOCKET Register Summary
        2. 3.13.11.2 CM_CORE_AON__OCP_SOCKET Register Description
      12. 3.13.12 CM_CORE_AON__RESTORE Registers
        1. 3.13.12.1 CM_CORE_AON__RESTORE Register Summary
        2. 3.13.12.2 CM_CORE_AON__RESTORE Register Description
      13. 3.13.13 CM_CORE_AON__RTC Registers
        1. 3.13.13.1 CM_CORE_AON__RTC Register Summary
        2. 3.13.13.2 CM_CORE_AON__RTC Register Description
      14. 3.13.14 CM_CORE_AON__VPE Registers
        1. 3.13.14.1 CM_CORE_AON__VPE Register Summary
        2. 3.13.14.2 CM_CORE_AON__VPE Register Description
      15. 3.13.15 CM_CORE__CAM Registers
        1. 3.13.15.1 CM_CORE__CAM Register Summary
        2. 3.13.15.2 CM_CORE__CAM Register Description
      16. 3.13.16 CM_CORE__CKGEN Registers
        1. 3.13.16.1 CM_CORE__CKGEN Register Summary
        2. 3.13.16.2 CM_CORE__CKGEN Register Description
      17. 3.13.17 CM_CORE__COREAON Registers
        1. 3.13.17.1 CM_CORE__COREAON Register Summary
        2. 3.13.17.2 CM_CORE__COREAON Register Description
      18. 3.13.18 CM_CORE__CORE Registers
        1. 3.13.18.1 CM_CORE__CORE Register Summary
        2. 3.13.18.2 CM_CORE__CORE Register Description
      19. 3.13.19 CM_CORE__CUSTEFUSE Registers
        1. 3.13.19.1 CM_CORE__CUSTEFUSE Register Summary
        2. 3.13.19.2 CM_CORE__CUSTEFUSE Register Description
      20. 3.13.20 CM_CORE__DSS Registers
        1. 3.13.20.1 CM_CORE__DSS Register Summary
        2. 3.13.20.2 CM_CORE__DSS Register Description
      21. 3.13.21 CM_CORE__GPU Registers
        1. 3.13.21.1 CM_CORE__GPU Register Summary
        2. 3.13.21.2 CM_CORE__GPU Register Description
      22. 3.13.22 CM_CORE__IVA Registers
        1. 3.13.22.1 CM_CORE__IVA Register Summary
        2. 3.13.22.2 CM_CORE__IVA Register Description
      23. 3.13.23 CM_CORE__L3INIT Registers
        1. 3.13.23.1 CM_CORE__L3INIT Register Summary
        2. 3.13.23.2 CM_CORE__L3INIT Register Description
      24. 3.13.24 CM_CORE__L4PER Registers
        1. 3.13.24.1 CM_CORE__L4PER Register Summary
        2. 3.13.24.2 CM_CORE__L4PER Register Description
      25. 3.13.25 CM_CORE__OCP_SOCKET Registers
        1. 3.13.25.1 CM_CORE__OCP_SOCKET Register Summary
        2. 3.13.25.2 CM_CORE__OCP_SOCKET Register Description
      26. 3.13.26 CM_CORE__RESTORE Registers
        1. 3.13.26.1 CM_CORE__RESTORE Register Summary
        2. 3.13.26.2 CM_CORE__RESTORE Register Description
      27. 3.13.27 CAM_PRM Registers
        1. 3.13.27.1 CAM_PRM Register Summary
        2. 3.13.27.2 CAM_PRM Register Description
      28. 3.13.28 CKGEN_PRM Registers
        1. 3.13.28.1 CKGEN_PRM Register Summary
        2. 3.13.28.2 CKGEN_PRM Register Description
      29. 3.13.29 CORE_PRM Registers
        1. 3.13.29.1 CORE_PRM Register Summary
        2. 3.13.29.2 CORE_PRM Register Description
      30. 3.13.30 CUSTEFUSE_PRM Registers
        1. 3.13.30.1 CUSTEFUSE_PRM Register Summary
        2. 3.13.30.2 CUSTEFUSE_PRM Register Description
      31. 3.13.31 DEVICE_PRM Registers
        1. 3.13.31.1 DEVICE_PRM Register Summary
        2. 3.13.31.2 DEVICE_PRM Register Description
      32. 3.13.32 DSP1_PRM Registers
        1. 3.13.32.1 DSP1_PRM Register Summary
        2. 3.13.32.2 DSP1_PRM Register Description
      33. 3.13.33 DSP2_PRM Registers
        1. 3.13.33.1 DSP2_PRM Register Summary
        2. 3.13.33.2 DSP2_PRM Register Description
      34. 3.13.34 DSS_PRM Registers
        1. 3.13.34.1 DSS_PRM Register Summary
        2. 3.13.34.2 DSS_PRM Register Description
      35. 3.13.35 EMU_CM Registers
        1. 3.13.35.1 EMU_CM Register Summary
        2. 3.13.35.2 EMU_CM Register Description
      36. 3.13.36 EMU_PRM Registers
        1. 3.13.36.1 EMU_PRM Register Summary
        2. 3.13.36.2 EMU_PRM Register Description
      37. 3.13.37 EVE1_PRM Registers
        1. 3.13.37.1 EVE1_PRM Register Summary
        2. 3.13.37.2 EVE1_PRM Register Description
      38. 3.13.38 EVE2_PRM Registers
        1. 3.13.38.1 EVE2_PRM Register Summary
        2. 3.13.38.2 EVE2_PRM Register Description
      39. 3.13.39 EVE3_PRM Registers
        1. 3.13.39.1 EVE3_PRM Register Summary
        2. 3.13.39.2 EVE3_PRM Register Description
      40. 3.13.40 GPU_PRM Registers
        1. 3.13.40.1 GPU_PRM Register Summary
        2. 3.13.40.2 GPU_PRM Register Description
      41. 3.13.41 INSTR_PRM Registers
        1. 3.13.41.1 INSTR_PRM Register Summary
        2. 3.13.41.2 INSTR_PRM Register Description
      42. 3.13.42 IPU_PRM Registers
        1. 3.13.42.1 IPU_PRM Register Summary
        2. 3.13.42.2 IPU_PRM Register Description
      43. 3.13.43 IVA_PRM Registers
        1. 3.13.43.1 IVA_PRM Register Summary
        2. 3.13.43.2 IVA_PRM Register Description
      44. 3.13.44 L3INIT_PRM Registers
        1. 3.13.44.1 L3INIT_PRM Register Summary
        2. 3.13.44.2 L3INIT_PRM Register Description
      45. 3.13.45 L4PER_PRM Registers
        1. 3.13.45.1 L4PER_PRM Register Summary
        2. 3.13.45.2 L4PER_PRM Register Description
      46. 3.13.46 MPU_PRM Registers
        1. 3.13.46.1 MPU_PRM Register Summary
        2. 3.13.46.2 MPU_PRM Register Description
      47. 3.13.47 OCP_SOCKET_PRM Registers
        1. 3.13.47.1 OCP_SOCKET_PRM Register Summary
        2. 3.13.47.2 OCP_SOCKET_PRM Register Description
      48. 3.13.48 RTC_PRM Registers
        1. 3.13.48.1 RTC_PRM Register Summary
        2. 3.13.48.2 RTC_PRM Register Description
      49. 3.13.49 VPE_PRM Registers
        1. 3.13.49.1 VPE_PRM Register Summary
        2. 3.13.49.2 VPE_PRM Register Description
      50. 3.13.50 WKUPAON_CM Registers
        1. 3.13.50.1 WKUPAON_CM Register Summary
        2. 3.13.50.2 WKUPAON_CM Register Description
      51. 3.13.51 WKUPAON_PRM Registers
        1. 3.13.51.1 WKUPAON_PRM Register Summary
        2. 3.13.51.2 WKUPAON_PRM Register Description
  6. 4 Dual Cortex-A15 MPU Subsystem
    1. 4.1 Dual Cortex-A15 MPU Subsystem Overview
      1. 4.1.1 Introduction
      2. 4.1.2 Features
    2. 4.2 Dual Cortex-A15 MPU Subsystem Integration
      1. 4.2.1 Clock Distribution
      2. 4.2.2 Reset Distribution
    3. 4.3 Dual Cortex-A15 MPU Subsystem Functional Description
      1. 4.3.1 MPU Subsystem Block Diagram
      2. 4.3.2 Cortex-A15 MPCore (MPU_CLUSTER)
        1. 4.3.2.1 MPU L2 Cache Memory System
          1. 4.3.2.1.1 MPU L2 Cache Architecture
          2. 4.3.2.1.2 MPU L2 Cache Controller
          3. 4.3.2.1.3 727
      3. 4.3.3 MPU_AXI2OCP
      4. 4.3.4 Memory Adapter
        1. 4.3.4.1 MPU_MA Overview
        2. 4.3.4.2 AXI Input Interface
        3. 4.3.4.3 Interleaving
          1. 4.3.4.3.1 High-Order Fixed Interleaving Model
          2. 4.3.4.3.2 Lower 2-GiB Programmable Interleaving Model
          3. 4.3.4.3.3 Local Interconnect and Synchronization Agent (LISA) Section Manager
          4. 4.3.4.3.4 MA_LSM Registers
          5. 4.3.4.3.5 Posted and Nonposted Writes
          6. 4.3.4.3.6 Errors
        4. 4.3.4.4 Statistics Collector Probe Ports
        5. 4.3.4.5 MPU_MA Firewall
        6. 4.3.4.6 MPU_MA Power and Reset Management
        7. 4.3.4.7 MPU_MA Watchpoint
          1. 4.3.4.7.1 Watchpoint Types
          2. 4.3.4.7.2 Transaction Filtering Options
          3. 4.3.4.7.3 Transaction Match Effects
          4. 4.3.4.7.4 Trigger Generation
          5. 4.3.4.7.5 Programming Options Summary
      5. 4.3.5 Realtime Counter (Master Counter)
        1. 4.3.5.1 Counter Operation
        2. 4.3.5.2 Frequency Change Procedure
      6. 4.3.6 MPU Watchdog Timer
      7. 4.3.7 MPU Subsystem Power Management
        1. 4.3.7.1 Power Domains
        2. 4.3.7.2 Power States of MPU_Cx
        3. 4.3.7.3 Power States of MPU Subsystem
        4. 4.3.7.4 MPU_WUGEN
        5. 4.3.7.5 Power Transition Sequence
        6. 4.3.7.6 SR3-APG Technology Fail-Safe Mode
      8. 4.3.8 MPU Subsystem AMBA Interface Configuration
    4. 4.4 Dual Cortex-A15 MPU Subsystem Register Manual
      1. 4.4.1  Dual Cortex-A15 MPU Subsystem Instance Summary
      2. 4.4.2  MPU_CS_STM Registers
      3. 4.4.3  MPU_INTC Registers
      4. 4.4.4  MPU_PRCM_OCP_SOCKET Registers
        1. 4.4.4.1 MPU_PRCM_OCP_SOCKET Register Summary
        2. 4.4.4.2 MPU_PRCM_OCP_SOCKET Register Description
      5. 4.4.5  MPU_PRCM_DEVICE Registers
        1. 4.4.5.1 MPU_PRCM_DEVICE Register Summary
        2. 4.4.5.2 MPU_PRCM_DEVICE Register Description
      6. 4.4.6  MPU_PRCM_PRM_C0 Registers
        1. 4.4.6.1 MPU_PRCM_PRM_C0 Register Summary
        2. 4.4.6.2 MPU_PRCM_PRM_C0 Register Description
      7. 4.4.7  MPU_PRCM_CM_C0 Registers
        1. 4.4.7.1 MPU_PRCM_CM_C0 Register Summary
        2. 4.4.7.2 MPU_PRCM_CM_C0 Register Description
      8. 4.4.8  MPU_PRCM_PRM_C1 Registers
        1. 4.4.8.1 MPU_PRCM_PRM_C1 Register Summary
        2. 4.4.8.2 MPU_PRCM_PRM_C1 Register Description
      9. 4.4.9  MPU_PRCM_CM_C1 Registers
        1. 4.4.9.1 MPU_PRCM_CM_C1 Register Summary
        2. 4.4.9.2 MPU_PRCM_CM_C1 Register Description
      10. 4.4.10 MPU_WUGEN Registers
        1. 4.4.10.1 MPU_WUGEN Register Summary
        2. 4.4.10.2 MPU_WUGEN Register Description
      11. 4.4.11 MPU_WD_TIMER Registers
        1. 4.4.11.1 MPU_WD_TIMER Register Summary
        2. 4.4.11.2 MPU_WD_TIMER Register Description
      12. 4.4.12 MPU_AXI2OCP_MISC Registers
        1. 4.4.12.1 MPU_AXI2OCP_MISC Register Summary
        2. 4.4.12.2 MPU_AXI2OCP_MISC Register Description
      13. 4.4.13 MPU_MA_LSM Registers
        1. 4.4.13.1 MPU_MA_LSM Register Summary
        2. 4.4.13.2 MPU_MA_LSM Register Description
      14. 4.4.14 MPU_MA_WP Registers
        1. 4.4.14.1 MPU_MA_WP Register Summary
        2. 4.4.14.2 MPU_MA_WP Register Description
  7. 5 DSP Subsystems
    1. 5.1 DSP Subsystems Overview
      1. 5.1.1 DSP Subsystems Key Features
    2. 5.2 DSP Subsystem Integration
    3. 5.3 DSP Subsystems Functional Description
      1. 5.3.1  DSP Subsystems Block Diagram
      2. 5.3.2  DSP Subsystem Components
        1. 5.3.2.1 C66x DSP Subsystem Introduction
        2. 5.3.2.2 DSP TMS320C66x CorePac
          1. 5.3.2.2.1 DSP TMS320C66x CorePac CPU
          2. 5.3.2.2.2 DSP TMS320C66x CorePac Internal Memory Controllers and Memories
            1. 5.3.2.2.2.1 Level 1 Memories
            2. 5.3.2.2.2.2 Level 2 Memory
          3. 5.3.2.2.3 DSP C66x CorePac Internal Peripherals
            1. 5.3.2.2.3.1 DSP C66x CorePac Interrupt Controller (DSP INTC)
            2. 5.3.2.2.3.2 DSP C66x CorePac Power-Down Controller (DSP PDC)
            3. 5.3.2.2.3.3 DSP C66x CorePac Bandwidth Manager (BWM)
            4. 5.3.2.2.3.4 DSP C66x CorePac Memory Protection Hardware
            5. 5.3.2.2.3.5 DSP C66x CorePac Internal DMA (IDMA) Controller
            6. 5.3.2.2.3.6 DSP C66x CorePac External Memory Controller
            7. 5.3.2.2.3.7 DSP C66x CorePac Extended Memory Controller
              1. 5.3.2.2.3.7.1 XMC MDMA Accesses at DSP System Level
                1. 5.3.2.2.3.7.1.1 DSP System MPAX Logic
                2. 5.3.2.2.3.7.1.2 MDMA Non-Post Override Control
            8. 5.3.2.2.3.8 L1P Memory Error Detection Logic
            9. 5.3.2.2.3.9 L2 Memory Error Detection and Correction Logic
        3. 5.3.2.3 DSP Debug and Trace Support
          1. 5.3.2.3.1 DSP Advanced Event Triggering (AET)
          2. 5.3.2.3.2 DSP Trace Support
          3. 5.3.2.3.3 826
      3. 5.3.3  DSP System Control Logic
        1. 5.3.3.1 DSP System Clocks
        2. 5.3.3.2 DSP Hardware Resets
        3. 5.3.3.3 DSP Software Resets
        4. 5.3.3.4 DSP Power Management
          1. 5.3.3.4.1 DSP System Powerdown Protocols
          2. 5.3.3.4.2 DSP Software and Hardware Power Down Sequence Overview
          3. 5.3.3.4.3 DSP IDLE Wakeup
          4. 5.3.3.4.4 DSP SYSTEM IRQWAKEEN registers
          5. 5.3.3.4.5 DSP Automatic Power Transition
      4. 5.3.4  DSP Interrupt Requests
        1. 5.3.4.1 DSP Input Interrupts
          1. 5.3.4.1.1 DSP Non-maskable Interrupt Input
        2. 5.3.4.2 DSP Event and Interrupt Generation Outputs
          1. 5.3.4.2.1 DSP MDMA and DSP EDMA Mflag Event Outputs
          2. 5.3.4.2.2 DSP Aggregated Error Interrupt Output
          3. 5.3.4.2.3 Non-DSP C66x CorePac Generated Peripheral Interrupt Outputs
      5. 5.3.5  DSP DMA Requests
        1. 5.3.5.1 DSP EDMA Wakeup Interrupt
      6. 5.3.6  DSP Intergated Memory Management Units
        1. 5.3.6.1 DSP MMUs Overview
        2. 5.3.6.2 Routing MDMA Traffic through DSP MMU0
        3. 5.3.6.3 Routing EDMA Traffic thorugh DSP MMU1
      7. 5.3.7  DSP Integrated EDMA Subsystem
        1. 5.3.7.1 DSP EDMA Overview
        2. 5.3.7.2 DSP System and Device Level Settings of DSP EDMA
      8. 5.3.8  DSP L2 interconnect Network
        1. 5.3.8.1 DSP Public Firewall Settings
        2. 5.3.8.2 DSP NoC Flag Mux and Error Log Registers
        3. 5.3.8.3 DSP NoC Arbitration
      9. 5.3.9  DSP Boot Configuration
      10. 5.3.10 DSP Internal and External Memory Views
        1. 5.3.10.1 C66x CPU View of the Address Space
        2. 5.3.10.2 DSP_EDMA View of the Address Space
        3. 5.3.10.3 L3_MAIN View of the DSP Address Space
    4. 5.4 DSP Subsystem Register Manual
      1. 5.4.1 DSP Subsystem Instance Summary
      2. 5.4.2 DSP_ICFG Registers
        1. 5.4.2.1 DSP_ICFG Register Summary
        2. 5.4.2.2 DSP_ICFG Register Description
      3. 5.4.3 DSP_SYSTEM Registers
        1. 5.4.3.1 DSP_SYSTEM Register Summary
        2. 5.4.3.2 DSP_SYSTEM Register Description
      4. 5.4.4 DSP_FW_L2_NOC_CFG Registers
        1. 5.4.4.1 DSP_FW_L2_NOC_CFG Register Summary
        2. 5.4.4.2 DSP_FW_L2_NOC_CFG Register Description
  8. 6 IVA Subsystem
  9. 7 Dual Cortex-M4 IPU Subsystem
    1. 7.1 Dual Cortex-M4 IPU Subsystem Overview
      1. 7.1.1 Introduction
      2. 7.1.2 Features
    2. 7.2 Dual Cortex-M4 IPU Subsystem Integration
      1. 7.2.1 Dual Cortex-M4 IPU Subsystem Clock and Reset Distribution
        1. 7.2.1.1 Clock Distribution
        2. 7.2.1.2 Reset Distribution
    3. 7.3 Dual Cortex-M4 IPU Subsystem Functional Description
      1. 7.3.1 IPUx Subsystem Block Diagram
      2. 7.3.2 Power Management
        1. 7.3.2.1 Local Power Management
        2. 7.3.2.2 Power Domains
        3. 7.3.2.3 887
        4. 7.3.2.4 Voltage Domain
        5. 7.3.2.5 Power States and Modes
        6. 7.3.2.6 Wake-Up Generator (IPUx_WUGEN)
          1. 7.3.2.6.1 IPUx_WUGEN Main Features
      3. 7.3.3 IPUx_UNICACHE
      4. 7.3.4 IPUx_UNICACHE_MMU
      5. 7.3.5 IPUx_UNICACHE_SCTM
        1. 7.3.5.1 Counter Functions
          1. 7.3.5.1.1 Input Events
          2. 7.3.5.1.2 Counters
            1. 7.3.5.1.2.1 Counting Modes
            2. 7.3.5.1.2.2 Counter Overflow
            3. 7.3.5.1.2.3 Counters and Processor State
            4. 7.3.5.1.2.4 Chaining Counters
            5. 7.3.5.1.2.5 Enabling and Disabling Counters
            6. 7.3.5.1.2.6 Resetting Counters
        2. 7.3.5.2 Timer Functions
          1. 7.3.5.2.1 Periodic Intervals
          2. 7.3.5.2.2 Event Generation
      6. 7.3.6 IPUx_MMU
        1. 7.3.6.1 IPUx_MMU Behavior on Page-Fault in IPUx Subsystem
      7. 7.3.7 Interprocessor Communication (IPC)
        1. 7.3.7.1 Use of WFE and SEV
        2. 7.3.7.2 Use of Interrupt for IPC
        3. 7.3.7.3 Use of the Bit-Band Feature for Semaphore Operations
        4. 7.3.7.4 Private Memory Space
      8. 7.3.8 IPU Boot Options
    4. 7.4 Dual Cortex-M4 IPU Subsystem Register Manual
      1. 7.4.1 IPUx Subsystem Instance Summary
      2. 7.4.2 IPUx_UNICACHE_CFG Registers
        1. 7.4.2.1 IPUx_UNICACHE_CFG Register Summary
        2. 7.4.2.2 IPUx_UNICACHE_CFG Register Description
      3. 7.4.3 IPUx_UNICACHE_SCTM Registers
        1. 7.4.3.1 IPUx_UNICACHE_SCTM Register Summary
        2. 7.4.3.2 IPUx_UNICACHE_SCTM Register Description
      4. 7.4.4 IPUx_UNICACHE_MMU (AMMU) Registers
        1. 7.4.4.1 IPUx_UNICACHE_MMU (AMMU) Register Summary
        2. 7.4.4.2 IPUx_UNICACHE_MMU (AMMU) Register Description
      5. 7.4.5 IPUx_MMU Registers
      6. 7.4.6 IPUx_Cx_INTC Registers
      7. 7.4.7 IPUx_WUGEN Registers
        1. 7.4.7.1 IPUx_WUGEN Register Summary
        2. 7.4.7.2 IPUx_WUGEN Register Description
      8. 7.4.8 IPUx_Cx_RW_TABLE Registers
        1. 7.4.8.1 IPUx_Cx_RW_TABLE Register Summary
        2. 7.4.8.2 IPUx_Cx_RW_TABLE Register Description
  10. 8 Embedded Vision Engine
    1. 8.1 Embedded Vision Engine (EVE) Subsystem
      1. 8.1.1 EVE Overview
        1. 8.1.1.1 EVE Memories
      2. 8.1.2 EVE Integration
        1. 8.1.2.1 Multi-EVE Recommended Connections
      3. 8.1.3 EVE Functional Description
        1. 8.1.3.1  EVE Connection ID (ConnID) Mapping
        2. 8.1.3.2  EVE Processors Overview
          1. 8.1.3.2.1 Scalar Core (ARP32)
          2. 8.1.3.2.2 VCOP
          3. 8.1.3.2.3 Scalar-Vector Interaction
        3. 8.1.3.3  Internal Memory Overview
          1. 8.1.3.3.1 Program Cache/Memory
          2. 8.1.3.3.2 ARP32 Data Memory (DMEM)
          3. 8.1.3.3.3 WBUF
          4. 8.1.3.3.4 Image Buffers–IBUFLA, IBUFLB, IBUFHA, and IBUFHB
          5. 8.1.3.3.5 Memory Switch Error Registers
          6. 8.1.3.3.6 Memory Error Detection
            1. 8.1.3.3.6.1 Captured Address – EDADDR and EDADDR_BO
            2. 8.1.3.3.6.2 Modes of Operation
            3. 8.1.3.3.6.3 Parity Error Testability
            4. 8.1.3.3.6.4 Parity Error Recovery
          7. 8.1.3.3.7 VCOP System Error Halt Conditions
        4. 8.1.3.4  Program Cache Architecture
          1. 8.1.3.4.1 Basic Operation
          2. 8.1.3.4.2 Line Buffer
          3. 8.1.3.4.3 Software Direct Preload
          4. 8.1.3.4.4 User Coherence Operation
            1. 8.1.3.4.4.1 Global Invalidate
            2. 8.1.3.4.4.2 Range-Based Invalidate
            3. 8.1.3.4.4.3 Single-Address Invalidate – For Breakpoint Operation
          5. 8.1.3.4.5 Demand-Based Prefetch
          6. 8.1.3.4.6 Debug Support
            1. 8.1.3.4.6.1 Read/Write Accessibility through OCP Debug Target Port
            2. 8.1.3.4.6.2 Breakpoint Support
            3. 8.1.3.4.6.3 Cache Profiling
          7. 8.1.3.4.7 Error Detection
        5. 8.1.3.5  EDMA
          1. 8.1.3.5.1 DMA Channel Events
          2. 8.1.3.5.2 DMA Parameter Set
          3. 8.1.3.5.3 Channel Controller
          4. 8.1.3.5.4 EVE-Level Bus Width and Throughput
            1. 8.1.3.5.4.1 Concurrent Transfer Requirements
        6. 8.1.3.6  General-Purpose Inputs/Outputs
        7. 8.1.3.7  CME Signaling
        8. 8.1.3.8  Multi-EVE and VIP Usage Models
          1. 8.1.3.8.1 Data Partitioning
          2. 8.1.3.8.2 Task Partitioning
          3. 8.1.3.8.3 983
        9. 8.1.3.9  Memory Management Unit
        10. 8.1.3.10 Interrupt Control
          1. 8.1.3.10.1 EVE Interrupt Sources – Memory Switch and Parity Error Interrupts
          2. 8.1.3.10.2 ARP32 INTC
          3. 8.1.3.10.3 Output Interrupt Reduction
          4. 8.1.3.10.4 End of Interrupt Mapping
        11. 8.1.3.11 Interprocessor Communication
          1. 8.1.3.11.1 Mailbox Configuration
            1. 8.1.3.11.1.1 Mailbox 0 – EVE to DSP1, DSP2 and MPU
            2. 8.1.3.11.1.2 Mailbox 1 – EVE to Other Hosts
            3. 8.1.3.11.1.3 Mailbox 2 – EVE to EVE in a 2x EVE System
        12. 8.1.3.12 Powerdown
          1. 8.1.3.12.1 Extended Duration Sleep
            1. 8.1.3.12.1.1 Sequence Overview
            2. 8.1.3.12.1.2 Idle Protocol Overview
            3. 8.1.3.12.1.3 Mstandby Protocol Overview
            4. 8.1.3.12.1.4 IDLE Wakeup
        13. 8.1.3.13 Hardware-Assisted Software Self-Test – MISRs
          1. 8.1.3.13.1 Mapping of MISRs to Different Width Buses
          2. 8.1.3.13.2 Detection of Valid Address and Data Cycles
          3. 8.1.3.13.3 Creating a Unique Signature – Software Self-Test Implications
          4. 8.1.3.13.4 Multipass Tests Using WBUF MISR
        14. 8.1.3.14 Error Recovery – ARP32 and OCP Disconnect
          1. 8.1.3.14.1 ARP32 Disconnect
          2. 8.1.3.14.2 OCP Initiator Disconnect
        15. 8.1.3.15 Lock and Unlock Feature
        16. 8.1.3.16 EVE Memory Map
          1. 8.1.3.16.1 VCOP and Local EDMA: IBUF Memory Map Aliasing
          2. 8.1.3.16.2 ARP32 Write Model – Avoiding Race Conditions
        17. 8.1.3.17 Debug Support
          1. 8.1.3.17.1 ARP32 Debug Support
          2. 8.1.3.17.2 SCTM
            1. 8.1.3.17.2.1 SCTM Configuration
            2. 8.1.3.17.2.2 SCTM Resources Reserved for BIOS
            3. 8.1.3.17.2.3 SCTM Event Mapping
            4. 8.1.3.17.2.4 SCTM Halt and Idle Modes
          3. 8.1.3.17.3 SMSET
            1. 8.1.3.17.3.1 SMSET Configuration
            2. 8.1.3.17.3.2 SMSET Event Mapping
        18. 8.1.3.18 EVE L2_FNOC Interconnect
          1. 8.1.3.18.1 EVE L2_FNOC Flag Mux and Error Log Registers
      4. 8.1.4 EVE Programming Model
        1. 8.1.4.1 Boot
        2. 8.1.4.2 Task Change and Program Cache Prefetch
          1. 8.1.4.2.1 Simple or Unoptimized Branch to New Task
          2. 8.1.4.2.2 Prefetch, Wait, then Branch to New Task
          3. 8.1.4.2.3 Hidden Prefetch
        3. 8.1.4.3 Interrupts
        4. 8.1.4.4 Safety Considerations
          1. 8.1.4.4.1 Memory Error Detection
          2. 8.1.4.4.2 MMU
          3. 8.1.4.4.3 Firewall
          4. 8.1.4.4.4 Interconnect
          5. 8.1.4.4.5 Application Stability/Sequencing
          6. 8.1.4.4.6 Interrupt Servicing
      5. 8.1.5 EVE Subsystem Register Manual
        1. 8.1.5.1 EVE Instance Summary
        2. 8.1.5.2 EVE Register Summary and Description
          1. 8.1.5.2.1 EVE Register Summary
          2. 8.1.5.2.2 EVE Register Description
        3. 8.1.5.3 EVE L2_FNOC Register Summary and Description
          1. 8.1.5.3.1 EVE L2_FNOC Register Summary
          2. 8.1.5.3.2 EVE L2_FNOC Register Description
      6. 8.1.6 Subsystem Counter Timer Module
        1. 8.1.6.1 Introduction
          1. 8.1.6.1.1 Overview
          2. 8.1.6.1.2 Top-Level Requirements
          3. 8.1.6.1.3 Configuration
          4. 8.1.6.1.4 Block Diagram
        2. 8.1.6.2 Functional Description
          1. 8.1.6.2.1 Configuration Interface
          2. 8.1.6.2.2 Counter Function
            1. 8.1.6.2.2.1 Input Events
            2. 8.1.6.2.2.2 Counters
            3. 8.1.6.2.2.3 Counting Mode
            4. 8.1.6.2.2.4 Counter Overflow
            5. 8.1.6.2.2.5 Counters and Processor State
            6. 8.1.6.2.2.6 Chaining Counters
              1. 8.1.6.2.2.6.1 Reading Chained Counters
            7. 8.1.6.2.2.7 Enabling and Disabling Counters
            8. 8.1.6.2.2.8 Resetting Counters
          3. 8.1.6.2.3 Timer Function
            1. 8.1.6.2.3.1 Periodic Intervals
            2. 8.1.6.2.3.2 Event Generation
            3. 8.1.6.2.3.3 Watchdog Timer Function
          4. 8.1.6.2.4 System Trace Integration
            1. 8.1.6.2.4.1 Overview
            2. 8.1.6.2.4.2 STM Configuration
              1. 8.1.6.2.4.2.1 Periodic Counter State Export
              2. 8.1.6.2.4.2.2 Application Control of Counter State Export
              3. 8.1.6.2.4.2.3 Application Control of the Counter Configuration Export
        3. 8.1.6.3 Use Case Examples
          1. 8.1.6.3.1 Counter Enable
            1. 8.1.6.3.1.1 Enabling a Single Counter
            2. 8.1.6.3.1.2 Reading a Single Counter
            3. 8.1.6.3.1.3 Enabling a Group of Counters Simultaneously
            4. 8.1.6.3.1.4 Reading a Group of Counters Simultaneously
            5. 8.1.6.3.1.5 Configuring a Chained Counter
          2. 8.1.6.3.2 Timer Enable
          3. 8.1.6.3.3 Periodic STM Export Enable
          4. 8.1.6.3.4 Disabling the SCTM
        4. 8.1.6.4 SCTM Register Manual
          1. 8.1.6.4.1 SCTM Instance Summary
          2. 8.1.6.4.2 SCTM Registers
            1. 8.1.6.4.2.1 SCTM Register Summary
            2. 8.1.6.4.2.2 SCTM Register Description
      7. 8.1.7 Software Message and System Event Trace
        1. 8.1.7.1 Introduction
          1. 8.1.7.1.1 Overview
          2. 8.1.7.1.2 Configuration
          3. 8.1.7.1.3 Block Diagram
        2. 8.1.7.2 Functional Description
          1. 8.1.7.2.1 Connectivity
          2. 8.1.7.2.2 SMSET Event Mapping
          3. 8.1.7.2.3 Software Messages
          4. 8.1.7.2.4 SMSET Master Port
            1. 8.1.7.2.4.1 OCP Disconnect
          5. 8.1.7.2.5 SMSET Debug Features
          6. 8.1.7.2.6 Component Ownership
            1. 8.1.7.2.6.1 Ownership State
              1. 8.1.7.2.6.1.1 Available State
              2. 8.1.7.2.6.1.2 Claimed State
              3. 8.1.7.2.6.1.3 Enabled State
            2. 8.1.7.2.6.2 Ownership Commands
            3. 8.1.7.2.6.3 Claim Reset
        3. 8.1.7.3 Use Case Examples
          1. 8.1.7.3.1 Procedure to Enable System Event Capture
          2. 8.1.7.3.2 Procedure to Start and Stop System Event Capture from External Trigger Detection
          3. 8.1.7.3.3 Procedure to Disable System Event Capture
        4. 8.1.7.4 SMSET Register Manual
          1. 8.1.7.4.1 SMSET Instance Summary
          2. 8.1.7.4.2 SMSET Register Summary
          3. 8.1.7.4.3 SMSET Register Description
    2. 8.2 ARP32 CPU and Instruction Set
      1. 8.2.1 Overview
      2. 8.2.2 Features
      3. 8.2.3 Block Diagram
      4. 8.2.4 Architecture
        1. 8.2.4.1  Interface Description
          1. 8.2.4.1.1 Data Memory Interface
          2. 8.2.4.1.2 Instruction Memory Interface
        2. 8.2.4.2  Pipeline
          1. 8.2.4.2.1 Overview
          2. 8.2.4.2.2 Pipeline Operation
            1. 8.2.4.2.2.1 ARP32 CPU Pipeline Operation
            2. 8.2.4.2.2.2 1129
          3. 8.2.4.2.3 Pipeline Interlocks
        3. 8.2.4.3  Data Format
        4. 8.2.4.4  Endian Support
        5. 8.2.4.5  Architectural Register File
        6. 8.2.4.6  CPU Control Registers
          1. 8.2.4.6.1  Control Status Register (CSR)
          2. 8.2.4.6.2  Interrupt Enable Register (IER)
          3. 8.2.4.6.3  Interrupt Flag Register (IFR)
          4. 8.2.4.6.4  Interrupt Set Register (ISR)
          5. 8.2.4.6.5  Interrupt Clear Register (ICR)
          6. 8.2.4.6.6  Nonmaskable Interrupt (NMI) Return Pointer Register (NRP)
          7. 8.2.4.6.7  Interrupt Return Pointer Register (IRP)
          8. 8.2.4.6.8  Stack Pointer Register (SP)
          9. 8.2.4.6.9  Global Data Pointer Register (GDP)
          10. 8.2.4.6.10 Link Register (LR)
          11. 8.2.4.6.11 Loop 0 Start Address Register (LSA0)
          12. 8.2.4.6.12 Loop 0 End Address Register (LEA0)
          13. 8.2.4.6.13 Loop 0 Iteration Count Register (LCNT0)
          14. 8.2.4.6.14 Loop 1 Start Address Register (LSA1)
          15. 8.2.4.6.15 Loop 1 End Address Register (LEA1)
          16. 8.2.4.6.16 Loop 1 Iteration Count Register (LCNT1)
          17. 8.2.4.6.17 Loop 0 Iteration Count Reload Value Register (LCNT0RLD)
          18. 8.2.4.6.18 Shadow Control Status Register (SCSR)
          19. 8.2.4.6.19 NMI Shadow Control Status Register (NMISCSR)
          20. 8.2.4.6.20 CPU Identification Register (CPUID)
          21. 8.2.4.6.21 Decode Program Counter Register (DPC)
          22. 8.2.4.6.22 Time Stamp Counter Registers (TSCL and TSCH)
            1. 8.2.4.6.22.1 Initialization
            2. 8.2.4.6.22.2 Enabling Counting
            3. 8.2.4.6.22.3 Disabling Counting
            4. 8.2.4.6.22.4 Reading the Counter
        7. 8.2.4.7  CPU Shadow Registers
        8. 8.2.4.8  Functional Units
        9. 8.2.4.9  Instruction Fetch
        10. 8.2.4.10 Alignment of 32-bit Instructions
        11. 8.2.4.11 Instruction Execution in Branch Delay Slot
        12. 8.2.4.12 Address Space
        13. 8.2.4.13 Program Counter Convention
        14. 8.2.4.14 Stack Pointer Convention
        15. 8.2.4.15 Global Data Pointer Convention
        16. 8.2.4.16 Conditional Execution
        17. 8.2.4.17 Hardware Loop Acceleration
          1. 8.2.4.17.1  Overview
          2. 8.2.4.17.2  Loop Registers
          3. 8.2.4.17.3  Loop Setup Instructions
          4. 8.2.4.17.4  Loop Operation
          5. 8.2.4.17.5  Call and Branch within Loop Context
          6. 8.2.4.17.6  Dynamic Changes to Loop Iteration Count
          7. 8.2.4.17.7  Interrupt Processing During HLA
          8. 8.2.4.17.8  HLA Usage in Interrupt Context
          9. 8.2.4.17.9  HLA Usage Restrictions
          10. 8.2.4.17.10 HLA Mapping Examples
            1. 8.2.4.17.10.1 Loops With Single Level of Nesting
              1. 8.2.4.17.10.1.1 C memset-like Loop, Single Level, Minimum Instructions
              2. 8.2.4.17.10.1.2 1184
              3. 8.2.4.17.10.1.3 C memcpy-like Loop, Single Level, Minimum Instructions
              4. 8.2.4.17.10.1.4 1186
            2. 8.2.4.17.10.2 Loops With Two Levels of Nesting
              1. 8.2.4.17.10.2.1 Two-level Nesting, Both Loops Ending at Same Instruction
              2. 8.2.4.17.10.2.2 1189
              3. 8.2.4.17.10.2.3 Two-level Nesting, Different Ending Instructions for Two Levels
              4. 8.2.4.17.10.2.4 1191
        18. 8.2.4.18 Interrupts
          1. 8.2.4.18.1  Overview
          2. 8.2.4.18.2  Interrupt Processing
          3. 8.2.4.18.3  Interrupt Acknowledgment
          4. 8.2.4.18.4  Interrupt Priorities
          5. 8.2.4.18.5  Interrupt Service Table (IST)
          6. 8.2.4.18.6  Interrupt Flags
            1. 8.2.4.18.6.1 Setting Interrupt Flag
            2. 8.2.4.18.6.2 Setting Interrupt Flag
            3. 8.2.4.18.6.3 1201
          7. 8.2.4.18.7  Interrupt Behavior
            1. 8.2.4.18.7.1 Reset Interrupt
            2. 8.2.4.18.7.2 Non-maskable Interrupt (NMI)
            3. 8.2.4.18.7.3 SWI Interrupt
            4. 8.2.4.18.7.4 Maskable Interrupts
            5. 8.2.4.18.7.5 UNDEF Interrupt
          8. 8.2.4.18.8  Interrupt Context Save and Restore
          9. 8.2.4.18.9  Nested Interrupts
            1. 8.2.4.18.9.1 Non-nested Interrupt Model
            2. 8.2.4.18.9.2 Nested Interrupt Model
          10. 8.2.4.18.10 Non-nested Interrupt Latency
            1. 8.2.4.18.10.1 Best Case Interrupt Latency
            2. 8.2.4.18.10.2 Worst Case Interrupt Latency
      5.      8.2.A Instruction Set
        1.       8.2.A.1 Instruction Operation and Execution Notations
        2.       8.2.A.2 Instruction Syntax and Opcode Notations
        3.       8.2.A.3 Instruction Scheduling Restrictions
          1.        8.2.A.3.1 Restrictions Applicable to a Branch Delay Slot
          2.        8.2.A.3.2 Restrictions on Loops Using Hardware Loop Assist (HLA)
          3.        8.2.A.3.3 Restrictions on Other Types of Control Flow Instructions
          4.        8.2.A.3.4 Restrictions for Write Data Bypass to Control Register Reads
          5.        8.2.A.3.5 Restrictions for Write Data Bypass to Shadow Register Reads
          6.        8.2.A.3.6 Restrictions for Link Register Update
        4.       8.2.A.4 Instruction Set Encoding
        5.       8.2.A.5 Instruction Descriptions
          1.        ABS
          2.        ADD
          3.        ADD
          4.        ADD
          5.        ADD
          6.        ADD
          7.        AND
          8.        AND
          9.        B(cc)
          10.        B(cc)
          11.        B(cc)
          12.        BIRP
          13.        BKPT
          14.        BNRP
          15.        CALL
          16.        CALL
          17.        CLR
          18.        CLR
          19.        CMP
          20.        CMP
          21.        CMP
          22.        CMPU
          23.        CMPU
          24.        CMPU
          25.        DIV
          26.        DIVU
          27.        EXT
          28.        EXT
          29.        EXTU
          30.        EXTU
          31.        IDLE
          32.        LDB(U)
          33.        LDB(U)
          34.        LDB(U)
          35.        LDB(U)
          36.        LDB(U)
          37.        LDB(U)
          38.        LDB(U)
          39.        LDB(U)
          40.        LDH(U)
          41.        LDH(U)
          42.        LDH(U)
          43.        LDH(U)
          44.        LDH(U)
          45.        LDH(U)
          46.        LDH(U)
          47.        LDH(U)
          48.        LDW
          49.        LDW
          50.        LDW
          51.        LDW
          52.        LDW
          53.        LDW
          54.        LDW
          55.        LDW
          56.        LDRF
          57.        LMBD
          58.        MAX
          59.        MAXU
          60.        MIN
          61.        MINU
          62.        MOD
          63.        MODU
          64.        MPY
          65.        MPYU
          66.        MV
          67.        MVC
          68.        MVC
          69.        MVC
          70.        MVCH
          71.        MVK
          72.        MVKH
          73.        MVKLS
          74.        MVKS
          75.        MVS
          76.        MVS
          77.        NEG
          78.        NOP
          79.        NOT
          80.        OR
          81.        OR
          82.        RET
          83.        REV
          84.        ROT
          85.        ROTC
          86.        SADD
          87.        SATN
          88.        SET
          89.        SET
          90.        SHL
          91.        SHL
          92.        SHRA
          93.        SHRA
          94.        SHRU
          95.        SHRU
          96.        SLA
          97.        SSUB
          98.        STB
          99.        STB
          100.        STB
          101.        STB
          102.        STB
          103.        STB
          104.        STB
          105.        STB
          106.        STH
          107.        STH
          108.        STH
          109.        STH
          110.        STH
          111.        STH
          112.        STH
          113.        STH
          114.        STW
          115.        STW
          116.        STW
          117.        STW
          118.        STW
          119.        STW
          120.        STW
          121.        STW
          122.        STHI
          123.        STRF
          124.        SUB
          125.        SUB
          126.        SUB
          127.        SUB
          128.        SUB
          129.        SWI
          130.        XOR
          131.        XOR
      6.      8.2.B Clock, Reset, and Dynamic Power Management
        1.       8.2.B.1 Introduction
        2.       8.2.B.2 CPU Reset Modes
        3.       8.2.B.3 Dynamic Power Management
      7.      8.2.C Notes on Programming Model
        1.       8.2.C.1 Booting
        2.       8.2.C.2 Enabling and Disabling Interrupts
          1.        8.2.C.2.1 Globally Enabling or Disabling Maskable Interrupts
          2.        8.2.C.2.2 Enabling or Disabling Individual Interrupts
        3.       8.2.C.3 Stack Usage in Interrupt Service Routine
        4.       8.2.C.4 General Restrictions
    3. 8.3 VCOP CPU and Instruction Set
      1. 8.3.1 Module Overview
      2. 8.3.2 Features
      3. 8.3.3 Block Diagram
      4. 8.3.4 System Interfaces
        1. 8.3.4.1 Interrupts
        2. 8.3.4.2 Configuration Bus Slave Port
        3. 8.3.4.3 Performance Counter Interface
        4. 8.3.4.4 Data Memory Map
      5. 8.3.5 Functional Description
        1. 8.3.5.1 Scalar-Vector Architecture
          1. 8.3.5.1.1 Scalar Core
          2. 8.3.5.1.2 Scalar-Vector Interaction
        2. 8.3.5.2 Vector Core Overview
          1. 8.3.5.2.1 Nested for Loop Model
            1. 8.3.5.2.1.1 Nested Loop Model Skeleton
            2. 8.3.5.2.1.2 1385
          2. 8.3.5.2.2 Instruction Organization
        3. 8.3.5.3 Vector Control
          1. 8.3.5.3.1 Repeat End Count
          2. 8.3.5.3.2 Parameter Pointer
          3. 8.3.5.3.3 Switch Buffers
        4. 8.3.5.4 Vector-Scalar Synchronization
          1. 8.3.5.4.1 Wait for Vector Core Done
          2. 8.3.5.4.2 Wait for Vector Core Ready
        5. 8.3.5.5 Vector Computation
          1. 8.3.5.5.1  Vector Loop
            1. 8.3.5.5.1.1 Retention of State Between VLOOPs
          2. 8.3.5.5.2  Vector Register Initialization
          3. 8.3.5.5.3  Address Generator (agen)
          4. 8.3.5.5.4  Vector Load
          5. 8.3.5.5.5  Vector Arithmetic/Logic Operations
          6. 8.3.5.5.6  Vector Store
          7. 8.3.5.5.7  Table Lookup Operation
          8. 8.3.5.5.8  Histogram Operation
          9. 8.3.5.5.9  Circular Buffer Addressing Support
          10. 8.3.5.5.10 Load/Store Address Alignment Constraints
        6. 8.3.5.6 Load/Store Buffer and Scheduling
          1. 8.3.5.6.1 3-Tap Horizontal Filtering, Byte Type
          2. 8.3.5.6.2 1408
          3. 8.3.5.6.3 Horizontal Filtering, Short Type
          4. 8.3.5.6.4 1410
        7. 8.3.5.7 VCOP Per-Loop Overhead
        8. 8.3.5.8 VCOP Error Handling
        9. 8.3.5.9 Vector Operation Details
          1. 8.3.5.9.1  VABS
          2. 8.3.5.9.2  VABSDIF
          3. 8.3.5.9.3  VADD
          4. 8.3.5.9.4  VADDH
          5. 8.3.5.9.5  VADDSUB
          6. 8.3.5.9.6  VADD3
          7. 8.3.5.9.7  VADIF3
          8. 8.3.5.9.8  VAND
          9. 8.3.5.9.9  VANDN
          10. 8.3.5.9.10 VAND3
          11. 8.3.5.9.11 VBINLOG
          12. 8.3.5.9.12 VBITC
          13. 8.3.5.9.13 VBITDI
          14. 8.3.5.9.14 VBITI
          15. 8.3.5.9.15 VBITPK
          16. 8.3.5.9.16 VBITR
          17. 8.3.5.9.17 VBITTR
          18. 8.3.5.9.18 VBITUNPK
          19. 8.3.5.9.19 VCMOV
          20. 8.3.5.9.20 VCMPEQ
          21. 8.3.5.9.21 VCMPGE
          22. 8.3.5.9.22 VCMPGT
          23. 8.3.5.9.23 VDINTRLV
          24. 8.3.5.9.24 VDINTRLV2
          25. 8.3.5.9.25 VEXITNZ
          26. 8.3.5.9.26 VINTRLV
          27. 8.3.5.9.27 VINTRLV2
          28. 8.3.5.9.28 VINTRLV4
          29. 8.3.5.9.29 VLMBD
          30. 8.3.5.9.30 VMADD
          31. 8.3.5.9.31 VMAX
          32. 8.3.5.9.32 VMAXSETF
          33. 8.3.5.9.33 VMIN
          34. 8.3.5.9.34 VMINSETF
          35. 8.3.5.9.35 VMPY
          36. 8.3.5.9.36 VMSUB
          37. 8.3.5.9.37 VNOP
          38. 8.3.5.9.38 VNOT
          39. 8.3.5.9.39 VOR
          40. 8.3.5.9.40 VOR3
          41. 8.3.5.9.41 VRND
          42. 8.3.5.9.42 VSAD
          43. 8.3.5.9.43 VSEL
          44. 8.3.5.9.44 VSHF
          45. 8.3.5.9.45 VSHFOR
          46. 8.3.5.9.46 VSHF16
          47. 8.3.5.9.47 VSIGN
          48. 8.3.5.9.48 VSORT2
          49. 8.3.5.9.49 VSUB
          50. 8.3.5.9.50 VSWAP
          51. 8.3.5.9.51 VXOR
      6. 8.3.6 Debug Support
      7. 8.3.7 VCOP Register Manual
        1. 8.3.7.1 VCOP Instance Summary
        2. 8.3.7.2 VCOP Registers
          1. 8.3.7.2.1 VCOP Registers Mapping Summary
          2. 8.3.7.2.2 VCOP Register Description
  11. 9 Imaging Subsystem
    1. 9.1 ISS Overview
      1. 9.1.1 ISS Integration
        1. 9.1.1.1 ISS PRCM Interface Integration
          1. 9.1.1.1.1 ISS Clock Domains
      2. 9.1.2 ISS Functional Description
        1. 9.1.2.1 ISS Interrupts
          1. 9.1.2.1.1 ISS Interrupt Merger
          2. 9.1.2.1.2 ISS Submodule Interrupts
            1. 9.1.2.1.2.1 ISS ISP Interrupts
            2. 9.1.2.1.2.2 ISS CAL_B Interrupts
            3. 9.1.2.1.2.3 ISS SIMCOP Interrupts
        2. 9.1.2.2 ISS Interconnect
        3. 9.1.2.3 ISS Video Mux
        4. 9.1.2.4 ISS Clocks
        5. 9.1.2.5 ISS Reset
        6. 9.1.2.6 ISS Power Management
          1. 9.1.2.6.1 ISS Power-Management Infrastructure Overview
          2. 9.1.2.6.2 ISS STANDBY Mechanism
          3. 9.1.2.6.3 ISS IDLE Mechanism
        7. 9.1.2.7 ISS CAL Usage Considerations
          1. 9.1.2.7.1 CAL Usage as Memory to Memory Pixel DMA
          2. 9.1.2.7.2 CAL Usage with GLBCE
      3. 9.1.3 ISS Register Manual
        1. 9.1.3.1 ISS Instance Summary
        2. 9.1.3.2 ISS Registers
          1. 9.1.3.2.1 ISS TOP Register Summary
          2. 9.1.3.2.2 ISS TOP Register Description
    2. 9.2 ISS Camera Adapter Layer (CAL)
      1. 9.2.1 ISS CAL Features
      2. 9.2.2 ISS CAL Integration
        1. 9.2.2.1 CAL Main Integration Attributes
        2. 9.2.2.2 CAL Integration - Video Port
        3. 9.2.2.3 CAL Integration - BYS Ports
      3. 9.2.3 ISS CAL Functional Description
        1. 9.2.3.1  CAL Block Diagram
        2. 9.2.3.2  CAL Hardware and Software Reset
        3. 9.2.3.3  CAL Clock Configuration
        4. 9.2.3.4  CAL Power Management
        5. 9.2.3.5  CAL Interrupt Events
        6. 9.2.3.6  CAL Data Stream
        7. 9.2.3.7  CAL Pixel Extraction
        8. 9.2.3.8  CAL DPCM Decoding and Encoding
          1. 9.2.3.8.1 CAL Partial DPCM Decompression
        9. 9.2.3.9  CAL Pixel Packing
        10. 9.2.3.10 CAL Write DMA
          1. 9.2.3.10.1 CAL Write DMA Overview
          2. 9.2.3.10.2 CAL Write DMA Data Cropping
          3. 9.2.3.10.3 CAL Write DMA Buffer Management
          4. 9.2.3.10.4 CAL Write DMA OCP Address Generation
            1. 9.2.3.10.4.1 Write DMA Buffer Base Address
            2. 9.2.3.10.4.2 Write DMA Line Start Address
            3. 9.2.3.10.4.3 Write DMA Data Address
          5. 9.2.3.10.5 CAL Write DMA OCP Transaction Generation
          6. 9.2.3.10.6 CAL Write DMA Real Time Traffic
        11. 9.2.3.11 CAL Read DMA
          1. 9.2.3.11.1 CAL Read DMA Overview
          2. 9.2.3.11.2 CAL Read DMA Data Provided to Processing Pipeline
          3. 9.2.3.11.3 CAL Read DMA Skipping Modes
          4. 9.2.3.11.4 CAL Read DMA YUV420 Support
          5. 9.2.3.11.5 CAL Read DMA OCP Request Generation
        12. 9.2.3.12 CAL Video Port
          1. 9.2.3.12.1 CAL Video Port Overview
          2. 9.2.3.12.2 CAL Video Port Pixel Clock Generation
          3. 9.2.3.12.3 CAL Video Port Video Timing Generator
        13. 9.2.3.13 CAL BYS Ports
          1. 9.2.3.13.1 CAL BYS Ports Overview
          2. 9.2.3.13.2 CAL BYS Output Port
          3. 9.2.3.13.3 BYS Input Port
        14. 9.2.3.14 CAL Registers Shadowing
      4. 9.2.4 ISS CAL Register Manual
        1. 9.2.4.1 CAL Instance Summary
        2. 9.2.4.2 CAL Registers
          1. 9.2.4.2.1 CAL Register Summary
          2. 9.2.4.2.2 CAL Register Description
    3. 9.3 ISS Image Signal Processor (ISP)
      1. 9.3.1 ISS ISP Overview
        1. 9.3.1.1 ISS ISP Features
        2. 9.3.1.2 ISS ISP Block Diagram
      2. 9.3.2 ISS ISP Integration
        1. 9.3.2.1 ISS ISP PRCM Interface
          1. 9.3.2.1.1 ISS ISP Clocks
          2. 9.3.2.1.2 ISS ISP Reset
        2. 9.3.2.2 ISS ISP Interrupt Tree
        3. 9.3.2.3 ISS ISP IPIPEIF Integration
          1. 9.3.2.3.1 ISS ISP IPIPEIF Interrupts
        4. 9.3.2.4 ISS ISP IPIPE Integration
          1. 9.3.2.4.1 ISS ISP IPIPE Interrupts
        5. 9.3.2.5 ISS ISP RSZ Integration
          1. 9.3.2.5.1 ISS ISP RSZ PRCM Interface
            1. 9.3.2.5.1.1 ISS ISP RSZ Reset
          2. 9.3.2.5.2 ISS ISP RSZ Interrupts
        6. 9.3.2.6 ISS ISP H3A Integration
          1. 9.3.2.6.1 ISS ISP H3A Interrupts
        7. 9.3.2.7 ISS ISP ISIF Integration
          1. 9.3.2.7.1 ISS ISP ISIF Interrupts
        8. 9.3.2.8 ISS ISP BL Integration
      3. 9.3.3 ISS ISP Functional Description
        1. 9.3.3.1  ISS ISP VP Functional Description
          1. 9.3.3.1.1 ISS ISP VP Overview
          2. 9.3.3.1.2 ISS ISP VP Data Formats
          3. 9.3.3.1.3 ISS ISP VP Top-Level Communication With CAL_B
          4. 9.3.3.1.4 ISS ISP VP Pixel Clock Inversion
        2. 9.3.3.2  ISS ISP GLBCE Functional Description
          1. 9.3.3.2.1 ISS ISP GLBCE Overview
          2. 9.3.3.2.2 ISS ISP GLBCE Interface
          3. 9.3.3.2.3 ISS ISP GLBCE Core
            1. 9.3.3.2.3.1 ISS ISP GLBCE Core Key Parameters
            2. 9.3.3.2.3.2 ISS ISP GLBCE Iridix Strength Calculation
            3. 9.3.3.2.3.3 ISS ISP GLBCE Iridix Configuration Registers
              1. 9.3.3.2.3.3.1  ISS ISP GLBCE Iridix Frame Width
              2. 9.3.3.2.3.3.2  ISS ISP GLBCE Iridix Frame Height
              3. 9.3.3.2.3.3.3  ISS ISP GLBCE Iridix Control
              4. 9.3.3.2.3.3.4  ISS ISP GLBCE Iridix Control
              5. 9.3.3.2.3.3.5  ISS ISP GLBCE Iridix Strength
              6. 9.3.3.2.3.3.6  ISS ISP GLBCE Iridix Variance
              7. 9.3.3.2.3.3.7  ISS ISP GLBCE Iridix Dither
              8. 9.3.3.2.3.3.8  ISS ISP GLBCE Iridix Amplification Limit
              9. 9.3.3.2.3.3.9  ISS ISP GLBCE Iridix Slope Min and Max
              10. 9.3.3.2.3.3.10 ISS ISP GLBCE Iridix Black Level
              11. 9.3.3.2.3.3.11 ISS ISP GLBCE Iridix White Level
              12. 9.3.3.2.3.3.12 ISS ISP GLBCE Iridix Asymmetry Function Look-up-table
              13. 9.3.3.2.3.3.13 ISS ISP GLBCE Iridix Forward and Reverse Perceptual Functions Look-up-tables
              14. 9.3.3.2.3.3.14 ISS ISP GLBCE Iridix Tile Position and Size
              15. 9.3.3.2.3.3.15 ISS ISP GLBCE Iridix WDR Look-up-table
          4. 9.3.3.2.4 ISS ISP GLBCE Embedded Memory
          5. 9.3.3.2.5 ISS ISP GLBCE Programming Model
            1. 9.3.3.2.5.1 ISS ISP GLBCE Restriction
              1. 9.3.3.2.5.1.1 ISS ISP GLBCE Recovery from Reset
              2. 9.3.3.2.5.1.2 General description of GLBCE processing
              3. 9.3.3.2.5.1.3 Continuous Frame Processing
              4. 9.3.3.2.5.1.4 Single Image Processing
        3. 9.3.3.3  ISS ISP NSF3V Functional Description
          1. 9.3.3.3.1 ISS ISP NSF3V Overview
          2. 9.3.3.3.2 ISS ISP NSF3V Register Shadowing
          3. 9.3.3.3.3 ISS ISP NSF3V Programming Model
            1. 9.3.3.3.3.1 ISS ISP NSF3V Initialization
        4. 9.3.3.4  ISS ISP IPIPEIF Functional Description
          1. 9.3.3.4.1  ISS ISP IPIPEIF Overview
          2. 9.3.3.4.2  ISS ISP IPIPEIF Top-Level Block Diagram
          3. 9.3.3.4.3  ISS ISP IPIPEIF Input Interface
            1. 9.3.3.4.3.1 ISS ISP IPIPEIF Input From VP
            2. 9.3.3.4.3.2 ISS ISP IPIPEIF Input From BL
              1. 9.3.3.4.3.2.1 ISS ISP IPIPEIF Double-Buffer Input Function When Reading From BL
          4. 9.3.3.4.4  ISS ISP IPIPEIF Data Path Selection
            1. 9.3.3.4.4.1 ISS ISP IPIPEIF INPSRC1 = 0 and INPSRC2 = 0
            2. 9.3.3.4.4.2 ISS ISP IPIPEIF INPSRC1 = 0 and INPSRC2 = 1
            3. 9.3.3.4.4.3 ISS ISP IPIPEIF INPSRC1 = 0 and INPSRC2 = 2
            4. 9.3.3.4.4.4 ISS ISP IPIPEIF INPSRC1 = 0 and INPSRC2 = 3
            5. 9.3.3.4.4.5 ISS ISP IPIPEIF INPSRC1 = 1 and INPSRC2 = 0
            6. 9.3.3.4.4.6 ISS ISP IPIPEIF INPSRC1 = 2 and INPSRC2 = 0
            7. 9.3.3.4.4.7 ISS ISP IPIPEIF INPSRC1 = 3 and INPSRC2 = 0
          5. 9.3.3.4.5  ISS ISP IPIPEIF Timing Generation
            1. 9.3.3.4.5.1 ISS ISP IPIPEIF Fractional Clock Divider
          6. 9.3.3.4.6  ISS ISP IPIPEIF Decompression (DPCM) Subblock: Unpack and Decompression Function
          7. 9.3.3.4.7  ISS ISP IPIPEIF Dark-Frame Subtraction Functionality
            1. 9.3.3.4.7.1 ISS ISP IPIPEIF Defect Pixel Correction
            2. 9.3.3.4.7.2 ISS ISP IPIPEIF DFS Subtraction Direction
          8. 9.3.3.4.8  ISS ISP IPIPEIF Wide Dynamic Range WDR Merging Functionality
            1. 9.3.3.4.8.1 ISS ISP IPIPEIF merging general description
          9. 9.3.3.4.9  ISS ISP IPIPEIF (1, 2, 1) Averaging Filter for IPIPE Data Path
          10. 9.3.3.4.10 ISS ISP IPIPEIF Horizontal Pixel Decimator (Downsizer) for IPIPE Data Path
          11. 9.3.3.4.11 ISS ISP IPIPEIF RAW Data Gain for IPIPE Data Path
          12. 9.3.3.4.12 ISS ISP IPIPEIF (1, 2 ,1) Averaging Filter for H3A Data Path
          13. 9.3.3.4.13 ISS ISP IPIPEIF Horizontal Pixel Decimator (Downsizer) for H3A Data Path
          14. 9.3.3.4.14 ISS ISP IPIPEIF YUV4:2:2 8-bit Packed Data Input Coming From ISIF Module
          15. 9.3.3.4.15 ISS ISP IPIPEIF YUV4:2:0 Data Input for Memory-to-Memory Resize Operations
          16. 9.3.3.4.16 ISS ISP IPIPEIF Module Events and Status Checking
        5. 9.3.3.5  ISS ISP IPIPE Functional Description
          1. 9.3.3.5.1  ISS ISP IPIPE Overview
          2. 9.3.3.5.2  ISS ISP IPIPE Top-Level Block Diagram
          3. 9.3.3.5.3  ISS ISP IPIPE Input Interface
          4. 9.3.3.5.4  ISS ISP IPIPE Defect Pixel Correction
            1. 9.3.3.5.4.1 ISS ISP IPIPE LUT Defect Pixel Correction (LUT DPC)
          5. 9.3.3.5.5  ISS ISP IPIPE DPC Interface
          6. 9.3.3.5.6  ISS ISP IPIPE White Balance
          7. 9.3.3.5.7  ISS ISP IPIPE YUV422to444
          8. 9.3.3.5.8  ISS ISP IPIPE RGB2RGB Blending Module
          9. 9.3.3.5.9  ISS ISP IPIPE Gamma Correction Module
          10. 9.3.3.5.10 ISS ISP IPIPE Second RGB2RGB Conversion Matrix
          11. 9.3.3.5.11 ISS ISP IPIPE RGB2YCbCr Conversion Matrix
          12. 9.3.3.5.12 ISS ISP IPIPE 4:2:2 Conversion Module
          13. 9.3.3.5.13 ISS ISP IPIPE 2D Edge-Enhancer
          14. 9.3.3.5.14 ISS ISP IPIPE Histogram
          15. 9.3.3.5.15 ISS ISP IPIPE Boxcar
        6. 9.3.3.6  ISS ISP RSZ Functional Description
          1. 9.3.3.6.1 ISS ISP RSZ Overview
          2. 9.3.3.6.2 ISS ISP RSZ Top-Level Block Diagram
          3. 9.3.3.6.3 ISS ISP RSZ Interfaces
            1. 9.3.3.6.3.1 ISS ISP RSZ VBUSP Interface
            2. 9.3.3.6.3.2 ISS ISP RSZ Video Port Interfaces
            3. 9.3.3.6.3.3 ISS ISP RSZ MTC Interfaces
            4. 9.3.3.6.3.4 ISS ISP RSZ CNF Interface
          4. 9.3.3.6.4 ISS ISP RSZ ICM Handshake Signals
          5. 9.3.3.6.5 ISS ISP RSZ Integration
          6. 9.3.3.6.6 ISS ISP RSZ Functional Description
            1. 9.3.3.6.6.1 ISS ISP RSZ Operating Modes
              1. 9.3.3.6.6.1.1 ISS ISP RSZ Operating Modes and Maximum Input Clock
            2. 9.3.3.6.6.2 ISS ISP RSZ Input Data Cropper
            3. 9.3.3.6.6.3 ISS ISP RSZ Averager
              1. 9.3.3.6.6.3.1 ISS ISP RSZ Use Cases
              2. 9.3.3.6.6.3.2 ISS ISP RSZ Memory Use
              3. 9.3.3.6.6.3.3 ISS ISP RSZ Border Conditions
            4. 9.3.3.6.6.4 ISS ISP RSZ Interpolation
              1. 9.3.3.6.6.4.1 ISS ISP RSZ Liner Interpolation Input Data
                1. 9.3.3.6.6.4.1.1 ISS ISP RSZ Cubic Convolution Mode
                2. 9.3.3.6.6.4.1.2 ISS ISP RSZ Phase Settings
            5. 9.3.3.6.6.5 ISS ISP RSZ Data Saturator
            6. 9.3.3.6.6.6 ISS ISP RSZ Color Converter
            7. 9.3.3.6.6.7 ISS ISP RSZ Output Interface
              1. 9.3.3.6.6.7.1 ISS ISP RSZ Circular Buffer
        7. 9.3.3.7  ISS ISP CNF Functional Description
          1. 9.3.3.7.1 ISS ISP CNF Overview
          2. 9.3.3.7.2 ISS ISP CNF Top Level Block Diagram
          3. 9.3.3.7.3 ISS ISP CNF Noise Filter Algorithm
          4. 9.3.3.7.4 ISS ISP CNF Chroma Downsampling and Upsampling
          5. 9.3.3.7.5 ISS ISP CNF Vertical and Horizontal Blanking
          6. 9.3.3.7.6 ISS ISP CNF configuring ranges/restrictions
        8. 9.3.3.8  ISS ISP H3A Functional Description
          1. 9.3.3.8.1 ISS ISP H3A Overview
          2. 9.3.3.8.2 ISS ISP H3A Top-Level Block Diagram
          3. 9.3.3.8.3 ISS ISP H3A Line Framing Logic
          4. 9.3.3.8.4 ISS ISP H3A Optional Preprocessing
          5. 9.3.3.8.5 ISS ISP H3A Autofocus Engine
            1. 9.3.3.8.5.1 ISS ISP H3A Paxel Extraction
            2. 9.3.3.8.5.2 ISS ISP H3A Horizontal FV Calculator
            3. 9.3.3.8.5.3 ISS ISP H3A HFV Accumulator
            4. 9.3.3.8.5.4 ISS ISP H3A VFV Calculator
            5. 9.3.3.8.5.5 ISS ISP H3A VFV Accumulator
          6. 9.3.3.8.6 ISS ISP H3A AE/AWB Engine
            1. 9.3.3.8.6.1 ISS ISP H3A Subsampler
            2. 9.3.3.8.6.2 ISS ISP H3A Additional Black Row of AE/AWB Windows
            3. 9.3.3.8.6.3 ISS ISP H3A Saturation Check
            4. 9.3.3.8.6.4 ISS ISP H3A AE/AWB Accumulators
          7. 9.3.3.8.7 ISS ISP H3A DMA Interface
          8. 9.3.3.8.8 ISS ISP H3A Events and Status Checking
        9. 9.3.3.9  ISS ISP ISIF Functional Description
          1. 9.3.3.9.1  ISS ISP ISIF Overview
          2. 9.3.3.9.2  ISS ISP ISIF Top-Level Block Diagram
          3. 9.3.3.9.3  ISS ISP ISIF Input Interface
          4. 9.3.3.9.4  ISS ISP ISIF Interface
          5. 9.3.3.9.5  ISS ISP ISIF Sensor Linearization
          6. 9.3.3.9.6  ISS ISP ISIF Input Data Formatter
            1. 9.3.3.9.6.1 1714
            2. 9.3.3.9.6.2 ISS ISP ISIF Formatter Area Settings
            3. 9.3.3.9.6.3 ISS ISP ISIF Formatter Programming
            4. 9.3.3.9.6.4 ISS ISP ISIF Combine the Divided Input Lines
          7. 9.3.3.9.7  ISS ISP ISIF Color Space Converter
          8. 9.3.3.9.8  ISS ISP ISIF Black Clamp
            1. 9.3.3.9.8.1 ISS ISP ISIF Clamp Value for Horizontal Direction
            2. 9.3.3.9.8.2 ISS ISP ISIF Clamp Value for Vertical Direction
          9. 9.3.3.9.9  ISS ISP ISIF Vertical Line Defect Correction (VDFC)
            1. 9.3.3.9.9.1 ISS ISP ISIF Vertical Line Defect Table Update Procedure
          10. 9.3.3.9.10 ISS ISP ISIF Lens Shading Correction Module (2D-LSC)
            1. 9.3.3.9.10.1 ISS ISP ISIF 2D-LSC Active Region Settings
              1. 9.3.3.9.10.1.1 ISS ISP ISIF 2D-LSC Gain and Offset Tables
              2. 9.3.3.9.10.1.2 ISS ISP ISIF 2D-LSC Gain and Offset Table Upsampling
              3. 9.3.3.9.10.1.3 ISS ISP ISIF Application of Gain and Offset to Image Pixels
              4. 9.3.3.9.10.1.4 ISS ISP ISIF Enabling and Disabling the 2D-LSC Module
              5. 9.3.3.9.10.1.5 ISS ISP ISIF 2D-LSC Events and Status Checking
              6. 9.3.3.9.10.1.6 ISS ISP ISIF Supported On-the-Fly 2D-LSC Configurations
              7. 9.3.3.9.10.1.7 ISS ISP ISIF Bandwidth Requirements on BL Read Port
          11. 9.3.3.9.11 ISS ISP ISIF White Balance
          12. 9.3.3.9.12 ISS ISP ISIF Low-Pass Filter
          13. 9.3.3.9.13 ISS ISP ISIF A-Law Compression
          14. 9.3.3.9.14 ISS ISP ISIF Culling
          15. 9.3.3.9.15 ISS ISP ISIF 12-to-8-Bit DPCM Compression Block
          16. 9.3.3.9.16 ISP ISIF Storage Formatter
          17. 9.3.3.9.17 ISS ISP ISIF Circular Buffer
          18. 9.3.3.9.18 ISS ISP ISIF YCbCr Signal Processing
          19. 9.3.3.9.19 ISS ISP ISIF Expected Bandwidth on BL Ports
            1. 9.3.3.9.19.1 ISS ISP ISIF Write Port
            2. 9.3.3.9.19.2 ISS ISP ISIF Read Port
          20. 9.3.3.9.20 ISS ISP ISIF Events and Status Checking
            1. 9.3.3.9.20.1 ISS ISP ISIF VDINT0, VDINT1, and VDINT2 Interrupts
            2. 9.3.3.9.20.2 ISS ISP ISIF 2DLSCINT Interrupt
            3. 9.3.3.9.20.3 ISS ISP ISIF Status Checking
        10. 9.3.3.10 ISS ISP BL Functional Description
          1. 9.3.3.10.1 ISS ISP BL Overview
          2. 9.3.3.10.2 ISS ISP BL Functional Description
          3. 9.3.3.10.3 ISS ISP BL Address Alignment
          4. 9.3.3.10.4 ISS ISP BL Out-of-Order Responses
          5. 9.3.3.10.5 ISS ISP BL Stalling
            1. 9.3.3.10.5.1 ISS ISP BL Stalling Write Requests
            2. 9.3.3.10.5.2 ISS ISP BL Stalling Read Requests
          6. 9.3.3.10.6 ISS ISP BL Dynamic and Static MFlag Generation
          7. 9.3.3.10.7 ISS ISP BL VBUSM2OCP Last Beat Command Delay
          8. 9.3.3.10.8 ISS ISP BL Peak Memory Bandwidth Reduction
        11. 9.3.3.11 ISS ISP Memory Mapping
      4. 9.3.4 ISS ISP Register Manual
        1. 9.3.4.1  ISS ISP Instance Summary
        2. 9.3.4.2  ISS ISP6P5_SYS1 Registers
          1. 9.3.4.2.1 ISS ISP6P5_SYS1 Register Summary
          2. 9.3.4.2.2 ISS ISP6P5_SYS1 Register Description
        3. 9.3.4.3  ISS ISP6P5_SYS2 Registers
          1. 9.3.4.3.1 ISS ISP6P5_SYS2 Register Summary
          2. 9.3.4.3.2 ISS ISP6P5_SYS2 Register Description
        4. 9.3.4.4  ISS ISP6P5_RESIZER Registers
          1. 9.3.4.4.1 ISS ISP6P5_RESIZER Register Summary
          2. 9.3.4.4.2 ISS ISP6P5_RESIZER Register Description
        5. 9.3.4.5  ISS ISP6P5_IPIPE Registers
          1. 9.3.4.5.1 ISS ISP6P5_IPIPE Register Summary
          2. 9.3.4.5.2 ISS ISP6P5_IPIPE Register Description
        6. 9.3.4.6  ISS ISP6P5_ISIF Registers
          1. 9.3.4.6.1 ISS ISP6P5_ISIF Register Summary
          2. 9.3.4.6.2 ISS ISP6P5_ISIF Register Description
        7. 9.3.4.7  ISS ISP6P5_IPIPEIF Registers
          1. 9.3.4.7.1 ISS ISP6P5_IPIPEIF Register Summary
          2. 9.3.4.7.2 ISS ISP6P5_IPIPEIF Register Description
        8. 9.3.4.8  ISS ISP6P5_H3A Registers
          1. 9.3.4.8.1 ISS ISP6P5_H3A Register Summary
          2. 9.3.4.8.2 ISS ISP6P5_H3A Register Description
        9. 9.3.4.9  ISS ISP6P5_SYS3 Registers
          1. 9.3.4.9.1 ISS ISP6P5_SYS3 Register Summary
          2. 9.3.4.9.2 ISS ISP6P5_SYS3 Register Description
        10. 9.3.4.10 ISS ISP6P5 CNF1 and NSF3V Registers
          1. 9.3.4.10.1 ISS ISP6P5 CNF1 and NSF3V Register Summary
          2. 9.3.4.10.2 ISS ISP6P5 CNF1 and NSF3V Register Description
        11. 9.3.4.11 ISS ISP6P5_GLBCE Registers
          1. 9.3.4.11.1 ISS ISP6P5_GLBCE Register Summary
          2. 9.3.4.11.2 ISS ISP6P5_GLBCE Register Description
    4. 9.4 ISS Still Image Coprocessor (SIMCOP)
      1. 9.4.1 ISS SIMCOP Overview
        1. 9.4.1.1 ISS SIMCOP Integration
        2. 9.4.1.2 ISS SIMCOP Functional Description
          1. 9.4.1.2.1 ISS SIMCOP Local Power and Clock Management
            1. 9.4.1.2.1.1 ISS SIMCOP Local Clock Management
            2. 9.4.1.2.1.2 Local Clock Autogating
            3. 9.4.1.2.1.3 ISS SIMCOP Power Management
          2. 9.4.1.2.2 ISS SIMCOP Reset
          3. 9.4.1.2.3 ISS SIMCOP Interrupt Merger
          4. 9.4.1.2.4 ISS SIMCOP Modules Description
        3. 9.4.1.3 ISS SIMCOP Programming Models
          1. 9.4.1.3.1 Global Initialization
            1. 9.4.1.3.1.1 Surrounding Modules Global Initialization
            2. 9.4.1.3.1.2 ISS SIMCOP Module Global Initialization
          2. 9.4.1.3.2 ISS SIMCOP Operational Modes Configuration
            1. 9.4.1.3.2.1 Interrupts
        4. 9.4.1.4 ISS SIMCOP Registers Manual
          1. 9.4.1.4.1 SIMCOP Instance Summary
          2. 9.4.1.4.2 SIMCOP Registers
            1. 9.4.1.4.2.1 SIMCOP Register Summary
            2. 9.4.1.4.2.2 SIMCOP Register Description
      2. 9.4.2 ISS SIMCOP Hardware Sequencer and Buffers Module
        1. 9.4.2.1 ISS SIMCOP Hardware Sequencer and Buffers Overview
        2. 9.4.2.2 ISS SIMCOP Hardware Sequencer and Buffer Integration
        3. 9.4.2.3 ISS SIMCOP Hardware Sequencer and Buffers Functional Description
          1. 9.4.2.3.1 ISS SIMCOP Hardware Sequencer and Buffers Software Reset
          2. 9.4.2.3.2 ISS SIMCOP Hardware Sequencer and Buffers Power Management
          3. 9.4.2.3.3 ISS SIMCOP Hardware Sequencer and Buffer Interrupt Requests
            1. 9.4.2.3.3.1 Static Crossbar
            2. 9.4.2.3.3.2 Image Buffers
          4. 9.4.2.3.4 ISS SIMCOP Hardware Sequencer
            1. 9.4.2.3.4.1 Automatic Operation
            2. 9.4.2.3.4.2 Hardware Sequencer Override
        4. 9.4.2.4 ISS SIMCOP Hardware Sequencer and Buffers Basic Programming Model
          1. 9.4.2.4.1 ISS SIMCOP Hardware Sequencer and Buffers Application Programming Principle
          2. 9.4.2.4.2 External CPU Use for Data Processing
        5. 9.4.2.5 ISS SIMCOP Hardware Sequencer and Buffer Registers Manual
          1. 9.4.2.5.1 Hardware Sequencer Instance Summary
          2. 9.4.2.5.2 Hardware Sequencer Registers
            1. 9.4.2.5.2.1 Hardware Sequencer Register Summary
            2. 9.4.2.5.2.2 Hardware Sequencer Register Description
      3. 9.4.3 ISS SIMCOP DMA Module
        1. 9.4.3.1 ISS SIMCOP DMA Overview
        2. 9.4.3.2 ISS SIMCOP DMA Integration
        3. 9.4.3.3 ISS SIMCOP DMA Functional Description
          1. 9.4.3.3.1 ISS SIMCOP DMA Block Diagram
          2. 9.4.3.3.2 ISS SIMCOP DMA Power Management
          3. 9.4.3.3.3 ISS SIMCOP DMA Interrupt Requests
          4. 9.4.3.3.4 ISS SIMCOP DMA Logical Channels
            1. 9.4.3.3.4.1 Logical Channel States
            2. 9.4.3.3.4.2 Logical Channel Chaining, Trigger, and Hardware Synchronization
            3. 9.4.3.3.4.3 Logical Channel Data Transfer
          5. 9.4.3.3.5 Transaction Generation
            1. 9.4.3.3.5.1 Incrementing Bursts for Regular Transfers
        4. 9.4.3.4 ISS SIMCOP DMA Basic Programming Model
          1. 9.4.3.4.1 Initialization of Surrounding Modules
          2. 9.4.3.4.2 ISS SIMCOP DMA Channel Configuration and Hardware Synchronization
          3. 9.4.3.4.3 Software Synchronization
        5. 9.4.3.5 ISS SIMCOP DMA Register Manual
          1. 9.4.3.5.1 ISS SIMCOP DMA Instance Summary
          2. 9.4.3.5.2 ISS SIMCOP DMA Registers
            1. 9.4.3.5.2.1 ISS SIMCOP DMA Register Summary
            2. 9.4.3.5.2.2 ISS SIMCOP DMA Register Description
      4. 9.4.4 ISS SIMCOP VTNF Module
        1. 9.4.4.1 ISS SIMCOP VTNF Overview
        2. 9.4.4.2 ISS SIMCOP VTNF Environment
          1. 9.4.4.2.1 ISS SIMCOP VTNF Protocols and Data Formats
        3. 9.4.4.3 ISS SIMCOP VTNF Integration
        4. 9.4.4.4 ISS SIMCOP VTNF Functional Description
          1. 9.4.4.4.1 ISS SIMCOP VTNF Block Diagram
          2. 9.4.4.4.2 ISS SIMCOP VTNF Clocks Management
          3. 9.4.4.4.3 ISS SIMCOP VTNF Interrupt Requests
          4. 9.4.4.4.4 ISS SIMCOP VTNF Configuration
            1. 9.4.4.4.4.1 ISS SIMCOP VTNF Initialization
            2. 9.4.4.4.4.2 ISS SIMCOP VTNF Programming Ranges and Restrictions
            3. 9.4.4.4.4.3 ISS SIMCOP VTNF Resets
            4. 9.4.4.4.4.4 ISS SIMCOP VTNF Programming Parameters Tuning
        5. 9.4.4.5 ISS SIMCOP VTNF Register Manual
          1. 9.4.4.5.1 ISS SIMCOP VTNF Instance Summary
          2. 9.4.4.5.2 ISS SIMCOP VTNF registers
            1. 9.4.4.5.2.1 ISS SIMCOP VTNF Register Summary
            2. 9.4.4.5.2.2 ISS SIMCOP VTNF Register Description
      5. 9.4.5 ISS SIMCOP LDC Module
        1. 9.4.5.1 ISS SIMCOP LDC Overview
        2. 9.4.5.2 ISS SIMCOP LDC Integration
        3. 9.4.5.3 ISS SIMCOP LDC Functional Description
          1. 9.4.5.3.1  ISS SIMCOP LDC Block Diagram
          2. 9.4.5.3.2  ISS SIMCOP LDC Interrupt Requests
          3. 9.4.5.3.3  ISS SIMCOP LDC Input/Output Format Data
            1. 9.4.5.3.3.1 ISS SIMCOP LDC YCbCr Format
            2. 9.4.5.3.3.2 ISS SIMCOP LDC Bayer Format
          4. 9.4.5.3.4  ISS SIMCOP Lens Distortion Back-Mapping
          5. 9.4.5.3.5  ISS SIMCOP LCD Bayer Chromatic Aberration Correction Implementation
          6. 9.4.5.3.6  ISS SIMCOP LDC Affine Transform
          7. 9.4.5.3.7  ISS SIMCOP LDC Perspective Transformation
          8. 9.4.5.3.8  ISS SIMCOP LDC Pixel Interpolation
          9. 9.4.5.3.9  ISS SIMCOP LDC Buffer Management
          10. 9.4.5.3.10 ISS SIMCOP LDC Input Circular Buffer
          11. 9.4.5.3.11 ISS SIMCOP LDC and Hardware Sequencer
            1. 9.4.5.3.11.1 ISS SIMCOP LDC and Hardware Sequencer and Buffers Overview
            2. 9.4.5.3.11.2 ISS SIMCOP LDC and Hardware Sequencer and Buffer Integration
            3. 9.4.5.3.11.3 ISS SIMCOP LDC and Hardware Sequencer and Buffers Functional Description
              1. 9.4.5.3.11.3.1 ISS SIMCOP Hardware Sequencer Buffer Description
                1. 9.4.5.3.11.3.1.1 ISS SIMCOP LDC Static Crossbar
                2. 9.4.5.3.11.3.1.2 ISS SIMCOP LDC Private Input Memory
              2. 9.4.5.3.11.3.2 ISS SIMCOP Hardware Sequencer
                1. 9.4.5.3.11.3.2.1 Hardware Sequencer Override
        4. 9.4.5.4 ISS SIMCOP LDC Basic Programming Model
          1. 9.4.5.4.1 ISS SIMCOP LDC Initialization of Surrounding Modules
          2. 9.4.5.4.2 ISS SIMCOP LDC Geometric Distortion Mode
          3. 9.4.5.4.3 ISS SIMCOP LDC Bayer Chromatic Aberration Mode
          4. 9.4.5.4.4 ISS SIMCOP LDC Programming Affine Transformation
          5. 9.4.5.4.5 ISS SIMCOP LDC Programming Perspective Transformation
        5. 9.4.5.5 ISS SIMCOP LDC Register Manual
          1. 9.4.5.5.1 ISS SIMCOP LDC Instance Summary
          2. 9.4.5.5.2 ISS SIMCOP LDC Registers
            1. 9.4.5.5.2.1 ISS SIMCOP LDC Register Summary
            2. 9.4.5.5.2.2 ISS SIMCOP LDC Register Description
  12. 10Camera Interface Subsystem
    1. 10.1 CAMSS Overview
      1. 10.1.1 CAMSS Block Diagram
      2. 10.1.2 1914
      3. 10.1.3 CAMSS Features
    2. 10.2 CAMSS Environment
      1. 10.2.1 CAMSS Interfaces Signal Descriptions
    3. 10.3 CAMSS Integration
      1. 10.3.1 CAMSS Main Integration Attributes
      2. 10.3.2 CAL Integration - Video Port
      3. 10.3.3 CAL Integration - PPI Interface
    4. 10.4 CAMSS Functional Description
      1. 10.4.1 CAMSS Hardware and Software Reset
      2. 10.4.2 CAMSS Clock Configuration
      3. 10.4.3 CAMSS Power Management
      4. 10.4.4 CAMSS Interrupt Events
      5. 10.4.5 CSI2 PHY Functional Description
        1. 10.4.5.1 CSI2 PHY Overview
        2. 10.4.5.2 CSI2 PHY Configuration
        3. 10.4.5.3 CSI2 PHY Link Initialization Sequence
        4. 10.4.5.4 CSI2 PHY Error Signals
      6. 10.4.6 CAL Functional Description
        1. 10.4.6.1  CAL Block Diagram
        2. 10.4.6.2  CSI2 Low Level Protocol
          1. 10.4.6.2.1 CSI2 Physical Layer
          2. 10.4.6.2.2 CSI2 Multi-lane Layer and Lane Merger
          3. 10.4.6.2.3 CSI2 Protocol Layer
            1. 10.4.6.2.3.1  CSI2 Short Packet
            2. 10.4.6.2.3.2  CSI2 Long Packet
            3. 10.4.6.2.3.3  CSI2 ECC and Checksum Generation
              1. 10.4.6.2.3.3.1 CSI2 ECC
              2. 10.4.6.2.3.3.2 CSI2 Checksum
            4. 10.4.6.2.3.4  CSI2 Alignment Constraints
            5. 10.4.6.2.3.5  CSI2 Data Identifier
            6. 10.4.6.2.3.6  CSI2 Virtual Channel ID
            7. 10.4.6.2.3.7  CSI2 Synchronization Codes
            8. 10.4.6.2.3.8  CSI2 Generic Short Packet Codes
            9. 10.4.6.2.3.9  CSI2 Frame Structure and Data
            10. 10.4.6.2.3.10 CSI2 Virtual Channel and Context
          4. 10.4.6.2.4 CSI2 TAG Generation FSM
        3. 10.4.6.3  CAL Data Stream Merger
        4. 10.4.6.4  CAL Pixel Extraction
        5. 10.4.6.5  CAL DPCM Decoding and Encoding
        6. 10.4.6.6  CAL Stream Interleaving
        7. 10.4.6.7  CAL Pixel Packing
        8. 10.4.6.8  CAL Write DMA
          1. 10.4.6.8.1 CAL Write DMA Overview
          2. 10.4.6.8.2 CAL Write DMA Data Cropping
          3. 10.4.6.8.3 CAL Write DMA YUV422 to YUV422BP Conversion
          4. 10.4.6.8.4 CAL Write DMA Buffer Management
          5. 10.4.6.8.5 CAL Write DMA OCP Address Generation
            1. 10.4.6.8.5.1 Write DMA Buffer Base Address
            2. 10.4.6.8.5.2 Write DMA Line Start Address
            3. 10.4.6.8.5.3 Write DMA Data Address
          6. 10.4.6.8.6 CAL Write DMA OCP Transaction Generation
          7. 10.4.6.8.7 CAL Write DMA Real Time Traffic
        9. 10.4.6.9  CAL Video Port
          1. 10.4.6.9.1 CAL Video Port Overview
          2. 10.4.6.9.2 CAL Video Port Pixel Clock Generation
          3. 10.4.6.9.3 CAL Video Port Video Timing Generator
        10. 10.4.6.10 CAL Registers Shadowing
    5. 10.5 CAMSS Register Manual
      1. 10.5.1 CAMSS Instance Summary
      2. 10.5.2 CAL Registers
        1. 10.5.2.1 CAL Register Summary
        2. 10.5.2.2 CAL Register Description
      3. 10.5.3 CSI2 PHY Registers
        1. 10.5.3.1 CSI2 PHY Register Summary
        2. 10.5.3.2 CSI2 PHY Register Description
  13. 11Video Input Port
    1. 11.1 VIP Overview
    2. 11.2 VIP Environment
    3. 11.3 VIP Integration
    4. 11.4 VIP Functional Description
      1. 11.4.1 VIP Block Diagram
      2. 11.4.2 VIP Software Reset
      3. 11.4.3 VIP Power and Clocks Management
        1. 11.4.3.1 VIP Clocks
        2. 11.4.3.2 VIP Idle Mode
        3. 11.4.3.3 VIP StandBy Mode
      4. 11.4.4 VIP Slice
        1. 11.4.4.1 VIP Slice Processing Path Overview
        2. 11.4.4.2 VIP Slice Processing Path Multiplexers
          1. 11.4.4.2.1 VIP_CSC Multiplexers
          2. 11.4.4.2.2 VIP_SC Multiplexer
          3. 11.4.4.2.3 Output to VPDMA Multiplexers
        3. 11.4.4.3 VIP Slice Processing Path Examples
          1. 11.4.4.3.1 Input: A=RGB, B=YUV422; Output: A=RGB, B=RGB
          2. 11.4.4.3.2 Input: A=YUV422 8/16, B=YUV422; Output: A=Scaled YUV420, B=RGB
          3. 11.4.4.3.3 Input: A=RGB, B=YUV422; Output: A=RGB, B=Scaled YUV420
          4. 11.4.4.3.4 Input: A=YUV444, B=YUV422; Output: A=YUV422, A=Scaled YUV422, B=YUV422
          5. 11.4.4.3.5 Input: A=YUV444; Output: A=Scaled YUV420, A=YUV420
          6. 11.4.4.3.6 Input: A=YUV444; Output: A=Scaled YUV420, A=YUV444
          7. 11.4.4.3.7 Input: A=YUV422 8/16; Output: A=Scaled YUV420, A=YUV444
          8. 11.4.4.3.8 Input: A=YUV422 8/16, B=YUV422; Output: A=Scaled YUV420, B=YUV420
          9. 11.4.4.3.9 Input: A=YUV422 8/16, B=YUV422; Output: A=YUV420, B=YUV420
      5. 11.4.5 VIP Parser
        1. 11.4.5.1  Features
        2. 11.4.5.2  Repacker
        3. 11.4.5.3  Analog Video
        4. 11.4.5.4  Digitized Video
        5. 11.4.5.5  Frame Buffers
        6. 11.4.5.6  Input Data Interface
          1. 11.4.5.6.1  8b Interface Mode
          2. 11.4.5.6.2  16b Interface Mode
          3. 11.4.5.6.3  24b Interface Mode
          4. 11.4.5.6.4  Signal Relationships
          5. 11.4.5.6.5  General 5 Pin Interfaces
          6. 11.4.5.6.6  Signal Subsets—4 Pin VSYNC, ACTVID, and FID
          7. 11.4.5.6.7  Signal Subsets—4 Pin VSYNC, HSYNC, and FID
          8. 11.4.5.6.8  Vertical Sync
          9. 11.4.5.6.9  Field ID Determination Using Dedicated Signal
          10. 11.4.5.6.10 Field ID Determination Using VSYNC Skew
          11. 11.4.5.6.11 Rationale for FID Determination By VSYNC Skew
          12. 11.4.5.6.12 ACTVID Framing
          13. 11.4.5.6.13 Ancillary Data Storage in Descrete Sync Mode
        7. 11.4.5.7  BT.656 Style Embedded Sync
          1. 11.4.5.7.1 Data Input
          2. 11.4.5.7.2 Sync Words
          3. 11.4.5.7.3 Error Correction
          4. 11.4.5.7.4 Embedded Sync Ancillary Data
          5. 11.4.5.7.5 Embedded Sync RGB 24-bit Data
        8. 11.4.5.8  Source Multiplexing
          1. 11.4.5.8.1  Multiplexing Scenarios
          2. 11.4.5.8.2  2-Way Multiplexing
          3. 11.4.5.8.3  4-Way Multiplexing
          4. 11.4.5.8.4  Line Multiplexing
          5. 11.4.5.8.5  Super Frame Concept in Line Multiplexing
          6. 11.4.5.8.6  8-bit Data Interface in Line Multiplexing
          7. 11.4.5.8.7  16-bit Data Interface in Line Multiplexing
          8. 11.4.5.8.8  Split Lines in Line Multiplex Mode
          9. 11.4.5.8.9  Meta Data
          10. 11.4.5.8.10 TI Line Mux Mode, Split Lines, and Channel ID Remapping
        9. 11.4.5.9  Channel ID Extraction for 2x/4x Multiplexed Source
          1. 11.4.5.9.1 Channel ID Extraction Overview
          2. 11.4.5.9.2 Channel ID Embedded in Protection Bits for 2- and 4-Way Multiplexing
          3. 11.4.5.9.3 Channel ID Embedded in Horizontal Blanking Pixel Data for 2- and 4-Way Multiplexing
        10. 11.4.5.10 Embedded Sync Mux Modes and Data Bus Widths
        11. 11.4.5.11 Ancillary and Active Video Cropping
        12. 11.4.5.12 Interrupts
        13. 11.4.5.13 VDET Interrupt
        14. 11.4.5.14 Source Video Size
        15. 11.4.5.15 Clipping
        16. 11.4.5.16 Current and Last FID Value
        17. 11.4.5.17 Disable Handling
        18. 11.4.5.18 Picture Size Interrupt
        19. 11.4.5.19 Discrete Sync Signals
          1. 11.4.5.19.1 VBLNK and HBLNK
          2. 11.4.5.19.2 BLNK and ACTVID (1)
          3. 11.4.5.19.3 VBLNK and ACTVID(2)
          4. 11.4.5.19.4 VBLNK and HSYNC
          5. 11.4.5.19.5 VSYNC and HBLNK
          6. 11.4.5.19.6 VSYNC and ACTIVID(1)
          7. 11.4.5.19.7 VSYNC and ACTIVID(2)
          8. 11.4.5.19.8 VSYNC and HSYNC
          9. 11.4.5.19.9 Line and Pixel Capture Examples
        20. 11.4.5.20 VIP Overflow Detection and Recovery
      6. 11.4.6 VIP Color Space Converter (CSC)
        1. 11.4.6.1 CSC Features
        2. 11.4.6.2 CSC Functional Description
          1. 11.4.6.2.1 HDTV Application
            1. 11.4.6.2.1.1 HDTV Application with Video Data Range
            2. 11.4.6.2.1.2 HDTV Application with Graphics Data Range
            3. 11.4.6.2.1.3 Quantized Coefficients for Color Space Converter in HDTV
          2. 11.4.6.2.2 SDTV Application
            1. 11.4.6.2.2.1 SDTV Application with Video Data Range
            2. 11.4.6.2.2.2 SDTV Application with Graphics Data Range
            3. 11.4.6.2.2.3 Quantized Coefficients for Color Space Converter in SDTV
        3. 11.4.6.3 CSC Bypass Mode
      7. 11.4.7 VIP Scaler (SC)
        1. 11.4.7.1 SC Features
        2. 11.4.7.2 SC Functional Description
          1. 11.4.7.2.1 Trimmer
          2. 11.4.7.2.2 2084
          3. 11.4.7.2.3 Peaking
          4. 11.4.7.2.4 Vertical Scaler
            1. 11.4.7.2.4.1 Running Average Filter
            2. 11.4.7.2.4.2 Vertical Scaler Configuration Parameters
          5. 11.4.7.2.5 Horizontal Scaler
            1. 11.4.7.2.5.1 Half Decimation Filter
            2. 11.4.7.2.5.2 Polyphase Filter
            3. 11.4.7.2.5.3 Nonlinear Horizontal Scaling
            4. 11.4.7.2.5.4 Horizontal Scaler Configuration Registers
          6. 11.4.7.2.6 Basic Configurations
          7. 11.4.7.2.7 Coefficient Memory
            1. 11.4.7.2.7.1 Overview
            2. 11.4.7.2.7.2 Physical Coefficient SRAM Layout
            3. 11.4.7.2.7.3 Scaler Coefficients Packing on 128-bit VPI Control I/F
            4. 11.4.7.2.7.4 VPI Control I/F Memory Map for Scaler Coefficients
            5. 11.4.7.2.7.5 VPI Control Interface
            6. 11.4.7.2.7.6 Coefficient Table Selection Guide
        3. 11.4.7.3 SC Code
          1. 11.4.7.3.1 Generate Coefficient Memory Image
          2. 11.4.7.3.2 Scaler Configuration Calculation
          3. 11.4.7.3.3 Typical Configuration Values
        4. 11.4.7.4 SC Coefficient Data Files
          1. 11.4.7.4.1 HS Polyphase Filter Coefficients
            1. 11.4.7.4.1.1 ppfcoef_scale_eq_1_32_phases_flip.dat
            2. 11.4.7.4.1.2 ppfcoef_scale_eq_8div16_32_phases_flip.dat
            3. 11.4.7.4.1.3 ppfcoef_scale_eq_9div16_32_phases_flip.dat
            4. 11.4.7.4.1.4 ppfcoef_scale_eq_10div16_32_phases_flip.dat
            5. 11.4.7.4.1.5 ppfcoef_scale_eq_11div16_32_phases_flip.dat
            6. 11.4.7.4.1.6 ppfcoef_scale_eq_12div16_32_phases_flip.dat
            7. 11.4.7.4.1.7 ppfcoef_scale_eq_13div16_32_phases_flip.dat
            8. 11.4.7.4.1.8 ppfcoef_scale_eq_14div16_32_phases_flip.dat
            9. 11.4.7.4.1.9 ppfcoef_scale_eq_15div16_32_phases_flip.dat
          2. 11.4.7.4.2 VS Polyphase Filter Coefficients
            1. 11.4.7.4.2.1 ppfcoef_scale_eq_1_32_phases_ver_5tap_flip.dat
            2. 11.4.7.4.2.2 ppfcoef_scale_eq_3_32_phases_flip.dat
            3. 11.4.7.4.2.3 ppfcoef_scale_eq_4_32_phases_flip.dat
            4. 11.4.7.4.2.4 ppfcoef_scale_eq_5_32_phases_flip.dat
            5. 11.4.7.4.2.5 ppfcoef_scale_eq_6_32_phases_flip.dat
            6. 11.4.7.4.2.6 ppfcoef_scale_eq_7_32_phases_flip.dat
              1. 11.4.7.4.2.6.1 ppfcoef_scale_eq_8div16_32_phases_ver_5tap_flip.dat
              2. 11.4.7.4.2.6.2 ppfcoef_scale_eq_9div16_32_phases_ver_5tap_flip.dat
              3. 11.4.7.4.2.6.3 ppfcoef_scale_eq_10div16_32_phases_ver_5tap_flip.dat
              4. 11.4.7.4.2.6.4 ppfcoef_scale_eq_11div16_32_phases_ver_5tap_flip.dat
              5. 11.4.7.4.2.6.5 ppfcoef_scale_eq_12div16_32_phases_ver_5tap_flip.dat
              6. 11.4.7.4.2.6.6 ppfcoef_scale_eq_13div16_32_phases_ver_5tap_flip.dat
              7. 11.4.7.4.2.6.7 ppfcoef_scale_eq_14div16_32_phases_ver_5tap_flip.dat
              8. 11.4.7.4.2.6.8 ppfcoef_scale_eq_15div16_32_phases_ver_5tap_flip.dat
          3. 11.4.7.4.3 VS (Bilinear Filter Coefficients)
            1. 11.4.7.4.3.1 ppfcoef_scale_eq_1_32_phases_flip_PPF3_peak5_gain_eq_1_25.dat
      8. 11.4.8 VIP Video Port Direct Memory Access (VPDMA)
        1. 11.4.8.1  VPDMA Introduction
        2. 11.4.8.2  VPDMA Basic Definitions
          1. 11.4.8.2.1 Client
          2. 11.4.8.2.2 Channel
          3. 11.4.8.2.3 List
          4. 11.4.8.2.4 Data Formats Supported
        3. 11.4.8.3  2141
        4. 11.4.8.4  VPDMA Client Buffering and Functionality
        5. 11.4.8.5  VPDMA Channels Assignment
        6. 11.4.8.6  VPDMA MFLAG Mechanism
        7. 11.4.8.7  VPDMA Interrupts
        8. 11.4.8.8  VPDMA Descriptors
          1. 11.4.8.8.1 Data Transfer Descriptors
            1. 11.4.8.8.1.1 Data Packet Descriptor Word 0 (Data)
              1. 11.4.8.8.1.1.1 Data Type
              2. 11.4.8.8.1.1.2 Notify
              3. 11.4.8.8.1.1.3 Field
              4. 11.4.8.8.1.1.4 Even Line Skip
              5. 11.4.8.8.1.1.5 Odd Line Skip
              6. 11.4.8.8.1.1.6 Line Stride
            2. 11.4.8.8.1.2 Data Packet Descriptor Word 1
              1. 11.4.8.8.1.2.1 Line Length
              2. 11.4.8.8.1.2.2 Transfer Height
            3. 11.4.8.8.1.3 Data Packet Descriptor Word 2
              1. 11.4.8.8.1.3.1 Start Address
            4. 11.4.8.8.1.4 Data Packet Descriptor Word 3
              1. 11.4.8.8.1.4.1 Packet Type
              2. 11.4.8.8.1.4.2 Mode
              3. 11.4.8.8.1.4.3 Direction
              4. 11.4.8.8.1.4.4 Channel
              5. 11.4.8.8.1.4.5 Priority
              6. 11.4.8.8.1.4.6 Next Channel
            5. 11.4.8.8.1.5 Data Packet Descriptor Word 4
              1. 11.4.8.8.1.5.1 Inbound data
                1. 11.4.8.8.1.5.1.1 Frame Width
                2. 11.4.8.8.1.5.1.2 Frame Height
              2. 11.4.8.8.1.5.2 Outbound data
                1. 11.4.8.8.1.5.2.1 Descriptor Write Address
                2. 11.4.8.8.1.5.2.2 Write Descriptor
                3. 11.4.8.8.1.5.2.3 Drop Data
            6. 11.4.8.8.1.6 Data Packet Descriptor Word 5
              1. 11.4.8.8.1.6.1 Outbound data
                1. 11.4.8.8.1.6.1.1 Max Width
                2. 11.4.8.8.1.6.1.2 Max Height
          2. 11.4.8.8.2 Configuration Descriptor
            1. 11.4.8.8.2.1 Configuration Descriptor Header Word0
            2. 11.4.8.8.2.2 Configuration Descriptor Header Word1
              1. 11.4.8.8.2.2.1 Number of Data Words
            3. 11.4.8.8.2.3 Configuration Descriptor Header Word2
              1. 11.4.8.8.2.3.1 Payload Location
            4. 11.4.8.8.2.4 Configuration Descriptor Header Word3
              1. 11.4.8.8.2.4.1 Packet Type
              2. 11.4.8.8.2.4.2 Direct
              3. 11.4.8.8.2.4.3 Class
                1. 11.4.8.8.2.4.3.1 Address Data Block Format
              4. 11.4.8.8.2.4.4 Destination
              5. 11.4.8.8.2.4.5 Descriptor Length
          3. 11.4.8.8.3 Control Descriptor
            1. 11.4.8.8.3.1 Generic Control Descriptor Format
            2. 11.4.8.8.3.2 Control Descriptor Header Description
              1. 11.4.8.8.3.2.1 Packet Type
              2. 11.4.8.8.3.2.2 Source
              3. 11.4.8.8.3.2.3 Control
            3. 11.4.8.8.3.3 Control Descriptor Types
              1. 11.4.8.8.3.3.1 Sync on Client
              2. 11.4.8.8.3.3.2 Sync on List
              3. 11.4.8.8.3.3.3 Sync on External Event
              4. 11.4.8.8.3.3.4 Sync on Channel
              5. 11.4.8.8.3.3.5 Sync on LM Timer
              6. 11.4.8.8.3.3.6 Change Client Interrupt
              7. 11.4.8.8.3.3.7 Send Interrupt
              8. 11.4.8.8.3.3.8 Reload List
              9. 11.4.8.8.3.3.9 Abort Channel
        9. 11.4.8.9  VPDMA Configuration
          1. 11.4.8.9.1 Regular List
          2. 11.4.8.9.2 Video Input Ports
            1. 11.4.8.9.2.1 Multiplexed Data Streams
            2. 11.4.8.9.2.2 Single YUV Color Separate
            3. 11.4.8.9.2.3 Dual YUV Interleaved
        10. 11.4.8.10 VPDMA Data Formats
          1. 11.4.8.10.1 YUV Data Formats
            1. 11.4.8.10.1.1 Y 4:4:4 (Data Type 0)
            2. 11.4.8.10.1.2 Y 4:2:2 (Data Type 1)
            3. 11.4.8.10.1.3 Y 4:2:0 (Data Type 2)
            4. 11.4.8.10.1.4 C 4:4:4 (Data Type 4)
            5. 11.4.8.10.1.5 C 4:2:2 (Data Type 5)
            6. 11.4.8.10.1.6 C 4:2:0 (Data Type 6)
            7. 11.4.8.10.1.7 YC 4:2:2 (Data Type 7)
            8. 11.4.8.10.1.8 YC 4:4:4 (Data Type 8)
            9. 11.4.8.10.1.9 CY 4:2:2 (Data Type 23)
          2. 11.4.8.10.2 RGB Data Formats
            1. 11.4.8.10.2.1  RGB16-565 (Data Type 0)
            2. 11.4.8.10.2.2  ARGB-1555 (Data Type 1)
            3. 11.4.8.10.2.3  ARGB-4444 (Data Type 2)
            4. 11.4.8.10.2.4  RGBA-5551 (Data Type 3)
            5. 11.4.8.10.2.5  RGBA-4444 (Data Type 4)
            6. 11.4.8.10.2.6  ARGB24-6666 (Data Type 5)
            7. 11.4.8.10.2.7  RGB24-888 (Data Type 6)
            8. 11.4.8.10.2.8  ARGB32-8888 (Data Type 7)
            9. 11.4.8.10.2.9  RGBA24-6666 (Data Type 8)
            10. 11.4.8.10.2.10 RGBA32-8888 (Data Type 9)
          3. 11.4.8.10.3 Miscellaneous Data Type
    5. 11.5 VIP Register Manual
      1. 11.5.1 VIP Instance Summary
      2. 11.5.2 VIP Top Level Registers
        1. 11.5.2.1 VIP Top Level Register Summary
        2. 11.5.2.2 VIP Top Level Register Description
      3. 11.5.3 VIP Parser Registers
        1. 11.5.3.1 VIP Parser Register Summary
        2. 11.5.3.2 VIP Parser Register Description
      4. 11.5.4 VIP CSC Registers
        1. 11.5.4.1 VIP CSC Register Summary
        2. 11.5.4.2 VIP CSC Register Description
      5. 11.5.5 VIP SC registers
        1. 11.5.5.1 VIP SC Register Summary
        2. 11.5.5.2 VIP SC Register Description
      6. 11.5.6 VIP VPDMA Registers
        1. 11.5.6.1 VIP VPDMA Register Summary
        2. 11.5.6.2 VIP VPDMA Register Description
  14. 12Video Processing Engine
    1. 12.1 VPE Overview
    2. 12.2 VPE Integration
    3. 12.3 VPE Functional Description
      1. 12.3.1  VPE Block Diagram
      2. 12.3.2  VPE VC1 Range Mapping/Range Reduction
      3. 12.3.3  VPE Deinterlacer (DEI)
        1. 12.3.3.1 Functional Description
        2. 12.3.3.2 Bypass Mode
        3. 12.3.3.3 2263
          1. 12.3.3.3.1 VPDMA Interface
          2. 12.3.3.3.2 MDT
          3. 12.3.3.3.3 EDI
          4. 12.3.3.3.4 FMD
          5. 12.3.3.3.5 MUX
          6. 12.3.3.3.6 LINE BUFFER
      4. 12.3.4  VPE Scaler (SC)
        1. 12.3.4.1 SC Features
        2. 12.3.4.2 SC Functional Description
          1. 12.3.4.2.1 Trimmer
          2. 12.3.4.2.2 2274
          3. 12.3.4.2.3 Peaking
          4. 12.3.4.2.4 Vertical Scaler
            1. 12.3.4.2.4.1 Running Average Filter
            2. 12.3.4.2.4.2 Vertical Scaler Configuration Parameters
          5. 12.3.4.2.5 Horizontal Scaler
            1. 12.3.4.2.5.1 Half Decimation Filter
            2. 12.3.4.2.5.2 Polyphase Filter
            3. 12.3.4.2.5.3 Nonlinear Horizontal Scaling
            4. 12.3.4.2.5.4 Horizontal Scaler Configuration Registers
          6. 12.3.4.2.6 Basic Configurations
          7. 12.3.4.2.7 Coefficient Memory
            1. 12.3.4.2.7.1 Overview
            2. 12.3.4.2.7.2 Physical Coefficient SRAM Layout
            3. 12.3.4.2.7.3 Scaler Coefficients Packing on 128-bit VPI Control I/F
            4. 12.3.4.2.7.4 VPI Control I/F Memory Map for Scaler Coefficients
            5. 12.3.4.2.7.5 VPI Control Interface
            6. 12.3.4.2.7.6 Coefficient Table Selection Guide
        3. 12.3.4.3 SC Code
          1. 12.3.4.3.1 Generate Coefficient Memory Image
          2. 12.3.4.3.2 Scaler Configuration Calculation
          3. 12.3.4.3.3 Typical Configuration Values
        4. 12.3.4.4 SC Coefficient Data Files
          1. 12.3.4.4.1 HS Polyphase Filter Coefficients
            1. 12.3.4.4.1.1 ppfcoef_scale_eq_1_32_phases_flip.dat
            2. 12.3.4.4.1.2 ppfcoef_scale_eq_8div16_32_phases_flip.dat
            3. 12.3.4.4.1.3 ppfcoef_scale_eq_9div16_32_phases_flip.dat
            4. 12.3.4.4.1.4 ppfcoef_scale_eq_10div16_32_phases_flip.dat
            5. 12.3.4.4.1.5 ppfcoef_scale_eq_11div16_32_phases_flip.dat
            6. 12.3.4.4.1.6 ppfcoef_scale_eq_12div16_32_phases_flip.dat
            7. 12.3.4.4.1.7 ppfcoef_scale_eq_13div16_32_phases_flip.dat
            8. 12.3.4.4.1.8 ppfcoef_scale_eq_14div16_32_phases_flip.dat
            9. 12.3.4.4.1.9 ppfcoef_scale_eq_15div16_32_phases_flip.dat
          2. 12.3.4.4.2 VS Polyphase Filter Coefficients
            1. 12.3.4.4.2.1 ppfcoef_scale_eq_1_32_phases_ver_5tap_flip.dat
            2. 12.3.4.4.2.2 ppfcoef_scale_eq_3_32_phases_flip.dat
            3. 12.3.4.4.2.3 ppfcoef_scale_eq_4_32_phases_flip.dat
            4. 12.3.4.4.2.4 ppfcoef_scale_eq_5_32_phases_flip.dat
            5. 12.3.4.4.2.5 ppfcoef_scale_eq_6_32_phases_flip.dat
            6. 12.3.4.4.2.6 ppfcoef_scale_eq_7_32_phases_flip.dat
              1. 12.3.4.4.2.6.1 ppfcoef_scale_eq_8div16_32_phases_ver_5tap_flip.dat
              2. 12.3.4.4.2.6.2 ppfcoef_scale_eq_9div16_32_phases_ver_5tap_flip.dat
              3. 12.3.4.4.2.6.3 ppfcoef_scale_eq_10div16_32_phases_ver_5tap_flip.dat
              4. 12.3.4.4.2.6.4 ppfcoef_scale_eq_11div16_32_phases_ver_5tap_flip.dat
              5. 12.3.4.4.2.6.5 ppfcoef_scale_eq_12div16_32_phases_ver_5tap_flip.dat
              6. 12.3.4.4.2.6.6 ppfcoef_scale_eq_13div16_32_phases_ver_5tap_flip.dat
              7. 12.3.4.4.2.6.7 ppfcoef_scale_eq_14div16_32_phases_ver_5tap_flip.dat
              8. 12.3.4.4.2.6.8 ppfcoef_scale_eq_15div16_32_phases_ver_5tap_flip.dat
              9. 12.3.4.4.2.6.9 ppcoef_scale_1x_ver_5tap.dat
          3. 12.3.4.4.3 VS (Bilinear Filter Coefficients)
            1. 12.3.4.4.3.1 ppfcoef_scale_eq_1_32_phases_flip_PPF3_peak5_gain_eq_1_25.dat
      5. 12.3.5  VPE Color Space Converter (CSC)
        1. 12.3.5.1 CSC Features
        2. 12.3.5.2 CSC Functional Description
        3. 12.3.5.3 2328
          1. 12.3.5.3.1 HDTV Application
            1. 12.3.5.3.1.1 HDTV Application with Video Data Range
            2. 12.3.5.3.1.2 HDTV Application with Graphics Data Range
            3. 12.3.5.3.1.3 Quantized Coefficients for Color Space Converter in HDTV
          2. 12.3.5.3.2 SDTV Application
            1. 12.3.5.3.2.1 SDTV Application with Video Data Range
            2. 12.3.5.3.2.2 SDTV Application with Graphics Data Range
            3. 12.3.5.3.2.3 Quantized Coefficients for Color Space Converter in SDTV
        4. 12.3.5.4 CSC Bypass Mode
      6. 12.3.6  VPE Chroma Up-Sampler (CHR_US)
        1. 12.3.6.1 Features
        2. 12.3.6.2 Functional Description
        3. 12.3.6.3 For Interlaced YUV420 Input Data
        4. 12.3.6.4 Edge Effects
        5. 12.3.6.5 Modes of Operation (VPDMA)
        6. 12.3.6.6 Coefficient Configuration
      7. 12.3.7  VPE Chroma Down-Sampler (CHR_DS)
      8. 12.3.8  VPE YUV422 to YUV444 Conversion
      9. 12.3.9  VPE Video Port Direct Memory Access (VPDMA)
        1. 12.3.9.1 VPDMA Introduction
        2. 12.3.9.2 VPDMA Basic Definitions
          1. 12.3.9.2.1 Client
          2. 12.3.9.2.2 Channel
          3. 12.3.9.2.3 List
          4. 12.3.9.2.4 Data Formats Supported
        3. 12.3.9.3 VPDMA Client Buffering and Functionality
        4. 12.3.9.4 VPDMA Channels Assignment
        5. 12.3.9.5 VPDMA Interrupts
        6. 12.3.9.6 VPDMA Descriptors
          1. 12.3.9.6.1 Data Transfer Descriptors
            1. 12.3.9.6.1.1 Data Packet Descriptor Word 0 (Data)
              1. 12.3.9.6.1.1.1 Data Type
              2. 12.3.9.6.1.1.2 Notify
              3. 12.3.9.6.1.1.3 Field
              4. 12.3.9.6.1.1.4 1D
              5. 12.3.9.6.1.1.5 Even Line Skip
              6. 12.3.9.6.1.1.6 Odd Line Skip
              7. 12.3.9.6.1.1.7 Line Stride
            2. 12.3.9.6.1.2 Data Packet Descriptor Word 1
              1. 12.3.9.6.1.2.1 Line Length
              2. 12.3.9.6.1.2.2 Transfer Height
            3. 12.3.9.6.1.3 Data Packet Descriptor Word 2
              1. 12.3.9.6.1.3.1 Start Address
            4. 12.3.9.6.1.4 Data Packet Descriptor Word 3
              1. 12.3.9.6.1.4.1 Packet Type
              2. 12.3.9.6.1.4.2 Mode
              3. 12.3.9.6.1.4.3 Direction
              4. 12.3.9.6.1.4.4 Channel
              5. 12.3.9.6.1.4.5 Priority
              6. 12.3.9.6.1.4.6 Next Channel
            5. 12.3.9.6.1.5 Data Packet Descriptor Word 4
              1. 12.3.9.6.1.5.1 Inbound data
                1. 12.3.9.6.1.5.1.1 Frame Width
                2. 12.3.9.6.1.5.1.2 Frame Height
              2. 12.3.9.6.1.5.2 Outbound data
                1. 12.3.9.6.1.5.2.1 Descriptor Write Address
                2. 12.3.9.6.1.5.2.2 Write Descriptor
                3. 12.3.9.6.1.5.2.3 Drop Data
                4. 12.3.9.6.1.5.2.4 Use Descriptor Register
            6. 12.3.9.6.1.6 Data Packet Descriptor Word 5
              1. 12.3.9.6.1.6.1 Outbound data
                1. 12.3.9.6.1.6.1.1 Max Width
                2. 12.3.9.6.1.6.1.2 Max Height
            7. 12.3.9.6.1.7 Data Packet Descriptor Word 6/7 (Data)
          2. 12.3.9.6.2 Configuration Descriptor
            1. 12.3.9.6.2.1 Configuration Descriptor Header Word0
            2. 12.3.9.6.2.2 Configuration Descriptor Header Word1
              1. 12.3.9.6.2.2.1 Number of Data Words
            3. 12.3.9.6.2.3 Configuration Descriptor Header Word2
              1. 12.3.9.6.2.3.1 Payload Location
            4. 12.3.9.6.2.4 Configuration Descriptor Header Word3
              1. 12.3.9.6.2.4.1 Packet Type
              2. 12.3.9.6.2.4.2 Direct
              3. 12.3.9.6.2.4.3 Class
                1. 12.3.9.6.2.4.3.1 Address Data Block Format
              4. 12.3.9.6.2.4.4 Destination
              5. 12.3.9.6.2.4.5 Descriptor Length
          3. 12.3.9.6.3 Control Descriptor
            1. 12.3.9.6.3.1 Generic Control Descriptor Format
            2. 12.3.9.6.3.2 Control Descriptor Header Description
              1. 12.3.9.6.3.2.1 Packet Type
              2. 12.3.9.6.3.2.2 Source
              3. 12.3.9.6.3.2.3 Control
            3. 12.3.9.6.3.3 Control Descriptor Types
              1. 12.3.9.6.3.3.1 Sync on Client
              2. 12.3.9.6.3.3.2 Sync on List
              3. 12.3.9.6.3.3.3 Sync on External Event
              4. 12.3.9.6.3.3.4 Sync on Channel
              5. 12.3.9.6.3.3.5 Sync on LM Timer
              6. 12.3.9.6.3.3.6 Change Client Interrupt
              7. 12.3.9.6.3.3.7 Send Interrupt
              8. 12.3.9.6.3.3.8 Reload List
              9. 12.3.9.6.3.3.9 Abort Channel
        7. 12.3.9.7 VPDMA Configuration
          1. 12.3.9.7.1 Regular List
          2. 12.3.9.7.2 Video Input Ports
            1. 12.3.9.7.2.1 Single YUV Color Separate
            2. 12.3.9.7.2.2 Dual YUV Interleaved
            3. 12.3.9.7.2.3 Single RGB Stream
        8. 12.3.9.8 VPDMA Data Formats
          1. 12.3.9.8.1 YUV Data Formats
            1. 12.3.9.8.1.1 Y 4:4:4 (Data Type 0)
            2. 12.3.9.8.1.2 Y 4:2:2 (Data Type 1)
            3. 12.3.9.8.1.3 Y 4:2:0 (Data Type 2)
            4. 12.3.9.8.1.4 C 4:4:4 (Data Type 4)
            5. 12.3.9.8.1.5 C 4:2:2 (Data Type 5)
            6. 12.3.9.8.1.6 C 4:2:0 (Data Type 6)
            7. 12.3.9.8.1.7 YC 4:2:2 (Data Type 7)
            8. 12.3.9.8.1.8 YC 4:4:4 (Data Type 8)
            9. 12.3.9.8.1.9 CY 4:2:2 (Data Type 23)
          2. 12.3.9.8.2 RGB Data Formats
            1. 12.3.9.8.2.1 Input Data Formats
              1. 12.3.9.8.2.1.1  RGB16-565 (Data Type 0)
              2. 12.3.9.8.2.1.2  ARGB-1555 (Data Type 1)
              3. 12.3.9.8.2.1.3  ARGB-4444 (Data Type 2)
              4. 12.3.9.8.2.1.4  RGBA-5551 (Data Type 3)
              5. 12.3.9.8.2.1.5  RGBA-4444 (Data Type 4)
              6. 12.3.9.8.2.1.6  ARGB24-6666 (Data Type 5)
              7. 12.3.9.8.2.1.7  RGB24-888 (Data Type 6)
              8. 12.3.9.8.2.1.8  ARGB32-8888 (Data Type 7)
              9. 12.3.9.8.2.1.9  RGBA24-6666 (Data Type 8)
              10. 12.3.9.8.2.1.10 RGBA32-8888 (Data Type 9)
            2. 12.3.9.8.2.2 Output Data Formats
              1. 12.3.9.8.2.2.1  RGB16-565 (Data Type 0)
              2. 12.3.9.8.2.2.2  ARGB-1555 (Data Type 1)
              3. 12.3.9.8.2.2.3  ARGB-4444 (Data Type 2)
              4. 12.3.9.8.2.2.4  RGBA-5551 (Data Type 3)
              5. 12.3.9.8.2.2.5  RGBA-4444 (Data Type 4)
              6. 12.3.9.8.2.2.6  ARGB24-6666 (Data Type 5)
              7. 12.3.9.8.2.2.7  RGB24-888 (Data Type 6)
              8. 12.3.9.8.2.2.8  ARGB32-8888 (Data Type 7)
              9. 12.3.9.8.2.2.9  RGBA24-6666 (Data Type 8)
              10. 12.3.9.8.2.2.10 RGBA32-8888 (Data Type 9)
          3. 12.3.9.8.3 Miscellaneous Data Type
      10. 12.3.10 VPE Software Reset
      11. 12.3.11 VPE Power and Clocks Management
        1. 12.3.11.1 VPE Clocks
        2. 12.3.11.2 VPE Idle Mode
        3. 12.3.11.3 VPE StandBy Mode
    4. 12.4 VPE Register Manual
      1. 12.4.1 VPE Instance Summary
      2. 12.4.2 VPE_CSC Registers
        1. 12.4.2.1 VPE_CSC Register Summary
        2. 12.4.2.2 VPE_CSC Register Description
      3. 12.4.3 VPE_SC Registers
        1. 12.4.3.1 VPE_SC Register Summary
        2. 12.4.3.2 VPE_SC Register Description
      4. 12.4.4 VPE_CHR_US Registers
        1. 12.4.4.1 VPE_CHR_US Register Summary
        2. 12.4.4.2 VPE_CHR_US Register Description
      5. 12.4.5 VPE_DEI Registers
        1. 12.4.5.1 VPE_DEI Register Summary
        2. 12.4.5.2 VPE_DEI Register Description
      6. 12.4.6 VPE_VPDMA Registers
        1. 12.4.6.1 VPE_VPDMA Register Summary
        2. 12.4.6.2 VPE_VPDMA Register Description
      7. 12.4.7 VPE_TOP_LEVEL Registers
        1. 12.4.7.1 VPE_TOP_LEVEL Register Summary
        2. 12.4.7.2 VPE_TOP_LEVEL Register Description
  15. 13Display Subsystem
    1. 13.1 Display Subsystem Overview
      1. 13.1.1 Display Subsystem Environment
        1. 13.1.1.1 Display Subsystem LCD Support
          1. 13.1.1.1.1 Display Subsystem LCD with Parallel Interfaces
        2. 13.1.1.2 Display Subsystem TV Display Support
          1. 13.1.1.2.1 Display Subsystem TV With Parallel Interfaces
          2. 13.1.1.2.2 Display Subsystem TV With Serial Interfaces
      2. 13.1.2 Display Subsystem Integration
        1. 13.1.2.1 Display Subsystem Clocks
        2. 13.1.2.2 Display Subsystem Resets
        3. 13.1.2.3 Display Subsystem Power Management
          1. 13.1.2.3.1 Display Subsystem Standby Mode
          2. 13.1.2.3.2 2501
          3. 13.1.2.3.3 Display Subsystem Wake-Up Mode
      3. 13.1.3 Display Subsystem DPLL Controllers Functional Description
        1. 13.1.3.1 DPLL Controllers Overview
        2. 13.1.3.2 OCP2SCP2 Functional Description
          1. 13.1.3.2.1 OCP2SCP2 Reset
            1. 13.1.3.2.1.1 Hardware Reset
            2. 13.1.3.2.1.2 Software Reset
          2. 13.1.3.2.2 OCP2SCP2 Power Management
            1. 13.1.3.2.2.1 Idle Mode
            2. 13.1.3.2.2.2 Clock Gating
          3. 13.1.3.2.3 OCP2SCP2 Timing Registers
        3. 13.1.3.3 DPLL_VIDEO Functional Description
          1. 13.1.3.3.1 DPLL_VIDEO Controller Architecture
          2. 13.1.3.3.2 DPLL_VIDEO Operations
          3. 13.1.3.3.3 DPLL_VIDEO Error Handling
          4. 13.1.3.3.4 DPLL_VIDEO Software Reset
          5. 13.1.3.3.5 DPLL_VIDEO Power Management
          6. 13.1.3.3.6 DPLL_VIDEO HSDIVIDER Loading Operation
          7. 13.1.3.3.7 DPLL_VIDEO Clock Sequence
          8. 13.1.3.3.8 DPLL_VIDEO Go Sequence
          9. 13.1.3.3.9 DPLL_VIDEO Recommended Values
        4. 13.1.3.4 DPLL_HDMI Functional Description
          1. 13.1.3.4.1  DPLL_HDMI and PLLCTRL_HDMI Overview
          2. 13.1.3.4.2  DPLL_HDMI and PLLCTRL_HDMI Architecture
          3. 13.1.3.4.3  DPLL_HDMI Operations
          4. 13.1.3.4.4  DPLL_HDMI Register Access
          5. 13.1.3.4.5  DPLL_HDMI Error Handling
          6. 13.1.3.4.6  DPLL_HDMI Software Reset
          7. 13.1.3.4.7  DPLL_HDMI Power Management
          8. 13.1.3.4.8  DPLL_HDMI Lock Sequence
          9. 13.1.3.4.9  DPLL_HDMI Go Sequence
          10. 13.1.3.4.10 DPLL_HDMI Recommended Values
      4. 13.1.4 Display Subsystem Programming Guide
      5. 13.1.5 Display Subsystem Register Manual
        1. 13.1.5.1 Display Subsystem Instance Summary
        2. 13.1.5.2 Display Subsystem Registers
          1. 13.1.5.2.1 Display Subsystem Registers Mapping Summary
          2. 13.1.5.2.2 Display Subsystem Register Description
        3. 13.1.5.3 OCP2SCP2 registers
          1. 13.1.5.3.1 OCP2SCP2 Register Summary
          2. 13.1.5.3.2 OCP2SCP Register Description
        4. 13.1.5.4 DPLL_VIDEO Registers
          1. 13.1.5.4.1 DPLL_VIDEO Register Summary
          2. 13.1.5.4.2 DPLL_VIDEO Register Description
        5. 13.1.5.5 DPLL_HDMI Registers
          1. 13.1.5.5.1 DPLL_HDMI Registers Mapping Summary
          2. 13.1.5.5.2 DPLL_HDMI Register Description
        6. 13.1.5.6 HDMI_WP Registers
          1. 13.1.5.6.1 HDMI_WP Registers Mapping Summary
          2. 13.1.5.6.2 HDMI_WP Register Description
        7. 13.1.5.7 DSI Registers
          1. 13.1.5.7.1 DSI Register Summary
          2. 13.1.5.7.2 DSI Register Description
    2. 13.2 Display Controller
      1. 13.2.1 DISPC Overview
      2. 13.2.2 DISPC Environment
        1. 13.2.2.1 DISPC LCD Output and Data Format for the Parallel Interface
        2. 13.2.2.2 DISPC Transaction Timing Diagrams
        3. 13.2.2.3 DISPC TV Output and Data Format for the Parallel Interface
      3. 13.2.3 DISPC Integration
      4. 13.2.4 DISPC Functional Description
        1. 13.2.4.1  DISPC Clock Configuration
        2. 13.2.4.2  DISPC Software Reset
        3. 13.2.4.3  DISPC Power Management
          1. 13.2.4.3.1 DISPC Idle Mode
          2. 13.2.4.3.2 DISPC StandBy Mode
          3. 13.2.4.3.3 DISPC Wakeup
        4. 13.2.4.4  DISPC Interrupt Requests
        5. 13.2.4.5  DISPC DMA Requests
        6. 13.2.4.6  DISPC DMA Engine
          1. 13.2.4.6.1 DISPC Addressing and Bursts
          2. 13.2.4.6.2 DISPC Immediate Base Address Flip Mechanism
          3. 13.2.4.6.3 DISPC DMA Buffers
            1. 13.2.4.6.3.1 DISPC READ DMA Buffers (GFX and VID Pipelines)
            2. 13.2.4.6.3.2 DISPC WRITE DMA Buffer (WB Pipeline)
          4. 13.2.4.6.4 DISPC MFLAG Mechanism and Arbitration
          5. 13.2.4.6.5 DISPC Predecimation
          6. 13.2.4.6.6 DISPC Progressive-to-Interlaced Format Conversion
          7. 13.2.4.6.7 DISPC Arbitration
          8. 13.2.4.6.8 DISPC DMA Power Modes
            1. 13.2.4.6.8.1 DISPC DMA Low-Power Mode
            2. 13.2.4.6.8.2 DISPC DMA Ultralow-Power Mode
        7. 13.2.4.7  DISPC Rotation and Mirroring
        8. 13.2.4.8  DISPC Memory Format
        9. 13.2.4.9  DISPC Graphics Pipeline
          1. 13.2.4.9.1 DISPC Replication Logic
          2. 13.2.4.9.2 DISPC Antiflicker Filter
        10. 13.2.4.10 DISPC Video Pipelines
          1. 13.2.4.10.1 DISPC Replication Logic
          2. 13.2.4.10.2 DISPC VC-1 Range Mapping Unit
          3. 13.2.4.10.3 DISPC CSC Unit YUV to RGB
            1. 13.2.4.10.3.1 DISPC Chrominance Resampling
          4. 13.2.4.10.4 DISPC Scaler Unit
            1. 13.2.4.10.4.1 DISPC Scaling Algorithms
            2. 13.2.4.10.4.2 DISPC Scaling limitations
        11. 13.2.4.11 DISPC Write-Back Pipeline
          1. 13.2.4.11.1 DISPC Write-Back CSC Unit RGB to YUV
          2. 13.2.4.11.2 DISPC Write-Back Scaler Unit
          3. 13.2.4.11.3 DISPC Write-Back RGB Truncation Logic
        12. 13.2.4.12 DISPC Hardware Cursor
        13. 13.2.4.13 DISPC LCD Outputs
          1. 13.2.4.13.1 DISPC Overlay Manager
            1. 13.2.4.13.1.1 DISPC Priority Rule
            2. 13.2.4.13.1.2 DISPC Alpha Blender
            3. 13.2.4.13.1.3 DISPC Transparency Color Keys
            4. 13.2.4.13.1.4 DISPC Overlay Optimization
          2. 13.2.4.13.2 DISPC Gamma Correction Unit
          3. 13.2.4.13.3 DISPC Color Phase Rotation Unit
          4. 13.2.4.13.4 DISPC Color Space Conversion
          5. 13.2.4.13.5 DISPC BT.656 and BT.1120 Modes
            1. 13.2.4.13.5.1 Blanking
            2. 13.2.4.13.5.2 EAV and SAV
          6. 13.2.4.13.6 DISPC Active Matrix
            1. 13.2.4.13.6.1 DISPC Spatial/Temporal Dithering
            2. 13.2.4.13.6.2 DISPC Multiple Cycle Output Format (TDM)
          7. 13.2.4.13.7 DISPC Synchronized Buffer Update
          8. 13.2.4.13.8 DISPC Timing Generator and Panel Settings
        14. 13.2.4.14 DISPC TV Output
          1. 13.2.4.14.1 DISPC Overlay Manager
          2. 13.2.4.14.2 DISPC Gamma Correction Unit
          3. 13.2.4.14.3 DISPC Synchronized Buffer Update
          4. 13.2.4.14.4 DISPC Timing and TV Format Settings
        15. 13.2.4.15 DISPC Frame Width Considerations
        16. 13.2.4.16 DISPC Extended 3D Support
          1. 13.2.4.16.1 DISPC Extended 3D Support - Line Alternative Format
          2. 13.2.4.16.2 2627
          3. 13.2.4.16.3 DISPC Extended 3D Support - Frame Packing Format Format
          4. 13.2.4.16.4 DISPC Extended 3D Support - DLP 3D Format
        17. 13.2.4.17 DISPC Shadow Registers
      5. 13.2.5 DISPC Programming Guide
        1. 13.2.5.1 DISPC Low-Level Programming Models
          1. 13.2.5.1.1 DISPC Global Initialization
            1. 13.2.5.1.1.1 DISPC Surrounding Modules Global Initialization
          2. 13.2.5.1.2 DISPC Operational Modes Configuration
            1. 13.2.5.1.2.1 DISPC DMA Configuration
              1. 13.2.5.1.2.1.1 DISPC Main Sequence – DISPC DMA Channel Configuration
            2. 13.2.5.1.2.2 DISPC GFX Pipeline Configuration
              1. 13.2.5.1.2.2.1 DISPC Main Sequence – Configure the GFX Pipeline
              2. 13.2.5.1.2.2.2 DISPC Subsequence – Configure the GFX Window
              3. 13.2.5.1.2.2.3 DISPC Subsequence – Configure the GFX Pipeline Processing
              4. 13.2.5.1.2.2.4 DISPC Subsequence – Configure the GFX Pipeline Layer Output
            3. 13.2.5.1.2.3 DISPC Video Pipeline Configuration
              1. 13.2.5.1.2.3.1 DISPC Main Sequence – Configure the Video Pipeline
              2. 13.2.5.1.2.3.2 DISPC Subsequence – Configure the Video Window
              3. 13.2.5.1.2.3.3 DISPC Subsequence – Configure the Video Pipeline Processing
              4. 13.2.5.1.2.3.4 DISPC Subsequence – Configure the VC-1 Range Mapping
              5. 13.2.5.1.2.3.5 DISPC Subsequence – Configure the Video Color Space Conversion
              6. 13.2.5.1.2.3.6 DISPC Subsequence – Configure the Video Scaler Unit
              7. 13.2.5.1.2.3.7 DISPC Subsequence – Configure the Video Pipeline Layer Output
            4. 13.2.5.1.2.4 DISPC WB Pipeline Configuration
              1. 13.2.5.1.2.4.1 DISPC Main Sequence – Configure the WB Pipeline
              2. 13.2.5.1.2.4.2 DISPC Subsequence – Configure the Capture Window
              3. 13.2.5.1.2.4.3 DISPC Subsequence – Configure the WB Scaler Unit
              4. 13.2.5.1.2.4.4 DISPC Subsequence – Configure the WB Color Space Conversion Unit
            5. 13.2.5.1.2.5 DISPC LCD Output Configuration
              1. 13.2.5.1.2.5.1 DISPC Main Sequence – Configure the LCD Output
              2. 13.2.5.1.2.5.2 DISPC Subsequence – Configure the Overlay Manager
              3. 13.2.5.1.2.5.3 DISPC Subsequence – Configure the Gamma Table for Gamma Correction
              4. 13.2.5.1.2.5.4 DISPC Subsequence – Configure the Color Phase Rotation
              5. 13.2.5.1.2.5.5 DISPC Subsequence – Configure the LCD Panel Timings and Parameters
              6. 13.2.5.1.2.5.6 DISPC Subsequence – Configure BT.656 or BT.1120 Mode
            6. 13.2.5.1.2.6 DISPC TV Output Configuration
              1. 13.2.5.1.2.6.1 DISPC Main Sequence – Configure the TV Output
                1. 13.2.5.1.2.6.1.1 DISPC Subsequence – Configure the TV Overlay Manager
                2. 13.2.5.1.2.6.1.2 DISPC Subsequence – Configure the Gamma Table for Gamma Correction
                3. 13.2.5.1.2.6.1.3 DISPC Subsequence – Configure the TV Panel Timings and Parameters
      6. 13.2.6 DISPC Register Manual
        1. 13.2.6.1 DISPC Instance Summary
        2. 13.2.6.2 DISPC Logical Register Mapping
        3. 13.2.6.3 DISPC Registers
          1. 13.2.6.3.1 DISPC Register Summary
          2. 13.2.6.3.2 DISPC Register Description
    3. 13.3 High-Definition Multimedia Interface
      1. 13.3.1 HDMI Overview
        1. 13.3.1.1 HDMI Main Features
        2. 13.3.1.2 HDMI Video Formats and Timings
          1. 13.3.1.2.1 HDMI CEA-861-D Video Formats and Timings
          2. 13.3.1.2.2 VESA DMT Video Formats and Timings
  16. 143D Graphics Accelerator
    1. 14.1 GPU Overview
      1. 14.1.1 GPU Features Overview
      2. 14.1.2 Graphics Feature Overview
    2. 14.2 GPU Integration
    3. 14.3 GPU Functional Description
      1. 14.3.1 GPU Block Diagram
      2. 14.3.2 GPU Clock Configuration
      3. 14.3.3 GPU Software Reset
      4. 14.3.4 GPU Power Management
      5. 14.3.5 GPU Thermal Management
      6. 14.3.6 GPU Interrupt Requests
    4. 14.4 GPU Register Manual
      1. 14.4.1 GPU Instance Summary
      2. 14.4.2 GPU Registers
        1. 14.4.2.1 GPU_WRAPPER Register Summary
        2. 14.4.2.2 GPU_WRAPPER Register Description
  17. 152D Graphics Accelerator
    1. 15.1 BB2D Overview
      1. 15.1.1 BB2D Key Features Overview
    2. 15.2 BB2D Integration
    3. 15.3 BB2D Functional Description
      1. 15.3.1 BB2D Block Diagram
      2. 15.3.2 BB2D Clock Configuration
      3. 15.3.3 BB2D Software Reset
      4. 15.3.4 BB2D Power Management
    4. 15.4 BB2D Register Manual
      1. 15.4.1 BB2D Instance Summary
      2. 15.4.2 BB2D Registers
        1. 15.4.2.1 BB2D Register Summary
        2. 15.4.2.2 BB2D Register Description
  18. 16Interconnect
    1. 16.1 Interconnect Overview
      1. 16.1.1 Terminology
      2. 16.1.2 Architecture Overview
    2. 16.2 L3_MAIN Interconnect
      1. 16.2.1 L3_MAIN Interconnect Overview
      2. 16.2.2 L3_MAIN Interconnect Integration
      3. 16.2.3 L3_MAIN Interconnect Functional Description
        1. 16.2.3.1 Module Use in L3_MAIN Interconnect
        2. 16.2.3.2 Module Distribution
          1. 16.2.3.2.1 L3_MAIN Interconnect Agents
          2. 16.2.3.2.2 L3_MAIN Connectivity Matrix
            1. 16.2.3.2.2.1 Clock Domain Mapping of the L3_MAIN Interconnect Modules
            2. 16.2.3.2.2.2 2724
          3. 16.2.3.2.3 Master NIU Identification
        3. 16.2.3.3 Bandwidth Regulators
        4. 16.2.3.4 Bandwidth Limiters
        5. 16.2.3.5 Flag Muxing
          1. 16.2.3.5.1 Flag Mux Time-out
        6. 16.2.3.6 Statistic Collectors Group
        7. 16.2.3.7 L3_MAIN Protection and Firewalls
          1. 16.2.3.7.1 L3_MAIN Firewall Reset
            1. 16.2.3.7.1.1 L3_MAIN Firewall – Exported Reset Values
          2. 16.2.3.7.2 Power Management
          3. 16.2.3.7.3 L3_MAIN Firewall Functionality
            1. 16.2.3.7.3.1 Protection Regions
            2. 16.2.3.7.3.2 L3_MAIN Firewall Registers Overview
            3. 16.2.3.7.3.3 Protection Mechanism per Region Examples
            4. 16.2.3.7.3.4 L3_MAIN Firewall Error Logging
            5. 16.2.3.7.3.5 L3_MAIN Firewall Default Configuration
        8. 16.2.3.8 L3_MAIN Interconnect Error Handling
          1. 16.2.3.8.1 Global Error-Routing Scheme
          2. 16.2.3.8.2 Slave NIU Error Logging
          3. 16.2.3.8.3 Flag Mux Error Logging
          4. 16.2.3.8.4 Severity Level of Standard and Custom Errors
          5. 16.2.3.8.5 Example for Decoding Standard/Custom Errors Logged in L3_MAIN
      4. 16.2.4 L3_MAIN Interconnect Programming Guide
        1. 16.2.4.1 L3 _MAIN Interconnect Low-Level Programming Models
          1. 16.2.4.1.1 Global Initialization
            1. 16.2.4.1.1.1 Global Initialization of Surrounding Modules
        2. 16.2.4.2 Operational Modes Configuration
          1. 16.2.4.2.1 L3_MAIN Interconnect Error Analysis Mode
            1. 16.2.4.2.1.1 Main Sequence: L3_MAIN Interconnect Error Analysis Mode
              1. 16.2.4.2.1.1.1 Subsequence: L3_MAIN Custom Error Identification
              2. 16.2.4.2.1.1.2 Subsequence: L3_MAIN Interconnect Protection Violation Error Identification
              3. 16.2.4.2.1.1.3 Subsequence: L3_MAIN Interconnect Standard Error Identification
              4. 16.2.4.2.1.1.4 Subsequence: L3_MAIN Interconnect FLAGMUX Configuration
      5. 16.2.5 L3_MAIN Interconnect Register Manual
        1. 16.2.5.1 L3_MAIN Register Group Summary
          1. 16.2.5.1.1 L3_MAIN Firewall Registers Summary and Description
            1. 16.2.5.1.1.1 L3_MAIN Firewall Registers Summary
            2. 16.2.5.1.1.2 L3_MAIN Firewall Registers Description
          2. 16.2.5.1.2 L3_MAIN Host Register Summary and Description
            1. 16.2.5.1.2.1 L3_MAIN HOST Register Summary
            2. 16.2.5.1.2.2 L3_MAIN HOST Register Description
          3. 16.2.5.1.3 L3_MAIN TARG Register Summary and Description
            1. 16.2.5.1.3.1 L3_MAIN TARG Register Summary
            2. 16.2.5.1.3.2 L3_MAIN TARG Register Description
          4. 16.2.5.1.4 L3_MAIN FLAGMUX Registers Summary and Description
            1. 16.2.5.1.4.1 L3_MAIN FLAGMUX Registers Summary
            2. 16.2.5.1.4.2 L3_MAIN FLAGMUX Rebisters Description
          5. 16.2.5.1.5 L3_MAIN FLAGMUX CLK1MERGE Registers Summary and Description
            1. 16.2.5.1.5.1 L3_MAIN FLAGMUX CLK1MERGE Registers Summary
            2. 16.2.5.1.5.2 L3_MAIN FLAGMUX CLK1MERGE Registers Description
          6. 16.2.5.1.6 L3_MAIN FLAGMUX TIMEOUT Registers Summary and Description
            1. 16.2.5.1.6.1 L3_MAIN FLAGMUX TIMEOUT Registers Summary
            2. 16.2.5.1.6.2 L3_MAIN FLAGMUX TIMEOUT Registers Description
          7. 16.2.5.1.7 L3_MAIN BW Regulator Register Summary and Description
            1. 16.2.5.1.7.1 L3_MAIN BW_REGULATOR Register Summary
            2. 16.2.5.1.7.2 L3_MAIN BW_REGULATOR Register Description
          8. 16.2.5.1.8 L3_MAIN Bandwidth Limiter Register Summary and Description
            1. 16.2.5.1.8.1 L3_MAIN BW Limiter Register Summary
            2. 16.2.5.1.8.2 L3_MAIN BW Limiter Register Description
          9. 16.2.5.1.9 L3_MAIN STATCOLL Register Summary and Description
            1. 16.2.5.1.9.1 L3_MAIN STATCOLL Register Summary
            2. 16.2.5.1.9.2 L3_MAIN STATCOLL Register Description
    3. 16.3 L4 Interconnects
      1. 16.3.1 L4 Interconnect Overview
      2. 16.3.2 L4 Interconnect Integration
      3. 16.3.3 L4 Interconnect Functional Description
        1. 16.3.3.1 Module Distribution
          1. 16.3.3.1.1 L4_PER1 Interconnect Agents
          2. 16.3.3.1.2 L4_PER2 Interconnect Agents
          3. 16.3.3.1.3 L4_PER3 Interconnect Agents
          4. 16.3.3.1.4 L4_CFG Interconnect Agents
          5. 16.3.3.1.5 L4_WKUP Interconnect Agents
        2. 16.3.3.2 Power Management
        3. 16.3.3.3 L4 Firewalls
          1. 16.3.3.3.1 Protection Group
          2. 16.3.3.3.2 Segments and Regions
          3. 16.3.3.3.3 L4 Firewall Address and Protection Register Settings
        4. 16.3.3.4 L4 Error Detection and Reporting
          1. 16.3.3.4.1 IA and TA Error Detection and Logging
          2. 16.3.3.4.2 Time-Out
          3. 16.3.3.4.3 Error Reporting
          4. 16.3.3.4.4 Error Recovery
          5. 16.3.3.4.5 Firewall Error Logging in the Control Module
      4. 16.3.4 L4 Interconnect Programming Guide
        1. 16.3.4.1 L4 Interconnect Low-level Programming Models
          1. 16.3.4.1.1 Global Initialization
            1. 16.3.4.1.1.1 Surrounding Modules Global Initialization
          2. 16.3.4.1.2 Operational Modes Configuration
            1. 16.3.4.1.2.1 L4 Interconnect Error Analysis Mode
              1. 16.3.4.1.2.1.1 Main Sequence: L4 Interconnect Error Analysis Mode
              2. 16.3.4.1.2.1.2 Subsequence: L4 Interconnect Protection Violation Error Identification
              3. 16.3.4.1.2.1.3 Subsequence: L4 Interconnect Unsupported Command/Address Hole Error Identification
              4. 16.3.4.1.2.1.4 Subsequence: L4 Interconnect Reset TA and Module
            2. 16.3.4.1.2.2 L4 Interconnect Time-Out Configuration Mode
              1. 16.3.4.1.2.2.1 Main Sequence: L4 Interconnect Time-Out Configuration Mode
            3. 16.3.4.1.2.3 L4 Interconnect Firewall Configuration Mode
              1. 16.3.4.1.2.3.1 Main Sequence: L4 Interconnect Firewall Configuration Mode
      5. 16.3.5 L4 Interconnects Register Manual
        1. 16.3.5.1 L4 Interconnects Instance Summary
        2. 16.3.5.2 L4 Initiator Agent (L4 IA)
          1. 16.3.5.2.1 L4 Initiator Agent (L4 IA) Register Summary
          2. 16.3.5.2.2 L4 Initiator Agent (L4 IA) Register Description
        3. 16.3.5.3 L4 Target Agent (L4 TA)
          1. 16.3.5.3.1 L4 Target Agent (L4 TA) Register Summary
          2. 16.3.5.3.2 L4 Target Agent (L4 TA) Register Description
        4. 16.3.5.4 L4 Link Agent (L4 LA)
          1. 16.3.5.4.1 L4 Link Agent (L4 LA) Register Summary
          2. 16.3.5.4.2 L4 Link Agent (L4 LA) Register Description
        5. 16.3.5.5 L4 Address Protection (L4 AP)
          1. 16.3.5.5.1 L4 Address Protection (L4 AP) Register Summary
          2. 16.3.5.5.2 L4 Address Protection (L4 AP) Register Description
  19. 17Memory Subsystem
    1. 17.1 Memory Subsystem Overview
      1. 17.1.1 DMM Overview
      2. 17.1.2 TILER Overview
      3. 17.1.3 EMIF Overview
      4. 17.1.4 GPMC Overview
      5. 17.1.5 ELM Overview
      6. 17.1.6 OCM Overview
    2. 17.2 Dynamic Memory Manager
      1. 17.2.1 DMM Overview
      2. 17.2.2 DMM Integration
        1. 17.2.2.1 DMM Configuration
      3. 17.2.3 DMM Functional Description
        1. 17.2.3.1 DMM Block Diagram
        2. 17.2.3.2 DMM Clock Configuration
        3. 17.2.3.3 DMM Power Management
        4. 17.2.3.4 DMM Interrupt Requests
        5. 17.2.3.5 DMM
          1. 17.2.3.5.1 DMM Concepts
            1. 17.2.3.5.1.1 Dynamic Mapping
            2. 17.2.3.5.1.2 Address Mapping
            3. 17.2.3.5.1.3 Address Translation
              1. 17.2.3.5.1.3.1 PAT View Mappings
              2. 17.2.3.5.1.3.2 PAT View Map Base Address
              3. 17.2.3.5.1.3.3 PAT Views
                1. 17.2.3.5.1.3.3.1 PAT Direct Access Translation
                2. 17.2.3.5.1.3.3.2 PAT Indirect Access Translation
                3. 17.2.3.5.1.3.3.3 PAT View Configuration
                4. 17.2.3.5.1.3.3.4 PAT Address Translation LUT
                5. 17.2.3.5.1.3.3.5 Direct Access to the PAT Table Vectors
                6. 17.2.3.5.1.3.3.6 Automatic Refill Through the Refill Engines
          2. 17.2.3.5.2 DMM Transaction Flows
            1. 17.2.3.5.2.1 Nontiled Transaction Flow
            2. 17.2.3.5.2.2 Tiled Transaction Flow
          3. 17.2.3.5.3 DMM Internal Macro-Architecture
            1. 17.2.3.5.3.1 LISA Description
            2. 17.2.3.5.3.2 PAT Description
            3. 17.2.3.5.3.3 PEG Description
            4. 17.2.3.5.3.4 LISA Interconnect Arbitration
            5. 17.2.3.5.3.5 ROBIN Description
            6. 17.2.3.5.3.6 TILER Description
        6. 17.2.3.6 TILER
          1. 17.2.3.6.1 TILER Concepts
            1. 17.2.3.6.1.1 TILER Rationale
              1. 17.2.3.6.1.1.1 The TILER is a 4-GiB Virtual Address Space Composed of Eight Views
              2. 17.2.3.6.1.1.2 A View is a 512-MiB Virtual Address Space Composed of Four Containers
              3. 17.2.3.6.1.1.3 A Container is a 128-MiB Virtual Address Space
              4. 17.2.3.6.1.1.4 A Page is a 4-kiB Virtual Address Space
              5. 17.2.3.6.1.1.5 A Tile is a 1-kiB Address Space
              6. 17.2.3.6.1.1.6 2885
              7. 17.2.3.6.1.1.7 A Subtile is a 128-Bit Address Space
            2. 17.2.3.6.1.2 TILER Modes
              1. 17.2.3.6.1.2.1 Bypass Mode
              2. 17.2.3.6.1.2.2 Page Mode
              3. 17.2.3.6.1.2.3 Tiled Mode
            3. 17.2.3.6.1.3 Object Container Definition
            4. 17.2.3.6.1.4 Page Definition
              1. 17.2.3.6.1.4.1 Container Geometry With 4-kiB Pages
              2. 17.2.3.6.1.4.2 Container Geometry and Page Mapping Summary
            5. 17.2.3.6.1.5 Orientation
            6. 17.2.3.6.1.6 Tile Definition
            7. 17.2.3.6.1.7 Subtiles
              1. 17.2.3.6.1.7.1 Subtiling Definition
            8. 17.2.3.6.1.8 TILER Virtual Addressing
              1. 17.2.3.6.1.8.1 Page Mode Virtual Addressing and Characteristics
              2. 17.2.3.6.1.8.2 Tiled Mode Virtual Addressing and Characteristics
              3. 17.2.3.6.1.8.3 Element Ordering in the TILER Container
                1. 17.2.3.6.1.8.3.1 Natural View or 0-Degree View (Orientation 0)
                2. 17.2.3.6.1.8.3.2 0-Degree View With Vertical Mirror or 180-Degree View With Horizontal Mirror (Orientation 1)
                3. 17.2.3.6.1.8.3.3 0-Degree View With Horizontal Mirror or 180-Degree View With Vertical Mirror (Orientation 2)
                4. 17.2.3.6.1.8.3.4 180-Degree View (Orientation 3)
                5. 17.2.3.6.1.8.3.5 90-Degree View With Vertical Mirror or 270-Degree View With Horizontal Mirror (Orientation 4)
                6. 17.2.3.6.1.8.3.6 270-Degree View (Orientation 5)
                7. 17.2.3.6.1.8.3.7 90-Degree View (Orientation 6)
                8. 17.2.3.6.1.8.3.8 90-Degree View With Horizontal Mirror or 270-Degree View With Vertical Mirror (Orientation 7)
          2. 17.2.3.6.2 TILER Macro-Architecture
          3. 17.2.3.6.3 TILER Guidelines for Initiators
            1. 17.2.3.6.3.1 Buffered Raster-Based Initiators
              1. 17.2.3.6.3.1.1 Buffer Size
              2. 17.2.3.6.3.1.2 Performance
      4. 17.2.4 DMM Use Cases and Tips
        1. 17.2.4.1 PAT Use Cases
          1. 17.2.4.1.1 Simple Manual Area Refill
          2. 17.2.4.1.2 Single Auto-Configured Area Refill
          3. 17.2.4.1.3 Chained Auto-Configured Area Refill
          4. 17.2.4.1.4 Synchronized Auto-Configured Area Refill
          5. 17.2.4.1.5 Cyclic Synchronized Auto-Configured Area Refill
        2. 17.2.4.2 Addressing Management with LISA
          1. 17.2.4.2.1 Case 1: Use of One Memory Controller
          2. 17.2.4.2.2 Case 2: Use of Two Memory Controllers
            1. 17.2.4.2.2.1 Address Upper Bits Shifting
      5. 17.2.5 DMM Basic Programming Model
        1. 17.2.5.1 Global Initialization
        2. 17.2.5.2 DMM Module Global Initialization
        3. 17.2.5.3 DMM Operational Modes Configuration
          1. 17.2.5.3.1 Different Operational Modes
          2. 17.2.5.3.2 Configuration Settings and LUT Refill
          3. 17.2.5.3.3 Interleaving Settings
          4. 17.2.5.3.4 Aliased Tiled View Orientation Settings and LUT Refill
          5. 17.2.5.3.5 Priority Settings
          6. 17.2.5.3.6 Error Handling
          7. 17.2.5.3.7 PAT Programming Model
            1. 17.2.5.3.7.1 PAT in Direct Translation Mode
            2. 17.2.5.3.7.2 PAT in Indirect Translation Mode
        4. 17.2.5.4 Addressing an Object in Tiled Mode
          1. 17.2.5.4.1 Frame-Buffer Addressing
          2. 17.2.5.4.2 TILER Page Mapping
        5. 17.2.5.5 Addressing an Object in Page Mode
        6. 17.2.5.6 Sharing Containers Between Different Modes
      6. 17.2.6 DMM Register Manual
        1. 17.2.6.1 DMM Instance Summary
        2. 17.2.6.2 DMM Registers
          1. 17.2.6.2.1 DMM Register Summary
          2. 17.2.6.2.2 DMM Register Description
    3. 17.3 EMIF Controller
      1. 17.3.1 EMIF Controller Overview
      2. 17.3.2 EMIF Module Environment
      3. 17.3.3 EMIF Module Integration
      4. 17.3.4 EMIF Functional Description
        1. 17.3.4.1  Block Diagram
          1. 17.3.4.1.1 Local Interface
          2. 17.3.4.1.2 FIFO Description
          3. 17.3.4.1.3 MPU Port Restrictions
          4. 17.3.4.1.4 Arbitration of Commands in the Command FIFO
        2. 17.3.4.2  Clock Management
          1. 17.3.4.2.1 EMIF_FICLK Overview
          2. 17.3.4.2.2 EMIF Dependency on MPU Clock Rate
        3. 17.3.4.3  Reset
        4. 17.3.4.4  System Power Management
          1. 17.3.4.4.1 Power-Down Mode
          2. 17.3.4.4.2 Self-Refresh Mode
        5. 17.3.4.5  Interrupt Requests
        6. 17.3.4.6  SDRAM Refresh Scheduling
        7. 17.3.4.7  SDRAM Initialization
          1. 17.3.4.7.1 DDR2 SDRAM Initialization
          2. 17.3.4.7.2 DDR3 SDRAM Initialization
        8. 17.3.4.8  DDR3 Read-Write Leveling
          1. 17.3.4.8.1 Full Leveling
          2. 17.3.4.8.2 Software Leveling
        9. 17.3.4.9  EMIF Access Cycles
        10. 17.3.4.10 Turnaround Time
        11. 17.3.4.11 PHY DLL Calibration
        12. 17.3.4.12 SDRAM Address Mapping
          1. 17.3.4.12.1 Address Mapping for IBANK_POS = 0 and EBANK_POS = 0
          2. 17.3.4.12.2 Address Mapping for IBANK_POS = 1 and EBANK_POS = 0
          3. 17.3.4.12.3 Address Mapping for IBANK_POS = 2 and EBANK_POS = 0
          4. 17.3.4.12.4 Address Mapping for IBANK_POS = 3 and EBANK_POS = 0
          5. 17.3.4.12.5 Address Mapping for IBANK_POS = 0 and EBANK_POS = 1
          6. 17.3.4.12.6 Address Mapping for IBANK_POS = 1 and EBANK_POS = 1
          7. 17.3.4.12.7 Address Mapping for IBANK_POS = 2 and EBANK_POS = 1
          8. 17.3.4.12.8 2986
          9. 17.3.4.12.9 Address Mapping for IBANK_POS = 3 and EBANK_POS = 1
        13. 17.3.4.13 DDR3 Output Impedance Calibration
        14. 17.3.4.14 Error Correction And Detection Feature
          1. 17.3.4.14.1 Read-Modify-Write Module
        15. 17.3.4.15 Class of Service
        16. 17.3.4.16 Performance Counters
          1. 17.3.4.16.1 Performance Counters General Examples
        17. 17.3.4.17 Forcing CKE to tri-state
      5. 17.3.5 EMIF Programming Guide
        1. 17.3.5.1 EMIF Low-Level Programming Models
          1. 17.3.5.1.1 Global Initialization
            1. 17.3.5.1.1.1 EMIF Configuration Sequence
          2. 17.3.5.1.2 Operational Modes Configuration
            1. 17.3.5.1.2.1 EMIF Output Impedance Calibration Mode
            2. 17.3.5.1.2.2 EMIF SDRAM Self-Refresh
            3. 17.3.5.1.2.3 EMIF SDRAM Power-Down Mode
            4. 17.3.5.1.2.4 EMIF ECC Configuration
      6. 17.3.6 EMIF Register Manual
        1. 17.3.6.1 EMIF Instance Summary
        2. 17.3.6.2 EMIF Registers
          1. 17.3.6.2.1 EMIF Register Summary
          2. 17.3.6.2.2 EMIF Register Description
    4. 17.4 General-Purpose Memory Controller
      1. 17.4.1 GPMC Overview
      2. 17.4.2 GPMC Environment
        1. 17.4.2.1 GPMC Modes
        2. 17.4.2.2 GPMC Signals
      3. 17.4.3 GPMC Integration
      4. 17.4.4 GPMC Functional Description
        1. 17.4.4.1  GPMC Block Diagram
        2. 17.4.4.2  GPMC Clock Configuration
        3. 17.4.4.3  GPMC Software Reset
        4. 17.4.4.4  GPMC Power Management
        5. 17.4.4.5  GPMC Interrupt Requests
        6. 17.4.4.6  L3 Interconnect Interface
        7. 17.4.4.7  GPMC Address and Data Bus
          1. 17.4.4.7.1 GPMC I/O Configuration Setting
          2. 17.4.4.7.2 GPMC CS0 Default Configuration at Device Reset
        8. 17.4.4.8  Address Decoder and Chip-Select Configuration
          1. 17.4.4.8.1 Chip-Select Base Address and Region Size
          2. 17.4.4.8.2 Access Protocol
            1. 17.4.4.8.2.1 Supported Devices
            2. 17.4.4.8.2.2 Access Size Adaptation and Device Width
            3. 17.4.4.8.2.3 Address/Data-Multiplexing Interface
          3. 17.4.4.8.3 External Signals
            1. 17.4.4.8.3.1 Wait Pin Monitoring Control
              1. 17.4.4.8.3.1.1 Wait Monitoring During Asynchronous Read Access
              2. 17.4.4.8.3.1.2 Wait Monitoring During Asynchronous Write Access
              3. 17.4.4.8.3.1.3 Wait Monitoring During Synchronous Read Access
              4. 17.4.4.8.3.1.4 Wait Monitoring During Synchronous Write Access
              5. 17.4.4.8.3.1.5 Wait With NAND Device
              6. 17.4.4.8.3.1.6 Idle Cycle Control Between Successive Accesses
                1. 17.4.4.8.3.1.6.1 Bus Turnaround (BUSTURNAROUND)
                2. 17.4.4.8.3.1.6.2 Idle Cycles Between Accesses to Same Chip-Select (CYCLE2CYCLESAMECSEN, CYCLE2CYCLEDELAY)
                3. 17.4.4.8.3.1.6.3 Idle Cycles Between Accesses to Different Chip-Select (CYCLE2CYCLEDIFFCSEN, CYCLE2CYCLEDELAY)
              7. 17.4.4.8.3.1.7 Slow Device Support (TIMEPARAGRANULARITY Parameter)
            2. 17.4.4.8.3.2 Reset
            3. 17.4.4.8.3.3 Byte Enable (nBE1/nBE0)
          4. 17.4.4.8.4 Error Handling
        9. 17.4.4.9  Timing Setting
          1. 17.4.4.9.1  Read Cycle Time and Write Cycle Time (RDCYCLETIME / WRCYCLETIME)
          2. 17.4.4.9.2  nCS: Chip-Select Signal Control Assertion/Deassertion Time (CSONTIME / CSRDOFFTIME / CSWROFFTIME / CSEXTRADELAY)
          3. 17.4.4.9.3  nADV/ALE: Address Valid/Address Latch Enable Signal Control Assertion/Deassertion Time (ADVONTIME / ADVRDOFFTIME / ADVWROFFTIME / ADVEXTRADELAY/ADVAADMUXONTIME/ADVAADMUXRDOFFTIME/ADVAADMUXWROFFTIME)
          4. 17.4.4.9.4  nOE/nRE: Output Enable/Read Enable Signal Control Assertion/Deassertion Time (OEONTIME / OEOFFTIME / OEEXTRADELAY / OEAADMUXONTIME / OEAADMUXOFFTIME)
          5. 17.4.4.9.5  nWE: Write Enable Signal Control Assertion/Deassertion Time (WEONTIME / WEOFFTIME / WEEXTRADELAY)
          6. 17.4.4.9.6  GPMC_CLK
          7. 17.4.4.9.7  GPMC_CLK and Control Signals Setup and Hold
          8. 17.4.4.9.8  Access Time (RDACCESSTIME / WRACCESSTIME)
            1. 17.4.4.9.8.1 Access Time on Read Access
            2. 17.4.4.9.8.2 Access Time on Write Access
          9. 17.4.4.9.9  Page Burst Access Time (PAGEBURSTACCESSTIME)
            1. 17.4.4.9.9.1 Page Burst Access Time on Read Access
            2. 17.4.4.9.9.2 Page Burst Access Time on Write Access
          10. 17.4.4.9.10 Bus Keeping Support
        10. 17.4.4.10 NOR Access Description
          1. 17.4.4.10.1 Asynchronous Access Description
            1. 17.4.4.10.1.1 Access on Address/Data Multiplexed Devices
              1. 17.4.4.10.1.1.1 Asynchronous Single-Read Operation on an Address/Data Multiplexed Device
              2. 17.4.4.10.1.1.2 Asynchronous Single-Write Operation on an Address/Data-Multiplexed Device
              3. 17.4.4.10.1.1.3 Asynchronous Multiple (Page) Write Operation on an Address/Data-Multiplexed Device
            2. 17.4.4.10.1.2 Access on Address/Address/Data-Multiplexed Devices
              1. 17.4.4.10.1.2.1 Asynchronous Single Read Operation on an AAD-Multiplexed Device
              2. 17.4.4.10.1.2.2 Asynchronous Single-Write Operation on an AAD-Multiplexed Device
              3. 17.4.4.10.1.2.3 Asynchronous Multiple (Page) Read Operation on an AAD-Multiplexed Device
          2. 17.4.4.10.2 Synchronous Access Description
            1. 17.4.4.10.2.1 Synchronous Single Read
            2. 17.4.4.10.2.2 Synchronous Multiple (Burst) Read (4-, 8-, 16-Word16 Burst With Wraparound Capability)
            3. 17.4.4.10.2.3 Synchronous Single Write
            4. 17.4.4.10.2.4 Synchronous Multiple (Burst) Write
          3. 17.4.4.10.3 Asynchronous and Synchronous Accesses in Nonmultiplexed Mode
            1. 17.4.4.10.3.1 Asynchronous Single-Read Operation on Nonmultiplexed Device
            2. 17.4.4.10.3.2 Asynchronous Single-Write Operation on Nonmultiplexed Device
            3. 17.4.4.10.3.3 Asynchronous Multiple (Page Mode) Read Operation on Nonmultiplexed Device
            4. 17.4.4.10.3.4 Synchronous Operations on a Nonmultiplexed Device
          4. 17.4.4.10.4 Page and Burst Support
          5. 17.4.4.10.5 System Burst vs External Device Burst Support
        11. 17.4.4.11 pSRAM Access Specificities
        12. 17.4.4.12 NAND Access Description
          1. 17.4.4.12.1 NAND Memory Device in Byte or 16-bit Word Stream Mode
            1. 17.4.4.12.1.1 Chip-Select Configuration for NAND Interfacing in Byte or Word Stream Mode
            2. 17.4.4.12.1.2 NAND Device Command and Address Phase Control
            3. 17.4.4.12.1.3 Command Latch Cycle
            4. 17.4.4.12.1.4 Address Latch Cycle
            5. 17.4.4.12.1.5 NAND Device Data Read and Write Phase Control in Stream Mode
            6. 17.4.4.12.1.6 NAND Device General Chip-Select Timing Control Requirement
            7. 17.4.4.12.1.7 Read and Write Access Size Adaptation
              1. 17.4.4.12.1.7.1 8-Bit-Wide NAND Device
              2. 17.4.4.12.1.7.2 16-Bit-Wide NAND Device
          2. 17.4.4.12.2 NAND Device-Ready Pin
            1. 17.4.4.12.2.1 Ready Pin Monitored by Software Polling
            2. 17.4.4.12.2.2 Ready Pin Monitored by Hardware Interrupt
          3. 17.4.4.12.3 ECC Calculator
            1. 17.4.4.12.3.1 Hamming Code
              1. 17.4.4.12.3.1.1 ECC Result Register and ECC Computation Accumulation Size
              2. 17.4.4.12.3.1.2 ECC Enabling
              3. 17.4.4.12.3.1.3 ECC Computation
              4. 17.4.4.12.3.1.4 ECC Comparison and Correction
              5. 17.4.4.12.3.1.5 ECC Calculation Based on 8-Bit Word
              6. 17.4.4.12.3.1.6 ECC Calculation Based on 16-Bit Word
            2. 17.4.4.12.3.2 BCH Code
              1. 17.4.4.12.3.2.1 Requirements
              2. 17.4.4.12.3.2.2 Memory Mapping of BCH Codeword
                1. 17.4.4.12.3.2.2.1 Memory Mapping of Data Message
                2. 17.4.4.12.3.2.2.2 Memory-Mapping of the ECC
                3. 17.4.4.12.3.2.2.3 Wrapping Modes
                  1. 4.4.12.3.2.2.3.1  Manual Mode (0x0)
                  2. 4.4.12.3.2.2.3.2  Mode 0x1
                  3. 4.4.12.3.2.2.3.3  Mode 0xA (10)
                  4. 4.4.12.3.2.2.3.4  Mode 0x2
                  5. 4.4.12.3.2.2.3.5  Mode 0x3
                  6. 4.4.12.3.2.2.3.6  Mode 0x7
                  7. 4.4.12.3.2.2.3.7  Mode 0x8
                  8. 4.4.12.3.2.2.3.8  Mode 0x4
                  9. 4.4.12.3.2.2.3.9  Mode 0x9
                  10. 4.4.12.3.2.2.3.10 Mode 0x5
                  11. 4.4.12.3.2.2.3.11 Mode 0xB (11)
                  12. 4.4.12.3.2.2.3.12 Mode 0x6
              3. 17.4.4.12.3.2.3 Supported NAND Page Mappings and ECC Schemes
                1. 17.4.4.12.3.2.3.1 Per-Sector Spare Mappings
                2. 17.4.4.12.3.2.3.2 Pooled Spare Mapping
                3. 17.4.4.12.3.2.3.3 Per-Sector Spare Mapping, with ECC Separated at the End of the Page
          4. 17.4.4.12.4 Prefetch and Write-Posting Engine
            1. 17.4.4.12.4.1 General Facts About the Engine Configuration
            2. 17.4.4.12.4.2 Prefetch Mode
            3. 17.4.4.12.4.3 FIFO Control in Prefetch Mode
            4. 17.4.4.12.4.4 Write-Posting Mode
            5. 17.4.4.12.4.5 FIFO Control in Write-Posting Mode
            6. 17.4.4.12.4.6 Optimizing NAND Access Using the Prefetch and Write-Posting Engine
            7. 17.4.4.12.4.7 Interleaved Accesses Between Prefetch and Write-Posting Engine and Other Chip-Selects
      5. 17.4.5 GPMC Basic Programming Model
        1. 17.4.5.1 GPMC High-Level Programming Model Overview
        2. 17.4.5.2 GPMC Initialization
        3. 17.4.5.3 GPMC Configuration in NOR Mode
        4. 17.4.5.4 GPMC Configuration in NAND Mode
        5. 17.4.5.5 Set Memory Access
        6. 17.4.5.6 GPMC Timing Parameters
          1. 17.4.5.6.1 GPMC Timing Parameters Formulas
            1. 17.4.5.6.1.1 NAND Flash Interface Timing Parameters Formulas
            2. 17.4.5.6.1.2 Synchronous NOR Flash Timing Parameters Formulas
            3. 17.4.5.6.1.3 Asynchronous NOR Flash Timing Parameters Formulas
      6. 17.4.6 GPMC Use Cases and Tips
        1. 17.4.6.1 How to Set GPMC Timing Parameters for Typical Accesses
          1. 17.4.6.1.1 External Memory Attached to the GPMC Module
          2. 17.4.6.1.2 Typical GPMC Setup
            1. 17.4.6.1.2.1 GPMC Configuration for Synchronous Burst Read Access
            2. 17.4.6.1.2.2 GPMC Configuration for Asynchronous Read Access
            3. 17.4.6.1.2.3 GPMC Configuration for Asynchronous Single Write Access
        2. 17.4.6.2 How to Choose a Suitable Memory to Use With the GPMC
          1. 17.4.6.2.1 Supported Memories or Devices
            1. 17.4.6.2.1.1 Memory Pin Multiplexing
            2. 17.4.6.2.1.2 NAND Interface Protocol
            3. 17.4.6.2.1.3 NOR Interface Protocol
            4. 17.4.6.2.1.4 Other Technologies
            5. 17.4.6.2.1.5 Supported Protocols
          2. 17.4.6.2.2 GPMC Features and Settings
      7. 17.4.7 GPMC Register Manual
        1. 17.4.7.1 GPMC Register Summary
        2. 17.4.7.2 GPMC Register Descriptions
    5. 17.5 Error Location Module
      1. 17.5.1 Error Location Module Overview
      2. 17.5.2 ELM Integration
      3. 17.5.3 ELM Functional Description
        1. 17.5.3.1 ELM Software Reset
        2. 17.5.3.2 ELM Power Management
        3. 17.5.3.3 ELM Interrupt Requests
        4. 17.5.3.4 Processing Initialization
        5. 17.5.3.5 Processing Sequence
        6. 17.5.3.6 Processing Completion
      4. 17.5.4 ELM Basic Programming Model
        1. 17.5.4.1 ELM Low-Level Programming Model
          1. 17.5.4.1.1 Processing Initialization
          2. 17.5.4.1.2 Read Results
          3. 17.5.4.1.3 3179
        2. 17.5.4.2 Use Case: ELM Used in Continuous Mode
        3. 17.5.4.3 Use Case: ELM Used in Page Mode
      5. 17.5.5 ELM Register Manual
        1. 17.5.5.1 ELM Instance Summary
        2. 17.5.5.2 ELM Registers
          1. 17.5.5.2.1 ELM Register Summary
          2. 17.5.5.2.2 ELM Register Description
    6. 17.6 On-Chip Memory (OCM) Subsystem
      1. 17.6.1 OCM Subsystem Overview
      2. 17.6.2 OCM Subsystem Integration
      3. 17.6.3 OCM Subsystem Functional Desctiption
        1. 17.6.3.1  Block Diagram
        2. 17.6.3.2  Resets
        3. 17.6.3.3  Clock Management
        4. 17.6.3.4  Interrupt Requests
        5. 17.6.3.5  OCM Subsystem Memory Regions
        6. 17.6.3.6  OCM Controller Modes Of Operation
        7. 17.6.3.7  ECC Associated FIFOs
        8. 17.6.3.8  ECC Counters And Corrected Bit Distribution Register
        9. 17.6.3.9  ECC Support
        10. 17.6.3.10 Circular Buffer (CBUF) Support
        11. 17.6.3.11 CBUF Mode Error Handling
          1. 17.6.3.11.1 VBUF Address Not Mapped to a CBUF Memory Space
          2. 17.6.3.11.2 VBUF Access Not Starting At The Base Address
          3. 17.6.3.11.3 Illegal Address Change Between Two Same Type Accesses
          4. 17.6.3.11.4 Illegal Frame SIze (Short Frame Detection)
          5. 17.6.3.11.5 CBUF Overflow
          6. 17.6.3.11.6 CBUF Underflow
        12. 17.6.3.12 Status Reporting
      4. 17.6.4 OCM Subsystem Register Manual
        1. 17.6.4.1 OCM Subsystem Instance Summary
        2. 17.6.4.2 OCM Subsystem Registers
          1. 17.6.4.2.1 OCM Subsystem Register Summary
          2. 17.6.4.2.2 OCM Subsystem Register Description
  20. 18DMA Controllers
    1. 18.1 System DMA
      1. 18.1.1 DMA_SYSTEM Module Overview
      2. 18.1.2 DMA_SYSTEM Controller Environment
      3. 18.1.3 DMA_SYSTEM Module Integration
        1. 18.1.3.1 DMA Requests to the DMA_SYSTEM Controller
        2. 18.1.3.2 Mapping of DMA Requests to DMA_CROSSBAR Inputs
      4. 18.1.4 DMA_SYSTEM Functional Description
        1. 18.1.4.1  DMA_SYSTEM Controller Power Management
        2. 18.1.4.2  DMA_SYSTEM Controller Interrupt Requests
          1. 18.1.4.2.1 Interrupt Generation
        3. 18.1.4.3  Logical Channel Transfer Overview
        4. 18.1.4.4  FIFO Queue Memory Pool
        5. 18.1.4.5  Addressing Modes
        6. 18.1.4.6  Packed Accesses
        7. 18.1.4.7  Burst Transactions
        8. 18.1.4.8  Endianism Conversion
        9. 18.1.4.9  Transfer Synchronization
          1. 18.1.4.9.1 Software Synchronization
          2. 18.1.4.9.2 Hardware Synchronization
        10. 18.1.4.10 Thread Budget Allocation
        11. 18.1.4.11 FIFO Budget Allocation
        12. 18.1.4.12 Chained Logical Channel Transfers
        13. 18.1.4.13 Reprogramming an Active Channel
        14. 18.1.4.14 Packet Synchronization
        15. 18.1.4.15 Graphics Acceleration Support
        16. 18.1.4.16 Supervisor Modes
        17. 18.1.4.17 Posted and Nonposted Writes
        18. 18.1.4.18 Disabling a Channel During Transfer
        19. 18.1.4.19 FIFO Draining Mechanism
        20. 18.1.4.20 Linked List
          1. 18.1.4.20.1 Overview
          2. 18.1.4.20.2 Link-List Transfer Profile
          3. 18.1.4.20.3 Descriptors
            1. 18.1.4.20.3.1 Type 1
            2. 18.1.4.20.3.2 Type 2
            3. 18.1.4.20.3.3 Type 3
          4. 18.1.4.20.4 Linked-List Control and Monitoring
            1. 18.1.4.20.4.1 Transfer Mode Setting
            2. 18.1.4.20.4.2 Starting a Linked List
            3. 18.1.4.20.4.3 Monitoring a Linked-List Progression
            4. 18.1.4.20.4.4 Interrupt During Linked-List Execution
            5. 18.1.4.20.4.5 Pause a Linked List
            6. 18.1.4.20.4.6 Stop a Linked List (Abort or Drain)
              1. 18.1.4.20.4.6.1 Drain
              2. 18.1.4.20.4.6.2 Abort
            7. 18.1.4.20.4.7 Status Bit Behavior
            8. 18.1.4.20.4.8 Linked-List Channel Linking
      5. 18.1.5 DMA_SYSTEM Basic Programming Model
        1. 18.1.5.1 Setup Configuration
        2. 18.1.5.2 Software-Triggered (Nonsynchronized) Transfer
        3. 18.1.5.3 Hardware-Synchronized Transfer
        4. 18.1.5.4 Synchronized Transfer Monitoring Using CDAC
        5. 18.1.5.5 Concurrent Software and Hardware Synchronization
        6. 18.1.5.6 Chained Transfer
        7. 18.1.5.7 90-Degree Clockwise Image Rotation
        8. 18.1.5.8 Graphic Operations
        9. 18.1.5.9 Linked-List Programming Guidelines
      6. 18.1.6 DMA_SYSTEM Register Manual
        1. 18.1.6.1 DMA_SYSTEM Instance Summary
        2. 18.1.6.2 DMA_SYSTEM Registers
          1. 18.1.6.2.1 DMA_SYSTEM Register Summary
          2. 18.1.6.2.2 DMA_SYSTEM Register Description
    2. 18.2 Enhanced DMA
      1. 18.2.1 EDMA Module Overview
        1. 18.2.1.1 EDMA Features
        2. 18.2.1.2 3280
        3. 18.2.1.3 EDMA Controllers Configuration
      2. 18.2.2 EDMA Controller Environment
      3. 18.2.3 EDMA Controller Integration
        1. 18.2.3.1 EDMA Requests to the EDMA Controller
      4. 18.2.4 EDMA Controller Functional Description
        1. 18.2.4.1  Block Diagram
          1. 18.2.4.1.1 Third-Party Channel Controller
          2. 18.2.4.1.2 Third-Party Transfer Controller
        2. 18.2.4.2  Types of EDMA controller Transfers
          1. 18.2.4.2.1 A-Synchronized Transfers
          2. 18.2.4.2.2 AB-Synchronized Transfers
        3. 18.2.4.3  Parameter RAM (PaRAM)
          1. 18.2.4.3.1 PaRAM
          2. 18.2.4.3.2 EDMA Channel PaRAM Set Entry Fields
            1. 18.2.4.3.2.1  Channel Options Parameter (OPT)
            2. 18.2.4.3.2.2  Channel Source Address (SRC)
            3. 18.2.4.3.2.3  Channel Destination Address (DST)
            4. 18.2.4.3.2.4  Count for 1st Dimension (ACNT)
            5. 18.2.4.3.2.5  Count for 2nd Dimension (BCNT)
            6. 18.2.4.3.2.6  Count for 3rd Dimension (CCNT)
            7. 18.2.4.3.2.7  BCNT Reload (BCNTRLD)
            8. 18.2.4.3.2.8  Source B Index (SBIDX)
            9. 18.2.4.3.2.9  Destination B Index (DBIDX)
            10. 18.2.4.3.2.10 Source C Index (SCIDX)
            11. 18.2.4.3.2.11 Destination C Index (DCIDX)
            12. 18.2.4.3.2.12 Link Address (LINK)
          3. 18.2.4.3.3 Null PaRAM Set
          4. 18.2.4.3.4 Dummy PaRAM Set
          5. 18.2.4.3.5 Dummy Versus Null Transfer Comparison
          6. 18.2.4.3.6 Parameter Set Updates
          7. 18.2.4.3.7 Linking Transfers
          8. 18.2.4.3.8 Constant Addressing Mode Transfers/Alignment Issues
          9. 18.2.4.3.9 Element Size
        4. 18.2.4.4  Initiating a DMA Transfer
          1. 18.2.4.4.1 DMA Channel
            1. 18.2.4.4.1.1 Event-Triggered Transfer Request
            2. 18.2.4.4.1.2 Manually-Triggered Transfer Request
            3. 18.2.4.4.1.3 Chain-Triggered Transfer Request
          2. 18.2.4.4.2 QDMA Channels
            1. 18.2.4.4.2.1 Auto-triggered and Link-Triggered Transfer Request
          3. 18.2.4.4.3 Comparison Between DMA and QDMA Channels
        5. 18.2.4.5  Completion of a DMA Transfer
          1. 18.2.4.5.1 Normal Completion
          2. 18.2.4.5.2 Early Completion
          3. 18.2.4.5.3 Dummy or Null Completion
        6. 18.2.4.6  Event, Channel, and PaRAM Mapping
          1. 18.2.4.6.1 DMA Channel to PaRAM Mapping
          2. 18.2.4.6.2 QDMA Channel to PaRAM Mapping
        7. 18.2.4.7  EDMA Channel Controller Regions
          1. 18.2.4.7.1 Region Overview
          2. 18.2.4.7.2 Channel Controller Regions
            1. 18.2.4.7.2.1 Resource Pool Division Across Two Regions
          3. 18.2.4.7.3 Region Interrupts
        8. 18.2.4.8  Chaining EDMA Channels
        9. 18.2.4.9  EDMA Interrupts
          1. 18.2.4.9.1 Transfer Completion Interrupts
            1. 18.2.4.9.1.1 Enabling Transfer Completion Interrupts
            2. 18.2.4.9.1.2 Clearing Transfer Completion Interrupts
          2. 18.2.4.9.2 EDMA Interrupt Servicing
          3. 18.2.4.9.3 Interrupt Servicing
          4. 18.2.4.9.4 3341
          5. 18.2.4.9.5 Interrupt Servicing
          6. 18.2.4.9.6 Interrupt Evaluation Operations
          7. 18.2.4.9.7 Error Interrupts
          8. 18.2.4.9.8 3345
        10. 18.2.4.10 Memory Protection
          1. 18.2.4.10.1 Active Memory Protection
          2. 18.2.4.10.2 Proxy Memory Protection
        11. 18.2.4.11 Event Queue(s)
          1. 18.2.4.11.1 DMA/QDMA Channel to Event Queue Mapping
          2. 18.2.4.11.2 Queue RAM Debug Visibility
          3. 18.2.4.11.3 Queue Resource Tracking
          4. 18.2.4.11.4 Performance Considerations
        12. 18.2.4.12 EDMA Transfer Controller (EDMA_TPTC)
          1. 18.2.4.12.1 Architecture Details
            1. 18.2.4.12.1.1 Command Fragmentation
            2. 18.2.4.12.1.2 TR Pipelining
            3. 18.2.4.12.1.3 Command Fragmentation (DBS = 64)
            4. 18.2.4.12.1.4 Performance Tuning
          2. 18.2.4.12.2 Memory Protection
          3. 18.2.4.12.3 Error Generation
          4. 18.2.4.12.4 Debug Features
            1. 18.2.4.12.4.1 Destination FIFO Register Pointer
          5. 18.2.4.12.5 EDMA_TPTC Configuration
        13. 18.2.4.13 Event Dataflow
        14. 18.2.4.14 EDMA controller Prioritization
          1. 18.2.4.14.1 Channel Priority
          2. 18.2.4.14.2 Trigger Source Priority
          3. 18.2.4.14.3 Dequeue Priority
        15. 18.2.4.15 EDMA Power, Reset and Clock Management
          1. 18.2.4.15.1 Clock and Power Management
          2. 18.2.4.15.2 Reset Considerations
        16. 18.2.4.16 Emulation Considerations
      5. 18.2.5 EDMA Transfer Examples
        1. 18.2.5.1 Block Move Example
        2. 18.2.5.2 Subframe Extraction Example
        3. 18.2.5.3 Data Sorting Example
        4. 18.2.5.4 Peripheral Servicing Example
          1. 18.2.5.4.1 Non-bursting Peripherals
          2. 18.2.5.4.2 Bursting Peripherals
          3. 18.2.5.4.3 Continuous Operation
            1. 18.2.5.4.3.1 Receive Channel
            2. 18.2.5.4.3.2 Transmit Channel
            3. 18.2.5.4.3.3 3384
          4. 18.2.5.4.4 Ping-Pong Buffering
            1. 18.2.5.4.4.1 Synchronization with the CPU
          5. 18.2.5.4.5 Transfer Chaining Examples
            1. 18.2.5.4.5.1 Servicing Input/Output FIFOs with a Single Event
            2. 18.2.5.4.5.2 Breaking Up Large Transfers with Intermediate Chaining
        5. 18.2.5.5 Setting Up an EDMA Transfer
          1. 18.2.5.5.1 3391
      6. 18.2.6 EDMA Debug Checklist and Programming Tips
        1. 18.2.6.1 EDMA Debug Checklist
        2. 18.2.6.2 EDMA Programming Tips
      7. 18.2.7 EDMA Register Manual
        1. 18.2.7.1 EDMA Instance Summary
        2. 18.2.7.2 EDMA Registers
          1. 18.2.7.2.1 EDMA Register Summary
          2. 18.2.7.2.2 EDMA Register Description
            1. 18.2.7.2.2.1 EDMA_TPCC Register Description
            2. 18.2.7.2.2.2 EDMA_TPTC0 and EDMA_TPTC1 Register Description
  21. 19Interrupt Controllers
    1. 19.1 Interrupt Controllers Overview
    2. 19.2 Interrupt Controllers Environment
    3. 19.3 Interrupt Controllers Integration
      1. 19.3.1 Interrupt Requests to MPU_INTC
      2. 19.3.2 Interrupt Requests to DSP1_INTC
      3. 19.3.3 Interrupt Requests to DSP2_INTC
      4. 19.3.4 Interrupt Requests to IPU1_Cx_INTC
      5. 19.3.5 Interrupt Requests to IPU2_Cx_INTC
      6. 19.3.6 Interrupt Requests to EVE1_INTC1
      7. 19.3.7 Interrupt Requests to EVE2_INTC1
      8. 19.3.8 Mapping of Device Interrupts to IRQ_CROSSBAR Inputs
    4. 19.4 Interrupt Controllers Functional Description
  22. 20Control Module
    1. 20.1 Control Module Overview
    2. 20.2 Control Module Environment
    3. 20.3 Control Module Integration
    4. 20.4 Control Module Functional Description
      1. 20.4.1 Control Module Clock Configuration
      2. 20.4.2 Control Module Resets
      3. 20.4.3 Control Module Power Management
        1. 20.4.3.1 Power Management Protocols
      4. 20.4.4 Hardware Requests
      5. 20.4.5 Control Module Initialization
      6. 20.4.6 Functional Description Of The Various Register Types In CTRL_MODULE_CORE Submodule
        1. 20.4.6.1  Pad Configuration
          1. 20.4.6.1.1 Pad Configuration Registers
            1. 20.4.6.1.1.1 Permanent PU/PD disabling
          2. 20.4.6.1.2 Pull Selection
          3. 20.4.6.1.3 Pad multiplexing
          4. 20.4.6.1.4 IOSETs
          5. 20.4.6.1.5 Virtual IO Timing Modes
          6. 20.4.6.1.6 Manual IO Timing Modes
          7. 20.4.6.1.7 Isolation Requirements
          8. 20.4.6.1.8 IO Delay Recalibration
        2. 20.4.6.2  Thermal Management Related Registers
          1. 20.4.6.2.1 Temperature Sensors Control Registers
          2. 20.4.6.2.2 Registers For The Thermal Alert Comparators
          3. 20.4.6.2.3 Thermal Shutdown Comparators
          4. 20.4.6.2.4 Temperature Timestamp Registers
          5. 20.4.6.2.5 Other Thermal Management Related Registers
          6. 20.4.6.2.6 Summary of the Thermal Management Related Registers
          7. 20.4.6.2.7 ADC Values Versus Temperature
        3. 20.4.6.3  PBIAS Cell And MMC1 I/O Cells Control Registers
        4. 20.4.6.4  IRQ_CROSSBAR Module Functional Description
        5. 20.4.6.5  DMA_CROSSBAR Module Functional Description
        6. 20.4.6.6  SDRAM Initiator Priority Registers
        7. 20.4.6.7  L3_MAIN Initiator Priority Registers
        8. 20.4.6.8  Memory Region Lock Registers
        9. 20.4.6.9  NMI Mapping To Respective Cores
        10. 20.4.6.10 Software Controls for the DDR2/DDR3 I/O Cells
        11. 20.4.6.11 Reference Voltage for the Device DDR2/DDR3 Receivers
        12. 20.4.6.12 AVS Class 0 Associated Registers
        13. 20.4.6.13 ABB Associated Registers
        14. 20.4.6.14 Registers For Other Miscellaneous Functions
          1. 20.4.6.14.1 System Boot Status Settings
          2. 20.4.6.14.2 Force MPU Write Nonposted Transactions
          3. 20.4.6.14.3 Firewall Error Status Registers
          4. 20.4.6.14.4 Settings Related To Different Peripheral Modules
      7. 20.4.7 Functional Description Of The Various Register Types In CTRL_MODULE_WKUP Submodule
        1. 20.4.7.1 Registers For Basic EMIF Configuration
    5. 20.5 Control Module Register Manual
    6. 20.6 IODELAYCONFIG Module Integration
    7. 20.7 IODELAYCONFIG Module Register Manual
  23. 21Mailbox
    1. 21.1 Mailbox Overview
    2. 21.2 Mailbox Integration
      1. 21.2.1 System MAILBOX Integration
      2. 21.2.2 IVA Mailbox Integration
      3. 21.2.3 EVE Mailbox Integration
    3. 21.3 Mailbox Functional Description
      1. 21.3.1 Mailbox Block Diagram
        1. 21.3.1.1 3474
      2. 21.3.2 Mailbox Software Reset
      3. 21.3.3 Mailbox Power Management
      4. 21.3.4 Mailbox Interrupt Requests
      5. 21.3.5 Mailbox Assignment
        1. 21.3.5.1 Description
      6. 21.3.6 Sending and Receiving Messages
        1. 21.3.6.1 Description
      7. 21.3.7 16-Bit Register Access
        1. 21.3.7.1 Description
      8. 21.3.8 Example of Communication
    4. 21.4 Mailbox Programming Guide
      1. 21.4.1 Mailbox Low-level Programming Models
        1. 21.4.1.1 Global Initialization
          1. 21.4.1.1.1 Surrounding Modules Global Initialization
          2. 21.4.1.1.2 Mailbox Global Initialization
            1. 21.4.1.1.2.1 Main Sequence - Mailbox Global Initialization
        2. 21.4.1.2 Mailbox Operational Modes Configuration
          1. 21.4.1.2.1 Mailbox Processing modes
            1. 21.4.1.2.1.1 Main Sequence - Sending a Message (Polling Method)
            2. 21.4.1.2.1.2 Main Sequence - Sending a Message (Interrupt Method)
            3. 21.4.1.2.1.3 Main Sequence - Receiving a Message (Polling Method)
            4. 21.4.1.2.1.4 Main Sequence - Receiving a Message (Interrupt Method)
        3. 21.4.1.3 Mailbox Events Servicing
          1. 21.4.1.3.1 Events Servicing in Sending Mode
          2. 21.4.1.3.2 Events Servicing in Receiving Mode
    5. 21.5 Mailbox Register Manual
      1. 21.5.1 Mailbox Instance Summary
      2. 21.5.2 Mailbox Registers
        1. 21.5.2.1 Mailbox Register Summary
        2. 21.5.2.2 Mailbox Register Description
  24. 22Memory Management Units
    1. 22.1 MMU Overview
    2. 22.2 MMU Integration
    3. 22.3 MMU Functional Description
      1. 22.3.1 MMU Block Diagram
        1. 22.3.1.1 MMU Address Translation Process
        2. 22.3.1.2 Translation Tables
          1. 22.3.1.2.1 Translation Table Hierarchy
          2. 22.3.1.2.2 First-Level Translation Table
            1. 22.3.1.2.2.1 First-Level Descriptor Format
            2. 22.3.1.2.2.2 First-Level Page Descriptor Format
            3. 22.3.1.2.2.3 First-Level Section Descriptor Format
            4. 22.3.1.2.2.4 Section Translation Summary
            5. 22.3.1.2.2.5 Supersection Translation Summary
          3. 22.3.1.2.3 Two-Level Translation
            1. 22.3.1.2.3.1 Second-Level Descriptor Format
            2. 22.3.1.2.3.2 Small Page Translation Summary
            3. 22.3.1.2.3.3 Large Page Translation Summary
        3. 22.3.1.3 Translation Lookaside Buffer
          1. 22.3.1.3.1 TLB Entry Format
        4. 22.3.1.4 No Translation (Bypass) Regions
      2. 22.3.2 MMU Software Reset
      3. 22.3.3 MMU Power Management
      4. 22.3.4 MMU Interrupt Requests
      5. 22.3.5 MMU Error Handling
    4. 22.4 MMU Low-level Programming Models
      1. 22.4.1 Global Initialization
        1. 22.4.1.1 Surrounding Modules Global Initialization
        2. 22.4.1.2 MMU Global Initialization
          1. 22.4.1.2.1 Main Sequence - MMU Global Initialization
          2. 22.4.1.2.2 Subsequence - Configure a TLB entry
        3. 22.4.1.3 Operational Modes Configuration
          1. 22.4.1.3.1 Main Sequence - Writing TLB Entries Statically
          2. 22.4.1.3.2 Main Sequence - Protecting TLB Entries
          3. 22.4.1.3.3 Main Sequence - Deleting TLB Entries
          4. 22.4.1.3.4 Main Sequence - Read TLB Entries
    5. 22.5 MMU Register Manual
      1. 22.5.1 MMU Instance Summary
      2. 22.5.2 MMU Registers
        1. 22.5.2.1 MMU Register Summary
        2. 22.5.2.2 MMU Register Description
  25. 23Spinlock
    1. 23.1 Spinlock Overview
    2. 23.2 Spinlock Integration
    3. 23.3 Spinlock Functional Description
      1. 23.3.1 Spinlock Software Reset
      2. 23.3.2 Spinlock Power Management
      3. 23.3.3 About Spinlocks
      4. 23.3.4 Spinlock Functional Operation
    4. 23.4 Spinlock Programming Guide
      1. 23.4.1 Spinlock Low-level Programming Models
        1. 23.4.1.1 Surrounding Modules Global Initialization
        2. 23.4.1.2 Basic Spinlock Operations
          1. 23.4.1.2.1 Spinlocks Clearing After a System Bug Recovery
          2. 23.4.1.2.2 Take and Release Spinlock
    5. 23.5 Spinlock Register Manual
      1. 23.5.1 Spinlock Instance Summary
      2. 23.5.2 Spinlock Registers
        1. 23.5.2.1 Spinlock Register Summary
        2. 23.5.2.2 Spinlock Register Description
  26. 24Timers
    1. 24.1 Timers Overview
    2. 24.2 General-Purpose Timers
      1. 24.2.1 General-Purpose Timers Overview
        1. 24.2.1.1 GP Timer Features
      2. 24.2.2 GP Timer Environment
        1. 24.2.2.1 GP Timer External System Interface
      3. 24.2.3 GP Timer Integration
      4. 24.2.4 GP Timer Functional Description
        1. 24.2.4.1  GP Timer Block Diagram
        2. 24.2.4.2  TIMER1, TIMER2 and TIMER10 Power Management
          1. 24.2.4.2.1 Wake-Up Capability
        3. 24.2.4.3  Power Management of Other GP Timers
          1. 24.2.4.3.1 Wake-Up Capability
        4. 24.2.4.4  Software Reset
        5. 24.2.4.5  GP Timer Interrupts
        6. 24.2.4.6  Timer Mode Functionality
          1. 24.2.4.6.1 1-ms Tick Generation (Only TIMER1, TIMER2 and TIMER10)
        7. 24.2.4.7  Capture Mode Functionality
        8. 24.2.4.8  Compare Mode Functionality
        9. 24.2.4.9  Prescaler Functionality
        10. 24.2.4.10 Pulse-Width Modulation
        11. 24.2.4.11 Timer Counting Rate
        12. 24.2.4.12 Timer Under Emulation
        13. 24.2.4.13 Accessing GP Timer Registers
          1. 24.2.4.13.1 Writing to Timer Registers
            1. 24.2.4.13.1.1 Write Posting Synchronization Mode
            2. 24.2.4.13.1.2 Write Nonposting Synchronization Mode
          2. 24.2.4.13.2 Reading From Timer Counter Registers
            1. 24.2.4.13.2.1 Read Posted
            2. 24.2.4.13.2.2 Read Non-Posted
        14. 24.2.4.14 Posted Mode Selection
      5. 24.2.5 GP Timer Low-Level Programming Models
        1. 24.2.5.1 Global Initialization
          1. 24.2.5.1.1 Global Initialization of Surrounding Modules
          2. 24.2.5.1.2 GP Timer Module Global Initialization
            1. 24.2.5.1.2.1 Main Sequence – GP Timer Module Global Initialization
        2. 24.2.5.2 Operational Mode Configuration
          1. 24.2.5.2.1 GP Timer Mode
            1. 24.2.5.2.1.1 Main Sequence – GP Timer Mode Configuration
          2. 24.2.5.2.2 GP Timer Compare Mode
            1. 24.2.5.2.2.1 Main Sequence – GP Timer Compare Mode Configuration
          3. 24.2.5.2.3 GP Timer Capture Mode
            1. 24.2.5.2.3.1 Main Sequence – GP Timer Capture Mode Configuration
            2. 24.2.5.2.3.2 Subsequence – Initialize Capture Mode
            3. 24.2.5.2.3.3 Subsequence – Detect Event
          4. 24.2.5.2.4 GP Timer PWM Mode
            1. 24.2.5.2.4.1 Main Sequence – GP Timer PWM Mode Configuration
      6. 24.2.6 GP Timer Register Manual
        1. 24.2.6.1 GP Timer Instance Summary
        2. 24.2.6.2 GP Timer Registers
          1. 24.2.6.2.1 GP Timer Register Summary
          2. 24.2.6.2.2 GP Timer Register Description
          3. 24.2.6.2.3 TIMER1, TIMER2, and TIMER10 Register Description
    3. 24.3 32-kHz Synchronized Timer (COUNTER_32K)
      1. 24.3.1 32-kHz Synchronized Timer Overview
        1. 24.3.1.1 32-kHz Synchronized Timer Features
      2. 24.3.2 32-kHz Synchronized Timer Integration
      3. 24.3.3 32-kHz Synchronized Timer Functional Description
        1. 24.3.3.1 Reading the 32-kHz Synchronized Timer
      4. 24.3.4 COUNTER_32K Timer Register Manual
        1. 24.3.4.1 COUNTER_32K Timer Register Mapping Summary
        2. 24.3.4.2 COUNTER_32K Timer Register Description
    4. 24.4 Watchdog Timer
      1. 24.4.1 Watchdog Timer Overview
        1. 24.4.1.1 Watchdog Timer Features
      2. 24.4.2 Watchdog Timer Integration
      3. 24.4.3 Watchdog Timer Functional Description
        1. 24.4.3.1  Power Management
          1. 24.4.3.1.1 Wake-Up Capability
        2. 24.4.3.2  Interrupts
        3. 24.4.3.3  General Watchdog Timer Operation
        4. 24.4.3.4  Reset Context
        5. 24.4.3.5  Overflow/Reset Generation
        6. 24.4.3.6  Prescaler Value/Timer Reset Frequency
        7. 24.4.3.7  Triggering a Timer Reload
        8. 24.4.3.8  Start/Stop Sequence for Watchdog Timer (Using the WSPR Register)
        9. 24.4.3.9  Modifying Timer Count/Load Values and Prescaler Setting
        10. 24.4.3.10 Watchdog Counter Register Access Restriction (WCRR)
        11. 24.4.3.11 Watchdog Timer Interrupt Generation
        12. 24.4.3.12 Watchdog Timer Under Emulation
        13. 24.4.3.13 Accessing Watchdog Timer Registers
      4. 24.4.4 Watchdog Timer Low-Level Programming Model
        1. 24.4.4.1 Global Initialization
          1. 24.4.4.1.1 Surrounding Modules Global Initialization
          2. 24.4.4.1.2 Watchdog Timer Module Global Initialization
            1. 24.4.4.1.2.1 Main Sequence – Watchdog Timer Module Global Initialization
        2. 24.4.4.2 Operational Mode Configuration
          1. 24.4.4.2.1 Watchdog Timer Basic Configuration
            1. 24.4.4.2.1.1 Main Sequence – Watchdog Timer Basic Configuration
            2. 24.4.4.2.1.2 Subsequence – Disable the Watchdog Timer
            3. 24.4.4.2.1.3 Subsequence – Enable the Watchdog Timer
      5. 24.4.5 Watchdog Timer Register Manual
        1. 24.4.5.1 Watchdog Timer Instance Summary
        2. 24.4.5.2 Watchdog Timer Registers
          1. 24.4.5.2.1 Watchdog Timer Register Summary
          2. 24.4.5.2.2 3661
          3. 24.4.5.2.3 Watchdog Timer Register Description
  27. 25Real-Time Clock (RTC)
    1. 25.1 RTC Overview
      1. 25.1.1 RTC Features
    2. 25.2 RTC Environment
      1. 25.2.1 RTC External Interface
    3. 25.3 RTC Integration
    4. 25.4 RTC Functional Description
      1. 25.4.1 Clock Source
      2. 25.4.2 Interrupt Support
        1. 25.4.2.1 CPU Interrupts
        2. 25.4.2.2 Interrupt Description
          1. 25.4.2.2.1 Timer Interrupt (timer_intr)
          2. 25.4.2.2.2 Alarm Interrupt (alarm_intr)
      3. 25.4.3 RTC Programming/Usage Guide
        1. 25.4.3.1 Time/Calendar Data Format
        2. 25.4.3.2 Register Access
        3. 25.4.3.3 Register Spurious Write Protection
        4. 25.4.3.4 Reading the Timer/Calendar (TC) Registers
          1. 25.4.3.4.1 Rounding Seconds
        5. 25.4.3.5 Modifying the TC Registers
          1. 25.4.3.5.1 General Registers
        6. 25.4.3.6 Crystal Compensation
      4. 25.4.4 Scratch Registers
      5. 25.4.5 Debouncing
      6. 25.4.6 Power Management
        1. 25.4.6.1 Device-Level Power Management
        2. 25.4.6.2 Subsystem-Level Power Management — PMIC Mode
    5. 25.5 RTC Low-Level Programming Guide
      1. 25.5.1 Global Initialization
        1. 25.5.1.1 Surrounding Modules Global Initialization
        2. 25.5.1.2 RTC Module Global Initialization
          1. 25.5.1.2.1 Main Sequence – RTC Module Global Initialization
    6. 25.6 RTC Register Manual
      1. 25.6.1 RTC Instance Summary
      2. 25.6.2 RTC_SS Registers
        1. 25.6.2.1 RTC_SS Register Summary
        2. 25.6.2.2 RTC_SS Register Description
  28. 26Serial Communication Interfaces
    1. 26.1  Multimaster High-Speed I2C Controller
      1. 26.1.1 HS I2C Overview
      2. 26.1.2 HS I2C Environment
        1. 26.1.2.1 HS I2C Typical Application
          1. 26.1.2.1.1 HS I2C Pins for Typical Connections in I2C Mode
          2. 26.1.2.1.2 HS I2C Interface Typical Connections
        2. 26.1.2.2 HS I2C Typical Connection Protocol and Data Format
          1. 26.1.2.2.1  HS I2C Serial Data Format
          2. 26.1.2.2.2  HS I2C Data Validity
          3. 26.1.2.2.3  HS I2C Start and Stop Conditions
          4. 26.1.2.2.4  HS I2C Addressing
            1. 26.1.2.2.4.1 Data Transfer Formats in F/S Mode
            2. 26.1.2.2.4.2 Data Transfer Format in HS Mode
          5. 26.1.2.2.5  HS I2C Master Transmitter
          6. 26.1.2.2.6  HS I2C Master Receiver
          7. 26.1.2.2.7  HS I2C Slave Transmitter
          8. 26.1.2.2.8  HS I2C Slave Receiver
          9. 26.1.2.2.9  HS I2C Bus Arbitration
          10. 26.1.2.2.10 HS I2C Clock Generation and Synchronization
      3. 26.1.3 HS I2C Integration
      4. 26.1.4 HS I2C Functional Description
        1. 26.1.4.1  HS I2C Block Diagram
        2. 26.1.4.2  HS I2C Clocks
          1. 26.1.4.2.1 HS I2C Clocking
          2. 26.1.4.2.2 HS I2C Automatic Blocking of the I2C Clock Feature
        3. 26.1.4.3  HS I2C Software Reset
        4. 26.1.4.4  HS I2C Power Management
        5. 26.1.4.5  HS I2C Interrupt Requests
        6. 26.1.4.6  HS I2C DMA Requests
        7. 26.1.4.7  HS I2C Programmable Multislave Channel Feature
        8. 26.1.4.8  HS I2C FIFO Management
          1. 26.1.4.8.1 HS I2C FIFO Interrupt Mode
          2. 26.1.4.8.2 HS I2C FIFO Polling Mode
          3. 26.1.4.8.3 HS I2C FIFO DMA Mode
          4. 26.1.4.8.4 HS I2C Draining Feature
        9. 26.1.4.9  HS I2C Noise Filter
        10. 26.1.4.10 HS I2C System Test Mode
      5. 26.1.5 HS I2C Programming Guide
        1. 26.1.5.1 HS I2C Low-Level Programming Models
          1. 26.1.5.1.1 HS I2C Programming Model
            1. 26.1.5.1.1.1 Main Program
              1. 26.1.5.1.1.1.1 Configure the Module Before Enabling the I2C Controller
              2. 26.1.5.1.1.1.2 Initialize the I2C Controller
              3. 26.1.5.1.1.1.3 Configure Slave Address and the Data Control Register
              4. 26.1.5.1.1.1.4 Initiate a Transfer
              5. 26.1.5.1.1.1.5 Receive Data
              6. 26.1.5.1.1.1.6 Transmit Data
            2. 26.1.5.1.1.2 Interrupt Subroutine Sequence
            3. 26.1.5.1.1.3 Programming Flow-Diagrams
      6. 26.1.6 HS I2C Register Manual
        1. 26.1.6.1 HS I2C Instance Summary
        2. 26.1.6.2 HS I2C Registers
          1. 26.1.6.2.1 HS I2C Register Summary
          2. 26.1.6.2.2 HS I2C Register Description
    2. 26.2  HDQ/1-Wire
      1. 26.2.1 HDQ1W Overview
      2. 26.2.2 HDQ1W Environment
        1. 26.2.2.1 HDQ1W Functional Modes
        2. 26.2.2.2 HDQ and 1-Wire (SDQ) Protocols
          1. 26.2.2.2.1 HDQ Protocol Initialization (Default)
          2. 26.2.2.2.2 1-Wire (SDQ) Protocol Initialization
          3. 26.2.2.2.3 Communication Sequence (HDQ and 1-Wire Protocols)
      3. 26.2.3 HDQ1W Integration
      4. 26.2.4 HDQ1W Functional Description
        1. 26.2.4.1 HDQ1W Block Diagram
        2. 26.2.4.2 HDQ1W Clocking Configuration
          1. 26.2.4.2.1 HDQ1W Clocks
        3. 26.2.4.3 HDQ1W Hardware and Software Reset
        4. 26.2.4.4 HDQ1W Power Management
          1. 26.2.4.4.1 Auto-Idle Mode
          2. 26.2.4.4.2 Power-Down Mode
          3. 26.2.4.4.3 3772
        5. 26.2.4.5 HDQ Interrupt Requests
        6. 26.2.4.6 HDQ Mode (Default)
          1. 26.2.4.6.1 HDQ Mode Features
          2. 26.2.4.6.2 Description
          3. 26.2.4.6.3 Single-Bit Mode
          4. 26.2.4.6.4 Interrupt Conditions
        7. 26.2.4.7 1-Wire Mode
          1. 26.2.4.7.1 1-Wire Mode Features
          2. 26.2.4.7.2 Description
          3. 26.2.4.7.3 1-Wire Single-Bit Mode Operation
          4. 26.2.4.7.4 Interrupt Conditions
          5. 26.2.4.7.5 Status Flags
        8. 26.2.4.8 BITFSM Delay
      5. 26.2.5 HDQ1W Low-Level Programming Model
        1. 26.2.5.1 Global Initialization
          1. 26.2.5.1.1 Surrounding Modules Global Initialization
          2. 26.2.5.1.2 HDQ1W Module Global Initialization
        2. 26.2.5.2 HDQ Operational Modes Configuration
          1. 26.2.5.2.1 Main Sequence - HDQ Write Operation Mode
          2. 26.2.5.2.2 Main Sequence - HDQ Read Operation Mode
            1. 26.2.5.2.2.1 Sub-sequence - Initialize HDQ Slave
        3. 26.2.5.3 1-Wire Operational Modes Configuration
          1. 26.2.5.3.1 Main Sequence - 1-Wire Write Operation Mode
          2. 26.2.5.3.2 Main Sequence - 1-Wire Read Operation Mode
          3. 26.2.5.3.3 Sub-sequence - Initialize 1-Wire Slave
      6. 26.2.6 HDQ1W Register Manual
        1. 26.2.6.1 HDQ1W Instance Summary
        2. 26.2.6.2 HDQ1W Registers
          1. 26.2.6.2.1 HDQ1W Register Summary
          2. 26.2.6.2.2 HDQ1W Register Description
    3. 26.3  UART/IrDA/CIR
      1. 26.3.1 UART/IrDA/CIR Overview
        1. 26.3.1.1 UART Features
        2. 26.3.1.2 IrDA Features
        3. 26.3.1.3 CIR Features
      2. 26.3.2 UART/IrDA/CIR Environment
        1. 26.3.2.1 UART Interface
          1. 26.3.2.1.1 System Using UART Communication With Hardware Handshake
          2. 26.3.2.1.2 UART Interface Description
          3. 26.3.2.1.3 UART Protocol and Data Format
        2. 26.3.2.2 IrDA Functional Interfaces
          1. 26.3.2.2.1 System Using IrDA Communication Protocol
          2. 26.3.2.2.2 IrDA Interface Description
          3. 26.3.2.2.3 IrDA Protocol and Data Format
            1. 26.3.2.2.3.1 SIR Mode
              1. 26.3.2.2.3.1.1 Frame Format
              2. 26.3.2.2.3.1.2 Asynchronous Transparency
              3. 26.3.2.2.3.1.3 Abort Sequence
              4. 26.3.2.2.3.1.4 Pulse Shaping
              5. 26.3.2.2.3.1.5 Encoder
              6. 26.3.2.2.3.1.6 Decoder
              7. 26.3.2.2.3.1.7 IR Address Checking
            2. 26.3.2.2.3.2 SIR Free-Format Mode
            3. 26.3.2.2.3.3 MIR Mode
              1. 26.3.2.2.3.3.1 MIR Encoder/Decoder
              2. 26.3.2.2.3.3.2 SIP Generation
            4. 26.3.2.2.3.4 FIR Mode
        3. 26.3.2.3 CIR Functional Interfaces
          1. 26.3.2.3.1 System Using CIR Communication Protocol With Remote Control
          2. 26.3.2.3.2 CIR Interface Description
          3. 26.3.2.3.3 CIR Protocol and Data Format
            1. 26.3.2.3.3.1 Carrier Modulation
            2. 26.3.2.3.3.2 Pulse Duty Cycle
            3. 26.3.2.3.3.3 Consumer IR Encoding/Decoding
      3. 26.3.3 UART/IrDA/CIR Integration
        1. 26.3.3.1 3838
      4. 26.3.4 UART/IrDA/CIR Functional Description
        1. 26.3.4.1 Block Diagram
        2. 26.3.4.2 Clock Configuration
        3. 26.3.4.3 Software Reset
        4. 26.3.4.4 Power Management
          1. 26.3.4.4.1 UART Mode Power Management
            1. 26.3.4.4.1.1 Module Power Saving
            2. 26.3.4.4.1.2 System Power Saving
          2. 26.3.4.4.2 IrDA Mode Power Management (UART3 Only)
            1. 26.3.4.4.2.1 Module Power Saving
            2. 26.3.4.4.2.2 System Power Saving
          3. 26.3.4.4.3 CIR Mode Power Management (UART3 Only)
            1. 26.3.4.4.3.1 Module Power Saving
            2. 26.3.4.4.3.2 System Power Saving
          4. 26.3.4.4.4 Local Power Management
        5. 26.3.4.5 Interrupt Requests
          1. 26.3.4.5.1 UART Mode Interrupt Management
            1. 26.3.4.5.1.1 UART Interrupts
            2. 26.3.4.5.1.2 Wake-Up Interrupt
          2. 26.3.4.5.2 IrDA Mode Interrupt Management
            1. 26.3.4.5.2.1 IrDA Interrupts
            2. 26.3.4.5.2.2 Wake-Up Interrupts
          3. 26.3.4.5.3 CIR Mode Interrupt Management
            1. 26.3.4.5.3.1 CIR Interrupts
            2. 26.3.4.5.3.2 Wake-Up Interrupts
        6. 26.3.4.6 FIFO Management
          1. 26.3.4.6.1 FIFO Trigger
            1. 26.3.4.6.1.1 Transmit FIFO Trigger
            2. 26.3.4.6.1.2 Receive FIFO Trigger
          2. 26.3.4.6.2 FIFO Interrupt Mode
          3. 26.3.4.6.3 FIFO Polled Mode Operation
          4. 26.3.4.6.4 FIFO DMA Mode Operation
            1. 26.3.4.6.4.1 DMA sequence to disable TX DMA
            2. 26.3.4.6.4.2 DMA Transfers (DMA Mode 1, 2, or 3)
            3. 26.3.4.6.4.3 DMA Transmission
            4. 26.3.4.6.4.4 DMA Reception
        7. 26.3.4.7 Mode Selection
          1. 26.3.4.7.1 Register Access Modes
            1. 26.3.4.7.1.1 Operational Mode and Configuration Modes
            2. 26.3.4.7.1.2 Register Access Submode
            3. 26.3.4.7.1.3 Registers Available for the Register Access Modes
          2. 26.3.4.7.2 UART/IrDA (SIR, MIR, FIR)/CIR Mode Selection
            1. 26.3.4.7.2.1 Registers Available for the UART Function
            2. 26.3.4.7.2.2 Registers Available for the IrDA Function (UART3 Only)
            3. 26.3.4.7.2.3 Registers Available for the CIR Function (UART3 Only)
        8. 26.3.4.8 Protocol Formatting
          1. 26.3.4.8.1 UART Mode
            1. 26.3.4.8.1.1 UART Clock Generation: Baud Rate Generation
            2. 26.3.4.8.1.2 Choosing the Appropriate Divisor Value
            3. 26.3.4.8.1.3 UART Data Formatting
              1. 26.3.4.8.1.3.1 Frame Formatting
              2. 26.3.4.8.1.3.2 Hardware Flow Control
              3. 26.3.4.8.1.3.3 Software Flow Control
                1. 26.3.4.8.1.3.3.1 Receive (RX)
                2. 26.3.4.8.1.3.3.2 Transmit (TX)
              4. 26.3.4.8.1.3.4 Autobauding Modes
              5. 26.3.4.8.1.3.5 Error Detection
              6. 26.3.4.8.1.3.6 Overrun During Receive
              7. 26.3.4.8.1.3.7 Time-Out and Break Conditions
                1. 26.3.4.8.1.3.7.1 Time-Out Counter
                2. 26.3.4.8.1.3.7.2 Break Condition
          2. 26.3.4.8.2 IrDA Mode (UART3 Only)
            1. 26.3.4.8.2.1 IrDA Clock Generation: Baud Generator
            2. 26.3.4.8.2.2 Choosing the Appropriate Divisor Value
            3. 26.3.4.8.2.3 IrDA Data Formatting
              1. 26.3.4.8.2.3.1 IR RX Polarity Control
              2. 26.3.4.8.2.3.2 IrDA Reception Control
              3. 26.3.4.8.2.3.3 IR Address Checking
              4. 26.3.4.8.2.3.4 Frame Closing
              5. 26.3.4.8.2.3.5 Store and Controlled Transmission
              6. 26.3.4.8.2.3.6 Error Detection
              7. 26.3.4.8.2.3.7 Underrun During Transmission
              8. 26.3.4.8.2.3.8 Overrun During Receive
              9. 26.3.4.8.2.3.9 Status FIFO
            4. 26.3.4.8.2.4 SIR Mode Data Formatting
              1. 26.3.4.8.2.4.1 Abort Sequence
              2. 26.3.4.8.2.4.2 Pulse Shaping
              3. 26.3.4.8.2.4.3 SIR Free Format Programming
            5. 26.3.4.8.2.5 MIR and FIR Mode Data Formatting
          3. 26.3.4.8.3 CIR Mode (UART3 Only)
            1. 26.3.4.8.3.1 CIR Mode Clock Generation
            2. 26.3.4.8.3.2 CIR Data Formatting
              1. 26.3.4.8.3.2.1 IR RX Polarity Control
              2. 26.3.4.8.3.2.2 CIR Transmission
      5. 26.3.5 UART/IrDA/CIR Basic Programming Model
        1. 26.3.5.1 Global Initialization
          1. 26.3.5.1.1 Surrounding Modules Global Initialization
          2. 26.3.5.1.2 UART/IrDA/CIR Module Global Initialization
        2. 26.3.5.2 Mode selection
        3. 26.3.5.3 Submode selection
        4. 26.3.5.4 Load FIFO trigger and DMA mode settings
          1. 26.3.5.4.1 DMA mode Settings
          2. 26.3.5.4.2 FIFO Trigger Settings
        5. 26.3.5.5 Protocol, Baud rate and interrupt settings
          1. 26.3.5.5.1 Baud rate settings
          2. 26.3.5.5.2 Interrupt settings
          3. 26.3.5.5.3 Protocol settings
          4. 26.3.5.5.4 UART/IrDA(SIR/MIR/FIR)/CIR
        6. 26.3.5.6 Hardware and Software Flow Control Configuration
          1. 26.3.5.6.1 Hardware Flow Control Configuration
          2. 26.3.5.6.2 Software Flow Control Configuration
        7. 26.3.5.7 IrDA Programming Model (UART3 Only)
          1. 26.3.5.7.1 SIR mode
            1. 26.3.5.7.1.1 Receive
            2. 26.3.5.7.1.2 Transmit
          2. 26.3.5.7.2 MIR mode
            1. 26.3.5.7.2.1 Receive
            2. 26.3.5.7.2.2 Transmit
          3. 26.3.5.7.3 FIR mode
            1. 26.3.5.7.3.1 Receive
            2. 26.3.5.7.3.2 Transmit
      6. 26.3.6 UART/IrDA/CIR Register Manual
        1. 26.3.6.1 UART/IrDA/CIR Instance Summary
        2. 26.3.6.2 UART/IrDA/CIR Registers
          1. 26.3.6.2.1 UART/IrDA/CIR Register Summary
          2. 26.3.6.2.2 UART/IrDA/CIR Register Description
    4. 26.4  Multichannel Serial Peripheral Interface
      1. 26.4.1 McSPI Overview
      2. 26.4.2 McSPI Environment
        1. 26.4.2.1 Basic McSPI Pins for Master Mode
        2. 26.4.2.2 Basic McSPI Pins for Slave Mode
        3. 26.4.2.3 Multichannel SPI Protocol and Data Format
          1. 26.4.2.3.1 Transfer Format
        4. 26.4.2.4 SPI in Master Mode
        5. 26.4.2.5 SPI in Slave Mode
      3. 26.4.3 McSPI Integration
      4. 26.4.4 McSPI Functional Description
        1. 26.4.4.1 McSPI Block Diagram
        2. 26.4.4.2 Reset
        3. 26.4.4.3 Master Mode
          1. 26.4.4.3.1 Master Mode Features
          2. 26.4.4.3.2 Master Transmit-and-Receive Mode (Full Duplex)
          3. 26.4.4.3.3 Master Transmit-Only Mode (Half Duplex)
          4. 26.4.4.3.4 Master Receive-Only Mode (Half Duplex)
          5. 26.4.4.3.5 Single-Channel Master Mode
            1. 26.4.4.3.5.1 Programming Tips When Switching to Another Channel
            2. 26.4.4.3.5.2 Force SPIEN[x] Mode
            3. 26.4.4.3.5.3 Turbo Mode
          6. 26.4.4.3.6 Start-Bit Mode
          7. 26.4.4.3.7 Chip-Select Timing Control
          8. 26.4.4.3.8 Programmable SPI Clock
            1. 26.4.4.3.8.1 Clock Ratio Granularity
        4. 26.4.4.4 Slave Mode
          1. 26.4.4.4.1 Dedicated Resources
          2. 26.4.4.4.2 Slave Transmit-and-Receive Mode
          3. 26.4.4.4.3 Slave Transmit-Only Mode
          4. 26.4.4.4.4 Slave Receive-Only Mode
        5. 26.4.4.5 3-Pin or 4-Pin Mode
        6. 26.4.4.6 FIFO Buffer Management
          1. 26.4.4.6.1 Buffer Almost Full
          2. 26.4.4.6.2 Buffer Almost Empty
          3. 26.4.4.6.3 End of Transfer Management
        7. 26.4.4.7 Interrupts
          1. 26.4.4.7.1 Interrupt Events in Master Mode
            1. 26.4.4.7.1.1 TXx_EMPTY
            2. 26.4.4.7.1.2 TXx_UNDERFLOW
            3. 26.4.4.7.1.3 RXx_ FULL
            4. 26.4.4.7.1.4 End Of Word Count
          2. 26.4.4.7.2 Interrupt Events in Slave Mode
            1. 26.4.4.7.2.1 TXx_EMPTY
            2. 26.4.4.7.2.2 TXx_UNDERFLOW
            3. 26.4.4.7.2.3 RXx_FULL
            4. 26.4.4.7.2.4 RX0_OVERFLOW
            5. 26.4.4.7.2.5 End Of Word Count
          3. 26.4.4.7.3 Interrupt-Driven Operation
          4. 26.4.4.7.4 Polling
        8. 26.4.4.8 DMA Requests
        9. 26.4.4.9 Power Saving Management
          1. 26.4.4.9.1 Normal Mode
          2. 26.4.4.9.2 Idle Mode
            1. 26.4.4.9.2.1 Wake-Up Event in Smart-Idle Mode
            2. 26.4.4.9.2.2 Transitions From Smart-Idle Mode to Normal Mode
            3. 26.4.4.9.2.3 Force-Idle Mode
      5. 26.4.5 McSPI Programming Guide
        1. 26.4.5.1 Global Initialization
          1. 26.4.5.1.1 Surrounding Modules Global Initialization
          2. 26.4.5.1.2 McSPI Global Initialization
            1. 26.4.5.1.2.1 Main Sequence – McSPI Global Initialization
        2. 26.4.5.2 Operational Mode Configuration
          1. 26.4.5.2.1 McSPI Operational Modes
            1. 26.4.5.2.1.1 Common Transfer Sequence
            2. 26.4.5.2.1.2 End of Transfer Sequences
            3. 26.4.5.2.1.3 Transmit-and-Receive (Master and Slave)
            4. 26.4.5.2.1.4 Transmit-Only (Master and Slave)
              1. 26.4.5.2.1.4.1 Based on Interrupt Requests
              2. 26.4.5.2.1.4.2 Based on DMA Write Requests
            5. 26.4.5.2.1.5 Master Normal Receive-Only
              1. 26.4.5.2.1.5.1 Based on Interrupt Requests
              2. 26.4.5.2.1.5.2 Based on DMA Read Requests
            6. 26.4.5.2.1.6 Master Turbo Receive-Only
              1. 26.4.5.2.1.6.1 Based on Interrupt Requests
              2. 26.4.5.2.1.6.2 Based on DMA Read Requests
            7. 26.4.5.2.1.7 Slave Receive-Only
            8. 26.4.5.2.1.8 Transfer Procedures With FIFO
              1. 26.4.5.2.1.8.1 Common Transfer Sequence in FIFO Mode
              2. 26.4.5.2.1.8.2 End of Transfer Sequences in FIFO Mode
              3. 26.4.5.2.1.8.3 Transmit-and-Receive With Word Count
              4. 26.4.5.2.1.8.4 Transmit-and-Receive Without Word Count
              5. 26.4.5.2.1.8.5 Transmit-Only
              6. 26.4.5.2.1.8.6 Receive-Only With Word Count
              7. 26.4.5.2.1.8.7 Receive-Only Without Word Count
        3. 26.4.5.3 Common Transfer Procedures Without FIFO – Polling Method
          1. 26.4.5.3.1 Receive-Only Procedure – Polling Method
          2. 26.4.5.3.2 Receive-Only Procedure – Interrupt Method
          3. 26.4.5.3.3 Transmit-Only Procedure – Polling Method
          4. 26.4.5.3.4 Transmit-and-Receive Procedure – Polling Method
      6. 26.4.6 McSPI Register Manual
        1. 26.4.6.1 McSPI Instance Summary
        2. 26.4.6.2 McSPI Registers
          1. 26.4.6.2.1 McSPI Register Summary
          2. 26.4.6.2.2 McSPI Register Description
    5. 26.5  Quad Serial Peripheral Interface
      1. 26.5.1 Quad Serial Peripheral Interface Overview
      2. 26.5.2 QSPI Environment
      3. 26.5.3 QSPI Integration
      4. 26.5.4 QSPI Functional Description
        1. 26.5.4.1 QSPI Block Diagram
          1. 26.5.4.1.1 SFI Register Control
          2. 26.5.4.1.2 SFI Translator
          3. 26.5.4.1.3 SPI Control Interface
          4. 26.5.4.1.4 SPI Clock Generator
          5. 26.5.4.1.5 SPI Control State-Machine
          6. 26.5.4.1.6 SPI Data Shifter
        2. 26.5.4.2 QSPI Clock Configuration
        3. 26.5.4.3 QSPI Interrupt Requests
        4. 26.5.4.4 QSPI Memory Regions
      5. 26.5.5 QSPI Register Manual
        1. 26.5.5.1 QSPI Instance Summary
        2. 26.5.5.2 QSPI registers
          1. 26.5.5.2.1 QSPI Register Summary
          2. 26.5.5.2.2 QSPI Register Description
    6. 26.6  Multichannel Audio Serial Port
      1. 26.6.1 McASP Overview
      2. 26.6.2 McASP Environment
        1. 26.6.2.1 McASP Signals
        2. 26.6.2.2 Protocols and Data Formats
          1. 26.6.2.2.1 Protocols Supported
          2. 26.6.2.2.2 Definition of Terms
          3. 26.6.2.2.3 TDM Format
          4. 26.6.2.2.4 I2S Format
          5. 26.6.2.2.5 S/PDIF Coding Format
            1. 26.6.2.2.5.1 Biphase-Mark Code
            2. 26.6.2.2.5.2 S/PDIF Subframe Format
            3. 26.6.2.2.5.3 Frame Format
      3. 26.6.3 McASP Integration
      4. 26.6.4 McASP Functional Description
        1. 26.6.4.1  McASP Block Diagram
        2. 26.6.4.2  McASP Clock and Frame-Sync Configurations
          1. 26.6.4.2.1 McASP Transmit Clock
          2. 26.6.4.2.2 McASP Receive Clock
          3. 26.6.4.2.3 Frame-Sync Generator
          4. 26.6.4.2.4 Synchronous and Asynchronous Transmit and Receive Operations
        3. 26.6.4.3  Serializers
        4. 26.6.4.4  Format Units
          1. 26.6.4.4.1 Transmit Format Unit
            1. 26.6.4.4.1.1 TDM Mode Transmission Data Alignment Settings
            2. 26.6.4.4.1.2 DIT Mode Transmission Data Alignment Settings
          2. 26.6.4.4.2 Receive Format Unit
            1. 26.6.4.4.2.1 TDM Mode Reception Data Alignment Settings
        5. 26.6.4.5  State-Machines
        6. 26.6.4.6  TDM Sequencers
        7. 26.6.4.7  McASP Software Reset
        8. 26.6.4.8  McASP Power Management
        9. 26.6.4.9  Transfer Modes
          1. 26.6.4.9.1 Burst Transfer Mode
          2. 26.6.4.9.2 Time-Division Multiplexed (TDM) Transfer Mode
            1. 26.6.4.9.2.1 TDM Time Slots Generation and Processing
            2. 26.6.4.9.2.2 Special 384-Slot TDM Mode for Connection to External DIR
          3. 26.6.4.9.3 DIT Transfer Mode
            1. 26.6.4.9.3.1 Transmit DIT Encoding
            2. 26.6.4.9.3.2 Transmit DIT Clock and Frame-Sync Generation
            3. 26.6.4.9.3.3 DIT Channel Status and User Data Register Files
        10. 26.6.4.10 Data Transmission and Reception
          1. 26.6.4.10.1 Data Ready Status and Event/Interrupt Generation
            1. 26.6.4.10.1.1 Transmit Data Ready
            2. 26.6.4.10.1.2 Receive Data Ready
            3. 26.6.4.10.1.3 Transfers Through the Data Port (DATA)
            4. 26.6.4.10.1.4 Transfers Through the Configuration Bus (CFG)
            5. 26.6.4.10.1.5 Using a Device CPU for McASP Servicing
            6. 26.6.4.10.1.6 Using the DMA for McASP Servicing
        11. 26.6.4.11 McASP Audio FIFO (AFIFO)
          1. 26.6.4.11.1 AFIFO Data Transmission
            1. 26.6.4.11.1.1 Transmit DMA Event Pacer
          2. 26.6.4.11.2 AFIFO Data Reception
            1. 26.6.4.11.2.1 Receive DMA Event Pacer
          3. 26.6.4.11.3 Arbitration Between Transmit and Receive DMA Requests
        12. 26.6.4.12 McASP Events and Interrupt Requests
          1. 26.6.4.12.1 Transmit Data Ready Event and Interrupt
          2. 26.6.4.12.2 Receive Data Ready Event and Interrupt
          3. 26.6.4.12.3 Error Interrupt
          4. 26.6.4.12.4 Multiple Interrupts
        13. 26.6.4.13 DMA Requests
        14. 26.6.4.14 Loopback Modes
          1. 26.6.4.14.1 Loopback Mode Configurations
        15. 26.6.4.15 Error Reporting
          1. 26.6.4.15.1 Buffer Underrun Error -Transmitter
          2. 26.6.4.15.2 Buffer Overrun Error-Receiver
          3. 26.6.4.15.3 DATA Port Error - Transmitter
          4. 26.6.4.15.4 DATA Port Error - Receiver
          5. 26.6.4.15.5 Unexpected Frame Sync Error
          6. 26.6.4.15.6 Clock Failure Detection
            1. 26.6.4.15.6.1 Clock Failure Check Startup
            2. 26.6.4.15.6.2 Transmit Clock Failure Check and Recovery
            3. 26.6.4.15.6.3 Receive Clock Failure Check and Recovery
      5. 26.6.5 McASP Low-Level Programming Model
        1. 26.6.5.1 Global Initialization
          1. 26.6.5.1.1 Surrounding Modules Global Initialization
          2. 26.6.5.1.2 McASP Global Initialization
            1. 26.6.5.1.2.1 Main Sequence – McASP Global Initialization for DIT-Transmission
              1. 26.6.5.1.2.1.1 Subsequence – Transmit Format Unit Configuration for DIT-Transmission
              2. 26.6.5.1.2.1.2 Subsequence – Transmit Frame Synchronization Generator Configuration for DIT-Transmission
              3. 26.6.5.1.2.1.3 Subsequence – Transmit Clock Generator Configuration for DIT-Transmission
              4. 26.6.5.1.2.1.4 Subsequence - McASP Pins Functional Configuration
              5. 26.6.5.1.2.1.5 Subsequence – DIT-specific Subframe Fields Configuration
            2. 26.6.5.1.2.2 Main Sequence – McASP Global Initialization for TDM-Reception
              1. 26.6.5.1.2.2.1 Subsequence – Receive Format Unit Configuration in TDM Mode
              2. 26.6.5.1.2.2.2 Subsequence – Receive Frame Synchronization Generator Configuration in TDM Mode
              3. 26.6.5.1.2.2.3 Subsequence – Receive Clock Generator Configuration
              4. 26.6.5.1.2.2.4 Subsequence—McASP Receiver Pins Functional Configuration
            3. 26.6.5.1.2.3 Main Sequence – McASP Global Initialization for TDM -Transmission
              1. 26.6.5.1.2.3.1 Subsequence – Transmit Format Unit Configuration in TDM Mode
              2. 26.6.5.1.2.3.2 Subsequence – Transmit Frame Synchronization Generator Configuration in TDM Mode
              3. 26.6.5.1.2.3.3 Subsequence – Transmit Clock Generator Configuration for TDM Cases
              4. 26.6.5.1.2.3.4 Subsequence—McASP Transmit Pins Functional Configuration
        2. 26.6.5.2 Operational Modes Configuration
          1. 26.6.5.2.1 McASP Transmission Modes
            1. 26.6.5.2.1.1 Main Sequence – McASP DIT- /TDM- Polling Transmission Method
            2. 26.6.5.2.1.2 Main Sequence – McASP DIT- /TDM - Interrupt Transmission Method
            3. 26.6.5.2.1.3 Main Sequence –McASP DIT- /TDM - Mode DMA Transmission Method
          2. 26.6.5.2.2 McASP Reception Modes
            1. 26.6.5.2.2.1 Main Sequence – McASP Polling Reception Method
            2. 26.6.5.2.2.2 Main Sequence – McASP TDM - Interrupt Reception Method
            3. 26.6.5.2.2.3 Main Sequence – McASP TDM - Mode DMA Reception Method
          3. 26.6.5.2.3 McASP Event Servicing
            1. 26.6.5.2.3.1 McASP DIT-/TDM- Transmit Interrupt Events Servicing
            2. 26.6.5.2.3.2 McASP TDM- Receive Interrupt Events Servicing
            3. 26.6.5.2.3.3 4175
            4. 26.6.5.2.3.4 Subsequence – McASP DIT-/TDM -Modes Transmit Error Handling
            5. 26.6.5.2.3.5 Subsequence – McASP Receive Error Handling
      6. 26.6.6 McASP Register Manual
        1. 26.6.6.1 McASP Instance Summary
        2. 26.6.6.2 McASP Registers
          1. 26.6.6.2.1 MCASP_CFG Register Summary
          2. 26.6.6.2.2 MCASP_CFG Register Description
          3. 26.6.6.2.3 MCASP_AFIFO Register Summary
          4. 26.6.6.2.4 MCASP_AFIFO Register Description
          5. 26.6.6.2.5 MCASP_DAT Register Summary
          6. 26.6.6.2.6 MCASP_DAT Register Description
    7. 26.7  SuperSpeed USB DRD
      1. 26.7.1 SuperSpeed USB DRD Subsystem Overview
        1. 26.7.1.1 Main Features
      2. 26.7.2 SuperSpeed USB DRD Subsystem Environment
        1. 26.7.2.1 SuperSpeed USB DRD Subsystem I/O Interfaces
        2. 26.7.2.2 SuperSpeed USB Subsystem Application
          1. 26.7.2.2.1 USB3.0 DRD Application
          2. 26.7.2.2.2 USB2.0 DRD Internal PHY
          3. 26.7.2.2.3 USB2.0 DRD External PHY
          4. 26.7.2.2.4 4196
          5. 26.7.2.2.5 Host Mode
          6. 26.7.2.2.6 Device Mode
      3. 26.7.3 SuperSpeed USB Subsystem Integration
    8. 26.8  SATA Controller
      1. 26.8.1 SATA Controller Overview
        1. 26.8.1.1 SATA Controller
          1. 26.8.1.1.1 AHCI Mode Overview
          2. 26.8.1.1.2 Native Command Queuing
          3. 26.8.1.1.3 SATA Transport Layer Functionalities
          4. 26.8.1.1.4 SATA Link Layer Functionalities
        2. 26.8.1.2 SATA Controller Features
      2. 26.8.2 SATA Controller Environment
      3. 26.8.3 SATA Controller Integration
      4. 26.8.4 SATA Controller Functional Description
        1. 26.8.4.1  SATA Controller Block Diagram
        2. 26.8.4.2  SATA Controller Link Layer Protocol and Data Format
          1. 26.8.4.2.1 SATA 8b/10b Parallel Encoding/Decoding
          2. 26.8.4.2.2 SATA Stream Dword Components
          3. 26.8.4.2.3 Scrambling/Descrambling Processing
        3. 26.8.4.3  Resets
          1. 26.8.4.3.1 Hardware Reset
          2. 26.8.4.3.2 Software Initiated Resets
            1. 26.8.4.3.2.1 Software Reset
            2. 26.8.4.3.2.2 Port Reset
            3. 26.8.4.3.2.3 HBA Reset
        4. 26.8.4.4  Power Management
          1. 26.8.4.4.1 SATA Specific Power Management
            1. 26.8.4.4.1.1 PARTIAL Power Mode
            2. 26.8.4.4.1.2 Slumber Power Mode
            3. 26.8.4.4.1.3 Software Control over Low Power States
            4. 26.8.4.4.1.4 Aggressive Power Management
          2. 26.8.4.4.2 Master Standby and Slave Idle Management Protocols
          3. 26.8.4.4.3 Clock Gating Synchronization
          4. 26.8.4.4.4 4230
        5. 26.8.4.5  Interrupt Requests
          1. 26.8.4.5.1 Interrupt Generation
          2. 26.8.4.5.2 Levels of Interrupt Control
          3. 26.8.4.5.3 Interrupt Events Description
            1. 26.8.4.5.3.1  Task File Error Status
            2. 26.8.4.5.3.2  Host Bus Fatal Error
            3. 26.8.4.5.3.3  Interface Fatal Error Status
            4. 26.8.4.5.3.4  Interface Non-Fatal Error Status
            5. 26.8.4.5.3.5  Overflow Status
            6. 26.8.4.5.3.6  Incorrect Port Multiplier Status
            7. 26.8.4.5.3.7  PHYReady Change Status
            8. 26.8.4.5.3.8  Port Connect Change Status
            9. 26.8.4.5.3.9  Descriptor Processed
            10. 26.8.4.5.3.10 Unknown FIS Interrupt
            11. 26.8.4.5.3.11 Set Device Bits Interrupt
            12. 26.8.4.5.3.12 DMA Setup FIS Interrupt
            13. 26.8.4.5.3.13 PIO Setup FIS Interrupt
            14. 26.8.4.5.3.14 Device to Host Register FIS Interrupt
          4. 26.8.4.5.4 Interrupt Condition Control
          5. 26.8.4.5.5 Command Completion Coalescing Interrupts
            1. 26.8.4.5.5.1 CCC Interrupt Based on Expired Timeout Value
            2. 26.8.4.5.5.2 CCC Interrupt Based on Completion Count
        6. 26.8.4.6  System Memory FIS Descriptors
          1. 26.8.4.6.1 Command List Structure Basics
          2. 26.8.4.6.2 Supported Types of Commands
          3. 26.8.4.6.3 Received FIS Structures
          4. 26.8.4.6.4 FIS Descriptors Summary
        7. 26.8.4.7  Transport Layer FIS-Based Interactions
          1. 26.8.4.7.1 Software Processing of the Port Command List
          2. 26.8.4.7.2 Handling the Received FIS Descriptors
        8. 26.8.4.8  DMA Port Configuration
        9. 26.8.4.9  Port Multiplier Operation
          1. 26.8.4.9.1 Command-Based Switching Mode
            1. 26.8.4.9.1.1 Port Multiplier NCQ and Non-NCQ Commands Generation
          2. 26.8.4.9.2 Port Multiplier Enumeration
        10. 26.8.4.10 Activity LED Generation Functionality
        11. 26.8.4.11 Supported Types of SATA Transfers
          1. 26.8.4.11.1 Supported Higher Level Protocols
        12. 26.8.4.12 SATA Controller AHCI Hardware Register Interface
      5. 26.8.5 SATA Controller Low Level Programming Model
        1. 26.8.5.1 Global Initialization
          1. 26.8.5.1.1 Surrounding Modules Global Initialization
          2. 26.8.5.1.2 SATA Controller Global Initialization
            1. 26.8.5.1.2.1 Main Sequence SATA Controller Global Initialization
            2. 26.8.5.1.2.2 SubSequence – Firmware Capability Writes
          3. 26.8.5.1.3 Issue Command - Main Sequence
          4. 26.8.5.1.4 Receive FIS—Main Sequence
      6. 26.8.6 SATA Controller Register Manual
        1. 26.8.6.1 SATA Controller Instance Summary
        2. 26.8.6.2 DWC_ahsata Registers
          1. 26.8.6.2.1 DWC_ahsata Register Summary
          2. 26.8.6.2.2 DWC_ahsata Register Description
        3. 26.8.6.3 SATAMAC_wrapper Registers
          1. 26.8.6.3.1 SATAMAC_wrapper Register Summary
          2. 26.8.6.3.2 SATAMAC_wrapper Register Description
    9. 26.9  PCIe Controller
      1. 26.9.1 PCIe Controller Subsystem Overview
        1. 26.9.1.1 PCIe Controllers Key Features
      2. 26.9.2 PCIe Controller Environment
      3. 26.9.3 PCIe Controllers Integration
      4. 26.9.4 PCIe SS Controller Functional Description
        1. 26.9.4.1 PCIe Controller Functional Block Diagram
        2. 26.9.4.2 PCIe Traffics
        3. 26.9.4.3 PCIe Controller Ports on L3_MAIN Interconnect
          1. 26.9.4.3.1 PCIe Controller Master Port
            1. 26.9.4.3.1.1 PCIe Controller Master Port to MMU Routing
          2. 26.9.4.3.2 PCIe Controller Slave Port
          3. 26.9.4.3.3 4298
        4. 26.9.4.4 PCIe Controller Reset Management
          1. 26.9.4.4.1 PCIe Reset Types and Stickiness
          2. 26.9.4.4.2 PCIe Reset Conditions
            1. 26.9.4.4.2.1 PCIe Main Reset
              1. 26.9.4.4.2.1.1 PCIe Subsystem Cold Main Reset Source
              2. 26.9.4.4.2.1.2 PCIe Subsystem Warm Main Reset Sources
            2. 26.9.4.4.2.2 PCIe Standard Specific Resets to the PCIe Core Logic
        5. 26.9.4.5 PCIe Controller Power Management
          1. 26.9.4.5.1 PCIe Protocol Power Management
            1. 26.9.4.5.1.1 PCIe Device/function power state (D-state)
            2. 26.9.4.5.1.2 PCIe Controller PIPE Powerstate (Powerdown Control)
          2. 26.9.4.5.2 PCIE Controller Clocks Management
            1. 26.9.4.5.2.1 PCIe Clock Domains
            2. 26.9.4.5.2.2 PCIe Controller Idle/Standby Clock Management Interfaces
              1. 26.9.4.5.2.2.1 PCIe Controller Master Standby Behavior
              2. 26.9.4.5.2.2.2 PCIe Controller Slave Idle/Disconnect Behavior
                1. 26.9.4.5.2.2.2.1 PCIe Controller Idle Sequence During D3cold/L3 State
        6. 26.9.4.6 PCIe Controller Interrupt Requests
          1. 26.9.4.6.1 PCIe Controller Main Hardware Management
            1. 26.9.4.6.1.1 PCIe Management Interrupt Events
            2. 26.9.4.6.1.2 PCIe Error Interrupt Events
            3. 26.9.4.6.1.3 Summary of PCIe Controller Main Hardware Interrupt Events
          2. 26.9.4.6.2 PCIe Controller Legacy and MSI Virtual Interrupts Management
            1. 26.9.4.6.2.1 Legacy PCI Interrupts (INTx)
              1. 26.9.4.6.2.1.1 Legacy PCI Interrupt Events Overview
              2. 26.9.4.6.2.1.2 Legacy PCI Interrupt Transmission (EP mode only)
              3. 26.9.4.6.2.1.3 Legacy PCI Interrupt Reception (RC mode only)
            2. 26.9.4.6.2.2 PCIe Controller Message Signaled Interrupts (MSI)
              1. 26.9.4.6.2.2.1 PCIe Specific MSI Interrupt Event Overview
              2. 26.9.4.6.2.2.2 PCIe Controller MSI Transmission Methods (EP mode)
                1. 26.9.4.6.2.2.2.1 PCIe Controller MSI transmission, hardware method
                2. 26.9.4.6.2.2.2.2 PCIe Controller MSI transmission, software method
              3. 26.9.4.6.2.2.3 PCIe Controller MSI Reception (RC mode)
          3. 26.9.4.6.3 PCIe Controller MSI Hardware Interrupt Events
        7. 26.9.4.7 PCIe Controller Address Spaces and Address Translation
        8. 26.9.4.8 PCIe Traffic Requesting and Responding
          1. 26.9.4.8.1 PCIe Memory-type (Mem) Traffic Management
            1. 26.9.4.8.1.1 PCIe Memory Requesting
            2. 26.9.4.8.1.2 PCIe Memory Responding
          2. 26.9.4.8.2 PCIe Configuration Type (Cfg) Traffic Management
            1. 26.9.4.8.2.1 RC Self-configuration (RC Only)
            2. 26.9.4.8.2.2 Configuration Requests over PCIe (RC Only)
            3. 26.9.4.8.2.3 Configuration Responding over PCIe (EP Only)
          3. 26.9.4.8.3 PCIe I/O-type (IO) traffic management
            1. 26.9.4.8.3.1 PCIe I/O requesting (RC only)
            2. 26.9.4.8.3.2 PCIe IO BAR initialization before enumeration (EP only)
            3. 26.9.4.8.3.3 PCIe I/O responding (PCI legacy EP only)
          4. 26.9.4.8.4 PCIe Message-type (Msg) traffic management
        9. 26.9.4.9 PCIe Programming Register Interface
          1. 26.9.4.9.1 PCIe Register Access
          2. 26.9.4.9.2 Double Mapping of the PCIe Local Control Registers
          3. 26.9.4.9.3 Base Address Registers (BAR) Initialization
      5. 26.9.5 PCIe Controller Low Level Programming Model
        1. 26.9.5.1 Surrounding Modules Global Initialization
        2. 26.9.5.2 Main Sequence of PCIe Controllers Initalization
      6. 26.9.6 PCIe Standard Registers vs PCIe Subsystem Hardware Registers Mapping
      7. 26.9.7 PCIe Controller Register Manual
        1. 26.9.7.1 PCIe Controller Instance Summary
        2. 26.9.7.2 PCIe_SS_EP_CFG_PCIe Registers
          1. 26.9.7.2.1 PCIe_SS_EP_CFG_PCIe Register Summary
          2. 26.9.7.2.2 PCIe_SS_EP_CFG_PCIe Register Description
          3. 26.9.7.2.3 4360
        3. 26.9.7.3 PCIe_SS_EP_CFG_DBICS Registers
          1. 26.9.7.3.1 PCIe_SS_EP_CFG_DBICS Register Summary
          2. 26.9.7.3.2 PCIe_SS_EP_CFG_DBICS Register Description
        4. 26.9.7.4 PCIe_SS_RC_CFG_DBICS Registers
          1. 26.9.7.4.1 PCIe_SS_RC_CFG_DBICS Register Summary
          2. 26.9.7.4.2 PCIe_SS_RC_CFG_DBICS Register Description
        5. 26.9.7.5 PCIe_SS_PL_CONF Registers
          1. 26.9.7.5.1 PCIe_SS_PL_CONF Register Summary
          2. 26.9.7.5.2 PCIe_SS_PL_CONF Register Description
        6. 26.9.7.6 PCIe_SS_EP_CFG_DBICS2 Registers
          1. 26.9.7.6.1 PCIe_SS_EP_CFG_DBICS2 Register Summary
          2. 26.9.7.6.2 PCIe_SS_EP_CFG_DBICS2 Register Description
        7. 26.9.7.7 PCIe_SS_RC_CFG_DBICS2 Registers
          1. 26.9.7.7.1 PCIe_SS_RC_CFG_DBICS2 Register Summary
          2. 26.9.7.7.2 PCIe_SS_RC_CFG_DBICS2 Register Description
        8. 26.9.7.8 PCIe_SS_TI_CONF Registers
          1. 26.9.7.8.1 PCIe_SS_TI_CONF Register Summary
          2. 26.9.7.8.2 PCIe_SS_TI_CONF Register Description
    10. 26.10 DCAN
      1. 26.10.1 DCAN Overview
        1. 26.10.1.1 Features
      2. 26.10.2 DCAN Environment
        1. 26.10.2.1 CAN Network Basics
      3. 26.10.3 DCAN Integration
      4. 26.10.4 DCAN Functional Description
        1. 26.10.4.1  Module Clocking Requirements
        2. 26.10.4.2  Interrupt Functionality
          1. 26.10.4.2.1 Message Object Interrupts
          2. 26.10.4.2.2 Status Change Interrupts
          3. 26.10.4.2.3 Error Interrupts
        3. 26.10.4.3  DMA Functionality
        4. 26.10.4.4  Local Power-Down Mode
          1. 26.10.4.4.1 Entering Local Power-Down Mode
          2. 26.10.4.4.2 Wakeup From Local Power Down
        5. 26.10.4.5  Parity Check Mechanism
          1. 26.10.4.5.1 Behavior on Parity Error
          2. 26.10.4.5.2 Parity Testing
        6. 26.10.4.6  Debug/Suspend Mode
        7. 26.10.4.7  Configuration of Message Objects Description
          1. 26.10.4.7.1 Configuration of a Transmit Object for Data Frames
          2. 26.10.4.7.2 Configuration of a Transmit Object for Remote Frames
          3. 26.10.4.7.3 Configuration of a Single Receive Object for Data Frames
          4. 26.10.4.7.4 Configuration of a Single Receive Object for Remote Frames
          5. 26.10.4.7.5 Configuration of a FIFO Buffer
        8. 26.10.4.8  Message Handling
          1. 26.10.4.8.1  Message Handler Overview
          2. 26.10.4.8.2  Receive/Transmit Priority
          3. 26.10.4.8.3  Transmission of Messages in Event Driven CAN Communication
          4. 26.10.4.8.4  Updating a Transmit Object
          5. 26.10.4.8.5  Changing a Transmit Object
          6. 26.10.4.8.6  Acceptance Filtering of Received Messages
          7. 26.10.4.8.7  Reception of Data Frames
          8. 26.10.4.8.8  Reception of Remote Frames
          9. 26.10.4.8.9  Reading Received Messages
          10. 26.10.4.8.10 Requesting New Data for a Receive Object
          11. 26.10.4.8.11 Storing Received Messages in FIFO Buffers
          12. 26.10.4.8.12 Reading From a FIFO Buffer
        9. 26.10.4.9  CAN Bit Timing
          1. 26.10.4.9.1 Bit Time and Bit Rate
            1. 26.10.4.9.1.1 Synchronization Segment
            2. 26.10.4.9.1.2 Propagation Time Segment
            3. 26.10.4.9.1.3 Phase Buffer Segments and Synchronization
            4. 26.10.4.9.1.4 Oscillator Tolerance Range
          2. 26.10.4.9.2 DCAN Bit Timing Registers
            1. 26.10.4.9.2.1 Calculation of the Bit Timing Parameters
            2. 26.10.4.9.2.2 Example for Bit Timing Calculation
        10. 26.10.4.10 Message Interface Register Sets
          1. 26.10.4.10.1 Message Interface Register Sets 1 and 2
          2. 26.10.4.10.2 IF3 Register Set
        11. 26.10.4.11 Message RAM
          1. 26.10.4.11.1 Structure of Message Objects
          2. 26.10.4.11.2 Addressing Message Objects in RAM
          3. 26.10.4.11.3 Message RAM Representation in Debug/Suspend Mode
          4. 26.10.4.11.4 Message RAM Representation in Direct Access Mode
        12. 26.10.4.12 CAN Operation
          1. 26.10.4.12.1 CAN Module Initialization
            1. 26.10.4.12.1.1 Configuration of CAN Bit Timing
            2. 26.10.4.12.1.2 Configuration of Message Objects
            3. 26.10.4.12.1.3 DCAN RAM Hardware Initialization
          2. 26.10.4.12.2 CAN Message Transfer (Normal Operation)
            1. 26.10.4.12.2.1 Automatic Retransmission
            2. 26.10.4.12.2.2 Auto-Bus-On
          3. 26.10.4.12.3 Test Modes
            1. 26.10.4.12.3.1 Silent Mode
            2. 26.10.4.12.3.2 Loopback Mode
            3. 26.10.4.12.3.3 External Loopback Mode
            4. 26.10.4.12.3.4 Loopback Mode Combined With Silent Mode
            5. 26.10.4.12.3.5 Software Control of CAN_TX Pin
        13. 26.10.4.13 GPIO Support
      5. 26.10.5 DCAN Register Manual
        1. 26.10.5.1 DCAN Instance Summary
        2. 26.10.5.2 DCAN Registers
          1. 26.10.5.2.1 DCAN Register Summary
          2. 26.10.5.2.2 DCAN Register Description
    11. 26.11 MCAN
      1. 26.11.1 MCAN Overview
        1. 26.11.1.1 Features
      2. 26.11.2 MCAN Environment
        1. 26.11.2.1 CAN Network Basics
      3. 26.11.3 MCAN Integration
      4. 26.11.4 MCAN Functional Description
        1. 26.11.4.1  Module Clocking Requirements
        2. 26.11.4.2  Interrupt and DMA Requests
          1. 26.11.4.2.1 Interrupt Requests
          2. 26.11.4.2.2 DMA Requests
          3. 26.11.4.2.3 4466
        3. 26.11.4.3  Fuseable CAN FD Operation Enable
        4. 26.11.4.4  Operating Modes
          1. 26.11.4.4.1 Software Initialization
          2. 26.11.4.4.2 Normal Operation
          3. 26.11.4.4.3 CAN FD Operation
          4. 26.11.4.4.4 Transmitter Delay Compensation
            1. 26.11.4.4.4.1 Description
            2. 26.11.4.4.4.2 Transmitter Delay Compensation Measurement
          5. 26.11.4.4.5 Restricted Operation Mode
          6. 26.11.4.4.6 Bus Monitoring Mode
          7. 26.11.4.4.7 Disabled Automatic Retransmission (DAR) Mode
            1. 26.11.4.4.7.1 Frame Transmission in DAR Mode
          8. 26.11.4.4.8 Power Down (Sleep Mode)
            1. 26.11.4.4.8.1 External Clock Stop Mode
            2. 26.11.4.4.8.2 Suspend Mode
            3. 26.11.4.4.8.3 Wakeup request
          9. 26.11.4.4.9 Test Modes
            1. 26.11.4.4.9.1 Internal Loop Back Mode
        5. 26.11.4.5  Timestamp Generation
          1. 26.11.4.5.1 External Timestamp Counter
        6. 26.11.4.6  Timeout Counter
        7. 26.11.4.7  Safety
          1. 26.11.4.7.1 ECC Wrapper
          2. 26.11.4.7.2 ECC Aggregator
            1. 26.11.4.7.2.1 ECC Aggregator Overview
            2. 26.11.4.7.2.2 ECC Aggregator Registers
            3. 26.11.4.7.2.3 Reads to ECC Control and Status Registers
            4. 26.11.4.7.2.4 ECC Interrupts
        8. 26.11.4.8  Rx Handling
          1. 26.11.4.8.1 Acceptance Filtering
            1. 26.11.4.8.1.1 Range Filter
            2. 26.11.4.8.1.2 Filter for specific IDs
            3. 26.11.4.8.1.3 Classic Bit Mask Filter
            4. 26.11.4.8.1.4 Standard Message ID Filtering
            5. 26.11.4.8.1.5 Extended Message ID Filtering
          2. 26.11.4.8.2 Rx FIFOs
            1. 26.11.4.8.2.1 Rx FIFO Blocking Mode
            2. 26.11.4.8.2.2 Rx FIFO Overwrite Mode
          3. 26.11.4.8.3 Dedicated Rx Buffers
            1. 26.11.4.8.3.1 Rx Buffer Handling
        9. 26.11.4.9  Tx Handling
          1. 26.11.4.9.1 Transmit Pause
          2. 26.11.4.9.2 Dedicated Tx Buffers
          3. 26.11.4.9.3 Tx FIFO
          4. 26.11.4.9.4 Tx Queue
          5. 26.11.4.9.5 Mixed Dedicated Tx Buffers/Tx FIFO
          6. 26.11.4.9.6 Mixed Dedicated Tx Buffers/Tx Queue
          7. 26.11.4.9.7 Transmit Cancellation
          8. 26.11.4.9.8 Tx Event Handling
        10. 26.11.4.10 FIFO Acknowledge Handling
        11. 26.11.4.11 Message RAM
          1. 26.11.4.11.1 Message RAM Configuration
          2. 26.11.4.11.2 Rx Buffer and FIFO Element
          3. 26.11.4.11.3 Tx Buffer Element
          4. 26.11.4.11.4 Tx Event FIFO Element
          5. 26.11.4.11.5 Standard Message ID Filter Element
          6. 26.11.4.11.6 Extended Message ID Filter Element
      5. 26.11.5 MCAN Register Manual
        1. 26.11.5.1 MCAN Instance Summary
        2. 26.11.5.2 MCAN Registers
          1. 26.11.5.2.1 MCAN Register Summary
          2. 26.11.5.2.2 MCAN Register Description
    12. 26.12 Gigabit Ethernet Switch (GMAC_SW)
      1. 26.12.1 GMAC_SW Overview
        1. 26.12.1.1 Features
        2. 26.12.1.2 4532
      2. 26.12.2 GMAC_SW Environment
        1. 26.12.2.1 G/MII Interface
        2. 26.12.2.2 RMII Interface
        3. 26.12.2.3 RGMII Interface
      3. 26.12.3 GMAC_SW Integration
      4. 26.12.4 GMAC_SW Functional Description
        1. 26.12.4.1  Functional Block Diagram
        2. 26.12.4.2  GMAC_SW Ports
          1. 26.12.4.2.1 Interface Mode Selection
        3. 26.12.4.3  Clocking
          1. 26.12.4.3.1 Subsystem Clocking
          2. 26.12.4.3.2 Interface Clocking
            1. 26.12.4.3.2.1 G/MII Interface Clocking
            2. 26.12.4.3.2.2 RGMII Interface Clocking
            3. 26.12.4.3.2.3 RMII Interface Clocking
            4. 26.12.4.3.2.4 MDIO Clocking
        4. 26.12.4.4  Software IDLE
        5. 26.12.4.5  Interrupt Functionality
          1. 26.12.4.5.1 Receive Packet Completion Pulse Interrupt (RX_PULSE)
          2. 26.12.4.5.2 Transmit Packet Completion Pulse Interrupt (TX_PULSE)
          3. 26.12.4.5.3 Receive Threshold Pulse Interrupt (RX_THRESH_PULSE)
          4. 26.12.4.5.4 Miscellaneous Pulse Interrupt (MISC_PULSE)
            1. 26.12.4.5.4.1 EVNT_PEND( CPTS_PEND) Interrupt
            2. 26.12.4.5.4.2 Statistics Interrupt
            3. 26.12.4.5.4.3 Host Error interrupt
            4. 26.12.4.5.4.4 MDIO Interrupts
          5. 26.12.4.5.5 Interrupt Pacing
        6. 26.12.4.6  Reset Isolation
          1. 26.12.4.6.1 Reset Isolation Functional Description
        7. 26.12.4.7  Software Reset
        8. 26.12.4.8  CPSW_3G
          1. 26.12.4.8.1  CPDMA RX and TX Interfaces
            1. 26.12.4.8.1.1 Functional Operation
            2. 26.12.4.8.1.2 Receive DMA Interface
              1. 26.12.4.8.1.2.1 Receive DMA Host Configuration
              2. 26.12.4.8.1.2.2 Receive Channel Teardown
            3. 26.12.4.8.1.3 Transmit DMA Interface
              1. 26.12.4.8.1.3.1 Transmit DMA Host Configuration
              2. 26.12.4.8.1.3.2 Transmit Channel Teardown
            4. 26.12.4.8.1.4 Transmit Rate Limiting
            5. 26.12.4.8.1.5 Command IDLE
          2. 26.12.4.8.2  Address Lookup Engine (ALE)
            1. 26.12.4.8.2.1 Address Table Entry
              1. 26.12.4.8.2.1.1 Free Table Entry
              2. 26.12.4.8.2.1.2 Multicast Address Table Entry
              3. 26.12.4.8.2.1.3 VLAN/Multicast Address Table Entry
              4. 26.12.4.8.2.1.4 Unicast Address Table Entry
              5. 26.12.4.8.2.1.5 OUI Unicast Address Table Entry
              6. 26.12.4.8.2.1.6 VLAN/Unicast Address Table Entry
              7. 26.12.4.8.2.1.7 VLAN Table Entry
            2. 26.12.4.8.2.2 Packet Forwarding Processes
            3. 26.12.4.8.2.3 Learning Process
            4. 26.12.4.8.2.4 VLAN Aware Mode
            5. 26.12.4.8.2.5 VLAN Unaware Mode
          3. 26.12.4.8.3  Packet Priority Handling
          4. 26.12.4.8.4  FIFO Memory Control
          5. 26.12.4.8.5  FIFO Transmit Queue Control
            1. 26.12.4.8.5.1 Normal Priority Mode
            2. 26.12.4.8.5.2 Dual MAC Mode
            3. 26.12.4.8.5.3 Rate Limit Mode
          6. 26.12.4.8.6  Audio Video Bridging
            1. 26.12.4.8.6.1 IEEE 802.1AS: Timing and Synchronization for Time-Sensitive Applications in Bridged Local Area Networks (Precision Time Protocol (PTP))
              1. 26.12.4.8.6.1.1 IEEE 1722: "Layer 2 Transport Protocol for Time-Sensitive Streams"
              2. 26.12.4.8.6.1.2 IEEE 1733: Extends RTCP for RTP Streaming over AVB-supported Networks
            2. 26.12.4.8.6.2 IEEE 802.1Qav: "Virtual Bridged Local Area Networks: Forwarding and Queuing for Time-Sensitive Streams"
              1. 26.12.4.8.6.2.1 Configuring the Device for 802.1Qav Operation:
          7. 26.12.4.8.7  Ethernet MAC Sliver (CPGMAC_SL)
            1. 26.12.4.8.7.1 G/MII Media Independent Interface
              1. 26.12.4.8.7.1.1 Data Reception
                1. 26.12.4.8.7.1.1.1 Receive Control
                2. 26.12.4.8.7.1.1.2 Receive Inter-Frame Interval
              2. 26.12.4.8.7.1.2 Data Transmission
                1. 26.12.4.8.7.1.2.1 Transmit Control
                2. 26.12.4.8.7.1.2.2 CRC Insertion
                3. 26.12.4.8.7.1.2.3 MTXER
                4. 26.12.4.8.7.1.2.4 Adaptive Performance Optimization (APO)
                5. 26.12.4.8.7.1.2.5 Inter-Packet-Gap Enforcement
                6. 26.12.4.8.7.1.2.6 Back Off
                7. 26.12.4.8.7.1.2.7 Programmable Transmit Inter-Packet Gap
                8. 26.12.4.8.7.1.2.8 Speed, Duplex and Pause Frame Support Negotiation
            2. 26.12.4.8.7.2 RMII Interface
              1. 26.12.4.8.7.2.1 Features
              2. 26.12.4.8.7.2.2 RMII Receive (RX)
              3. 26.12.4.8.7.2.3 RMII Transmit (TX)
            3. 26.12.4.8.7.3 RGMII Interface
              1. 26.12.4.8.7.3.1 RGMII Features
              2. 26.12.4.8.7.3.2 RGMII Receive (RX)
              3. 26.12.4.8.7.3.3 In-Band Mode of Operation
              4. 26.12.4.8.7.3.4 Forced Mode of Operation
              5. 26.12.4.8.7.3.5 RGMII Transmit (TX)
            4. 26.12.4.8.7.4 Frame Classification
          8. 26.12.4.8.8  Embedded Memories
          9. 26.12.4.8.9  Flow Control
            1. 26.12.4.8.9.1 CPPI Port Flow Control
            2. 26.12.4.8.9.2 Ethernet Port Flow Control
              1. 26.12.4.8.9.2.1 Receive Flow Control
                1. 26.12.4.8.9.2.1.1 Collision Based Receive Buffer Flow Control
                2. 26.12.4.8.9.2.1.2 IEEE 802.3X Based Receive Flow Control
              2. 26.12.4.8.9.2.2 Transmit Flow Control
          10. 26.12.4.8.10 Short Gap
          11. 26.12.4.8.11 Switch Latency
          12. 26.12.4.8.12 Emulation Control
          13. 26.12.4.8.13 FIFO Loopback
          14. 26.12.4.8.14 Device Level Ring (DLR) Support
          15. 26.12.4.8.15 Energy Efficient Ethernet Support (802.3az)
          16. 26.12.4.8.16 CPSW_3G Network Statistics
            1. 26.12.4.8.16.1 4639
        9. 26.12.4.9  Static Packet Filter (SPF)
          1. 26.12.4.9.1 SPF Overview
          2. 26.12.4.9.2 SPF Functional Description
            1. 26.12.4.9.2.1 SPF Block Diagram
            2. 26.12.4.9.2.2 Interrupts
            3. 26.12.4.9.2.3 Protocol Header Extractor
            4. 26.12.4.9.2.4 Programmable Rule Engine
              1. 26.12.4.9.2.4.1 Internal Registers
              2. 26.12.4.9.2.4.2 Packet Buffer
            5. 26.12.4.9.2.5 Intrusion Event Logger
            6. 26.12.4.9.2.6 Rate Limiter
            7. 26.12.4.9.2.7 Rule Engine Instruction Set Architecture
              1. 26.12.4.9.2.7.1 Instruction Format
              2. 26.12.4.9.2.7.2 Operand Field
              3. 26.12.4.9.2.7.3 Arithmetic/Logical Function Field
              4. 26.12.4.9.2.7.4 Operation Field
          3. 26.12.4.9.3 Programming Guide
            1. 26.12.4.9.3.1 Initialization Routine
            2. 26.12.4.9.3.2 Interrupt Service Routine
            3. 26.12.4.9.3.3 Rule Engine Example Program
        10. 26.12.4.10 Common Platform Time Sync (CPTS)
          1. 26.12.4.10.1 CPTS Architecture
          2. 26.12.4.10.2 CPTS Initialization
          3. 26.12.4.10.3 Time Stamp Value
          4. 26.12.4.10.4 Event FIFO
          5. 26.12.4.10.5 Time Sync Events
            1. 26.12.4.10.5.1 Time Stamp Push Event
            2. 26.12.4.10.5.2 Time Stamp Counter Rollover Event
            3. 26.12.4.10.5.3 Time Stamp Counter Half-rollover Event
            4. 26.12.4.10.5.4 Hardware Time Stamp Push Event
            5. 26.12.4.10.5.5 Ethernet Port Events
          6. 26.12.4.10.6 CPTS Interrupt Handling
        11. 26.12.4.11 CPPI Buffer Descriptors
          1. 26.12.4.11.1 TX Buffer Descriptors
            1. 26.12.4.11.1.1 CPPI TX Data Word 0
            2. 26.12.4.11.1.2 CPPI TX Data Word 1
            3. 26.12.4.11.1.3 CPPI TX Data Word 2
            4. 26.12.4.11.1.4 CPPI TX Data Word 3
          2. 26.12.4.11.2 RX Buffer Descriptors
            1. 26.12.4.11.2.1 CPPI RX Data Word 0
            2. 26.12.4.11.2.2 CPPI RX Data Word 1
            3. 26.12.4.11.2.3 CPPI RX Data Word 2
            4. 26.12.4.11.2.4 CPPI RX Data Word 3
        12. 26.12.4.12 MDIO
          1. 26.12.4.12.1 MDIO Frame Formats
          2. 26.12.4.12.2 MDIO Functional Description
      5. 26.12.5 GMAC_SW Programming Guide
        1. 26.12.5.1 Transmit Operation
        2. 26.12.5.2 Receive Operation
        3. 26.12.5.3 MDIO Software Interface
          1. 26.12.5.3.1 Initializing the MDIO Module
          2. 26.12.5.3.2 Writing Data To a PHY Register
          3. 26.12.5.3.3 Reading Data From a PHY Register
        4. 26.12.5.4 Initialization and Configuration of CPSW
      6. 26.12.6 GMAC_SW Register Manual
        1. 26.12.6.1  GMAC_SW Instance Summary
        2. 26.12.6.2  SS Registers
          1. 26.12.6.2.1 SS Register Summary
          2. 26.12.6.2.2 SS Register Description
        3. 26.12.6.3  PORT Registers
          1. 26.12.6.3.1 PORT Register Summary
          2. 26.12.6.3.2 PORT Register Description
        4. 26.12.6.4  CPDMA registers
          1. 26.12.6.4.1 CPDMA Register Summary
          2. 26.12.6.4.2 CPDMA Register Description
        5. 26.12.6.5  STATS Registers
          1. 26.12.6.5.1 STATS Register Summary
          2. 26.12.6.5.2 STATS Register Description
        6. 26.12.6.6  STATERAM Registers
          1. 26.12.6.6.1 STATERAM Register Summary
          2. 26.12.6.6.2 STATERAM Register Description
        7. 26.12.6.7  CPTS registers
          1. 26.12.6.7.1 CPTS Register Summary
          2. 26.12.6.7.2 CPTS Register Description
        8. 26.12.6.8  ALE registers
          1. 26.12.6.8.1 ALE Register Summary
          2. 26.12.6.8.2 ALE Register Description
        9. 26.12.6.9  SL registers
          1. 26.12.6.9.1 SL Register Summary
          2. 26.12.6.9.2 SL Register Description
        10. 26.12.6.10 MDIO registers
          1. 26.12.6.10.1 MDIO Register Summary
          2. 26.12.6.10.2 MDIO Register Description
        11. 26.12.6.11 WR registers
          1. 26.12.6.11.1 WR Register Summary
          2. 26.12.6.11.2 WR Register Description
        12. 26.12.6.12 SPF Registers
          1. 26.12.6.12.1 SPF Register Summary
          2. 26.12.6.12.2 SPF Register Description
    13. 26.13 Media Local Bus (MLB)
      1. 26.13.1 MLB Overview
      2. 26.13.2 MLB Environment
        1. 26.13.2.1 MLB IO Cell Controls
        2. 26.13.2.2 Doubling the MLB Clock Line Frequency
      3. 26.13.3 MLB Integration
      4. 26.13.4 MLB Functional Description
        1. 26.13.4.1 Block Diagram
          1. 26.13.4.1.1 MediaLB Core Block
          2. 26.13.4.1.2 Routing Fabric Block
          3. 26.13.4.1.3 Data Buffer RAM
          4. 26.13.4.1.4 Channel Table RAM
            1. 26.13.4.1.4.1 Channel Allocation Table
            2. 26.13.4.1.4.2 Channel Descriptor Table
          5. 26.13.4.1.5 DMA Block
            1. 26.13.4.1.5.1 Synchronous Channel Descriptor
            2. 26.13.4.1.5.2 Isochronous Channel Descriptors
            3. 26.13.4.1.5.3 Asynchronous and Control Channel Descriptors
              1. 26.13.4.1.5.3.1 Single-Packet Mode
              2. 26.13.4.1.5.3.2 Multiple-Packet Mode
        2. 26.13.4.2 Software and Data Flow for MLBSS
          1. 26.13.4.2.1 Data Flow For Receive Channels
          2. 26.13.4.2.2 Data Flow for Transmit Channels
        3. 26.13.4.3 MLB Priority On The L3_MAIN Interconnect
      5. 26.13.5 MLB Programming Guide
        1. 26.13.5.1 Global Initialization
          1. 26.13.5.1.1 Surrounding Modules Global Initialization
          2. 26.13.5.1.2 MLBSS Global Initialization
            1. 26.13.5.1.2.1 Channel Initialization
        2. 26.13.5.2 MLBSS Operational Modes Configuration
          1. 26.13.5.2.1 Channel Servicing
          2. 26.13.5.2.2 Channel Table RAM Access
      6. 26.13.6 MLB Register Manual
        1. 26.13.6.1 MLB Instance Summary
        2. 26.13.6.2 MLB registers
          1. 26.13.6.2.1 MLB Register Summary
          2. 26.13.6.2.2 MLB Register Description
  29. 27eMMC/SD/SDIO
    1. 27.1 eMMC/SD/SDIO Overview
      1. 27.1.1 eMMC/SD/SDIO Features
    2. 27.2 eMMC/SD/SDIO Environment
      1. 27.2.1 eMMC/SD/SDIO Functional Modes
        1. 27.2.1.1 eMMC/SD/SDIO Connected to an eMMC, SD, or SDIO Card
      2. 27.2.2 Protocol and Data Format
        1. 27.2.2.1 Protocol
        2. 27.2.2.2 Data Format
    3. 27.3 eMMC/SD/SDIO Integration
    4. 27.4 eMMC/SD/SDIO Functional Description
      1. 27.4.1  Block Diagram
      2. 27.4.2  Resets
        1. 27.4.2.1 Hardware Reset
        2. 27.4.2.2 Software Reset
      3. 27.4.3  Power Management
      4. 27.4.4  Interrupt Requests
        1. 27.4.4.1 Interrupt-Driven Operation
        2. 27.4.4.2 Polling
        3. 27.4.4.3 Asynchronous Interrupt
      5. 27.4.5  DMA Modes
        1. 27.4.5.1 Master DMA Operations
          1. 27.4.5.1.1 Descriptor Table Description
          2. 27.4.5.1.2 Requirements for Descriptors
            1. 27.4.5.1.2.1 Data Length
            2. 27.4.5.1.2.2 Supported Features
            3. 27.4.5.1.2.3 Error Generation
          3. 27.4.5.1.3 Advanced DMA Description
        2. 27.4.5.2 Slave DMA Operations
          1. 27.4.5.2.1 DMA Receive Mode
          2. 27.4.5.2.2 DMA Transmit Mode
      6. 27.4.6  Mode Selection
      7. 27.4.7  Buffer Management
        1. 27.4.7.1 Data Buffer
          1. 27.4.7.1.1 Memory Size, Block Length, and Buffer-Management Relationship
          2. 27.4.7.1.2 Data Buffer Status
      8. 27.4.8  Transfer Process
        1. 27.4.8.1 Different Types of Commands
        2. 27.4.8.2 Different Types of Responses
      9. 27.4.9  Transfer or Command Status and Errors Reporting
        1. 27.4.9.1 Busy Time-Out for R1b, R5b Response Type
        2. 27.4.9.2 Busy Time-Out After Write CRC Status
        3. 27.4.9.3 Write CRC Status Time-Out
        4. 27.4.9.4 Read Data Time-Out
        5. 27.4.9.5 Boot Acknowledge Time-Out
      10. 27.4.10 Auto Command 12 Timings
        1. 27.4.10.1 Auto CMD12 Timings During Write Transfer
        2. 27.4.10.2 Auto CMD12 Timings During Read Transfer
      11. 27.4.11 Transfer Stop
      12. 27.4.12 Output Signals Generation
        1. 27.4.12.1 Generation on Falling Edge of MMC Clock
        2. 27.4.12.2 Generation on Rising Edge of MMC Clock
      13. 27.4.13 Sampling Clock Tuning
      14. 27.4.14 Card Boot Mode Management
        1. 27.4.14.1 Boot Mode Using CMD0
        2. 27.4.14.2 Boot Mode With CMD Line Tied to 0
      15. 27.4.15 MMC CE-ATA Command Completion Disable Management
      16. 27.4.16 Test Registers
      17. 27.4.17 eMMC/SD/SDIO Hardware Status Features
    5. 27.5 eMMC/SD/SDIO Programming Guide
      1. 27.5.1 Low-Level Programming Models
        1. 27.5.1.1 Global Initialization
          1. 27.5.1.1.1 Surrounding Modules Global Initialization
          2. 27.5.1.1.2 eMMC/SD/SDIO Host Controller Initialization Flow
            1. 27.5.1.1.2.1 Enable Interface and Functional Clock for MMC Controller
            2. 27.5.1.1.2.2 MMCHS Soft Reset Flow
            3. 27.5.1.1.2.3 Set MMCHS Default Capabilities
            4. 27.5.1.1.2.4 Wake-Up Configuration
            5. 27.5.1.1.2.5 MMC Host and Bus Configuration
        2. 27.5.1.2 Operational Modes Configuration
          1. 27.5.1.2.1 Basic Operations for eMMC/SD/SDIO Host Controller
            1. 27.5.1.2.1.1 Card Detection, Identification, and Selection
              1. 27.5.1.2.1.1.1 CMD Line Reset Procedure
            2. 27.5.1.2.1.2 Read/Write Transfer Flow in DMA Mode With Interrupt
              1. 27.5.1.2.1.2.1 DATA Lines Reset Procedure
            3. 27.5.1.2.1.3 Read/Write Transfer Flow in DMA Mode With Polling
            4. 27.5.1.2.1.4 Read/Write Transfer Flow Without DMA With Polling
            5. 27.5.1.2.1.5 Read/Write Transfer Flow in CE-ATA Mode
            6. 27.5.1.2.1.6 Suspend-Resume Flow
              1. 27.5.1.2.1.6.1 Suspend Flow
              2. 27.5.1.2.1.6.2 Resume Flow
            7. 27.5.1.2.1.7 Basic Operations – Steps Detailed
              1. 27.5.1.2.1.7.1 Command Transfer Flow
              2. 27.5.1.2.1.7.2 MMCHS Clock Frequency Change
              3. 27.5.1.2.1.7.3 Bus Width Selection
          2. 27.5.1.2.2 Bus Voltage Selection
          3. 27.5.1.2.3 Boot Mode Configuration
            1. 27.5.1.2.3.1 Boot Using CMD0
            2. 27.5.1.2.3.2 Boot With CMD Line Tied to 0
          4. 27.5.1.2.4 SDR104/HS200 DLL Tuning Procedure
    6. 27.6 eMMC/SD/SDIO Register Manual
      1. 27.6.1 eMMC/SD/SDIO Instance Summary
      2. 27.6.2 eMMC/SD/SDIO Registers
        1. 27.6.2.1 eMMC/SD/SDIO Register Summary
        2. 27.6.2.2 eMMC/SD/SDIO Register Description
  30. 28Shared PHY Component Subsystem
    1. 28.1 SATA PHY Subsystem
      1. 28.1.1 SATA PHY Subsystem Overview
      2. 28.1.2 SATA PHY Subsystem Environment
        1. 28.1.2.1 SATA PHY I/O Signals
      3. 28.1.3 SATA PHY Subsystem Integration
      4. 28.1.4 SATA PHY Subsystem Functional Description
        1. 28.1.4.1 SATA PLL Controller L4 Interface Adapter Functional Description
        2. 28.1.4.2 SATA PHY Serializer and Deserializer Functional Descriptions
          1. 28.1.4.2.1 SATA PHY Reset
          2. 28.1.4.2.2 SATA_PHY Clocking
            1. 28.1.4.2.2.1 SATA_PHY Input Clocks
            2. 28.1.4.2.2.2 SATA_PHY Output Clocks
          3. 28.1.4.2.3 SATA_PHY Power Management
            1. 28.1.4.2.3.1 SATA_PHY Power-Up/-Down Sequences
            2. 28.1.4.2.3.2 SATA_PHY Low-Power Modes
          4. 28.1.4.2.4 SATA_PHY Hardware Requests
        3. 28.1.4.3 SATA Clock Generator Subsystem Functional Description
          1. 28.1.4.3.1 SATA DPLL Clock Generator Overview
          2. 28.1.4.3.2 SATA DPLL Clock Generator Reset
          3. 28.1.4.3.3 SATA DPLL Low-Power Modes
          4. 28.1.4.3.4 SATA DPLL Clocks Configuration
            1. 28.1.4.3.4.1 SATA DPLL Input Clock Control
            2. 28.1.4.3.4.2 SATA DPLL Output Clock Configuration
              1. 28.1.4.3.4.2.1 SATA DPLL Output Clock Gating
          5. 28.1.4.3.5 SATA DPLL Subsystem Architecture
          6. 28.1.4.3.6 SATA DPLL Clock Generator Modes and State Transitions
            1. 28.1.4.3.6.1 SATA Clock Generator Power Up
            2. 28.1.4.3.6.2 SATA DPLL Sequences
            3. 28.1.4.3.6.3 SATA DPLL Locked Mode
            4. 28.1.4.3.6.4 SATA DPLL Idle-Bypass Mode
            5. 28.1.4.3.6.5 SATA DPLL MN-Bypass Mode
            6. 28.1.4.3.6.6 SATA DPLL Error Conditions
          7. 28.1.4.3.7 SATA PLL Controller Functions
            1. 28.1.4.3.7.1 SATA PLL Controller Register Access
            2. 28.1.4.3.7.2 SATA DPLL Clock Programming Sequence
            3. 28.1.4.3.7.3 SATA DPLL Recommended Values
      5. 28.1.5 SATA PHY Subsystem Low-Level Programming Model
    2. 28.2 USB3_PHY Subsystem
      1. 28.2.1 USB3_PHY Subsystem Overview
      2. 28.2.2 USB3_PHY Subsystem Environment
        1. 28.2.2.1 USB3_PHY I/O Signals
      3. 28.2.3 USB3_PHY Subsystem Integration
      4. 28.2.4 USB3_PHY Subsystem Functional Description
        1. 28.2.4.1 Super-Speed USB PLL Controller L4 Interface Adapter Functional Description
        2. 28.2.4.2 USB3_PHY Serializer and Deserializer Functional Descriptions
          1. 28.2.4.2.1 USB3_PHY Module Resets
            1. 28.2.4.2.1.1 Hardware Reset
            2. 28.2.4.2.1.2 Software Reset
          2. 28.2.4.2.2 USB3_PHY Subsystem Clocking
            1. 28.2.4.2.2.1 USB3_PHY Subsystem Input Clocks
            2. 28.2.4.2.2.2 USB3_PHY Subsystem Output Clocks
          3. 28.2.4.2.3 USB3_PHY Power Management
            1. 28.2.4.2.3.1 USB3_PHY Power-Up/-Down Sequences
            2. 28.2.4.2.3.2 USB3_PHY Low-Power Modes
            3. 28.2.4.2.3.3 Clock Gating
          4. 28.2.4.2.4 USB3_PHY Hardware Requests
        3. 28.2.4.3 USB3_PHY Clock Generator Subsystem Functional Description
          1. 28.2.4.3.1 USB3_PHY DPLL Clock Generator Overview
          2. 28.2.4.3.2 USB3_PHY DPLL Clock Generator Reset
          3. 28.2.4.3.3 USB3_PHY DPLL Low-Power Modes
          4. 28.2.4.3.4 USB3_PHY DPLL Clocks Configuration
            1. 28.2.4.3.4.1 USB3_PHY DPLL Input Clock Control
            2. 28.2.4.3.4.2 USB3_PHY DPLL Output Clock Configuration
              1. 28.2.4.3.4.2.1 USB3_PHY DPLL Output Clock Gating
          5. 28.2.4.3.5 USB3_PHY DPLL Subsystem Architecture
          6. 28.2.4.3.6 USB3_PHY DPLL Clock Generator Modes and State Transitions
            1. 28.2.4.3.6.1 USB3_PHY Clock Generator Power Up
            2. 28.2.4.3.6.2 USB3_PHY DPLL Sequences
            3. 28.2.4.3.6.3 USB3_PHY DPLL Locked Mode
            4. 28.2.4.3.6.4 USB3_PHY DPLL Idle-Bypass Mode
            5. 28.2.4.3.6.5 USB3_PHY DPLL MN-Bypass Mode
            6. 28.2.4.3.6.6 USB3_PHY DPLL Error Conditions
          7. 28.2.4.3.7 USB3_PHY PLL Controller Functions
            1. 28.2.4.3.7.1 USB3_PHY PLL Controller Register Access
            2. 28.2.4.3.7.2 4936
            3. 28.2.4.3.7.3 USB3_PHY DPLL Clock Programming Sequence
            4. 28.2.4.3.7.4 USB3_PHY DPLL Recommended Values
      5. 28.2.5 USB3_PHY Subsystem Low-Level Programming Model
    3. 28.3 USB3 PHY and SATA PHY Register Manual
      1. 28.3.1 USB3 PHY and SATA PHY Instance Summary
      2. 28.3.2 USB3_PHY_RX Registers
        1. 28.3.2.1 USB3_PHY_RX Register Summary
        2. 28.3.2.2 USB3_PHY_RX Register Description
      3. 28.3.3 USB3_PHY_TX Registers
        1. 28.3.3.1 USB3_PHY_TX Register Summary
        2. 28.3.3.2 USB3_PHY_TX Register Description
      4. 28.3.4 SATA_PHY_RX Registers
        1. 28.3.4.1 SATA_PHY_RX Register Summary
        2. 28.3.4.2 SATA_PHY_RX Register Description
      5. 28.3.5 SATA_PHY_TX Registers
        1. 28.3.5.1 SATA_PHY_TX Register Summary
        2. 28.3.5.2 SATA_PHY_TX Register Description
      6. 28.3.6 DPLLCTRL Registers
        1. 28.3.6.1 DPLLCTRL Register Summary
        2. 28.3.6.2 DPLLCTRL Register Description
    4. 28.4 PCIe PHY Subsystem
      1. 28.4.1 PCIe PHY Subsystem Overview
        1. 28.4.1.1 PCIe PHY Subsystem Key Features
      2. 28.4.2 PCIe PHY Subsystem Environment
        1. 28.4.2.1 PCIe PHY I/O Signals
      3. 28.4.3 PCIe Shared PHY Subsystem Integration
      4. 28.4.4 PCIe PHY Subsystem Functional Description
        1. 28.4.4.1 PCIe PHY Subsystem Block Diagram
        2. 28.4.4.2 OCP2SCP Functional Description
          1. 28.4.4.2.1 OCP2SCP Reset
            1. 28.4.4.2.1.1 Hardware Reset
            2. 28.4.4.2.1.2 Software Reset
          2. 28.4.4.2.2 OCP2SCP Power Management
            1. 28.4.4.2.2.1 Idle Mode
            2. 28.4.4.2.2.2 Clock Gating
          3. 28.4.4.2.3 OCP2SCP Timing Registers
        3. 28.4.4.3 PCIe PHY Serializer and Deserializer Functional Descriptions
          1. 28.4.4.3.1 PCIe PHY Module Resets
            1. 28.4.4.3.1.1 Hardware Reset
            2. 28.4.4.3.1.2 Software Reset
          2. 28.4.4.3.2 PCIe PHY Subsystem Clocking
            1. 28.4.4.3.2.1 PCIe PHY Subsystem Input Clocks
            2. 28.4.4.3.2.2 PCIe PHY Subsystem Output Clocks
          3. 28.4.4.3.3 PCIe PHY Power Management
            1. 28.4.4.3.3.1 PCIe PHY Power-Up/-Down Sequences
            2. 28.4.4.3.3.2 PCIe PHY Low-Power Modes
            3. 28.4.4.3.3.3 Clock Gating
          4. 28.4.4.3.4 PCIe PHY Hardware Requests
        4. 28.4.4.4 PCIe PHY Clock Generator Subsystem Functional Description
          1. 28.4.4.4.1 PCIe PHY DPLL Clock Generator
            1. 28.4.4.4.1.1 PCIe PHY DPLL Clock Generator Overview
            2. 28.4.4.4.1.2 PCIe PHY DPLL Clock Generator Reset
            3. 28.4.4.4.1.3 PCIe PHY DPLL Low-Power Modes
            4. 28.4.4.4.1.4 PCIe PHY DPLL Clocks Configuration
              1. 28.4.4.4.1.4.1 PCIe PHY DPLL Input Clock Control
              2. 28.4.4.4.1.4.2 PCIe PHY DPLL Output Clock Configuration
                1. 28.4.4.4.1.4.2.1 PCIe PHY DPLL Output Clock Gating
            5. 28.4.4.4.1.5 PCIe PHY DPLL Subsystem Architecture
            6. 28.4.4.4.1.6 PCIe PHY DPLL Clock Generator Modes and State Transitions
              1. 28.4.4.4.1.6.1 PCIe PHY Clock Generator Power Up
              2. 28.4.4.4.1.6.2 PCIe PHY DPLL Sequences
              3. 28.4.4.4.1.6.3 PCIe PHY DPLL Locked Mode
              4. 28.4.4.4.1.6.4 PCIe PHY DPLL Idle-Bypass Mode
              5. 28.4.4.4.1.6.5 PCIe PHY DPLL Low Power Stop Mode
              6. 28.4.4.4.1.6.6 PCIe PHY DPLL Clock Programming Sequence
              7. 28.4.4.4.1.6.7 PCIe PHY DPLL Recommended Values
          2. 28.4.4.4.2 PCIe PHY APLL Clock Generator
            1. 28.4.4.4.2.1 PCIe PHY APLL Clock Generator Overview
            2. 28.4.4.4.2.2 PCIe PHY APLL Clock Generator Reset
            3. 28.4.4.4.2.3 PCIe PHY APLL Low-Power Mode
            4. 28.4.4.4.2.4 PCIe PHY APLL Clocks Configuration
              1. 28.4.4.4.2.4.1 PCIe PHY APLL Input Clock Control
              2. 28.4.4.4.2.4.2 PCIe PHY APLL Output Clock Configuration
                1. 28.4.4.4.2.4.2.1 PCIe PHY APLL Output Clock Gating
            5. 28.4.4.4.2.5 PCIe PHY APLL Subsystem Architecture
            6. 28.4.4.4.2.6 PCIe PHY APLL Clock Generator Modes and State Transitions
              1. 28.4.4.4.2.6.1 PCIe PHY APLL Clock Generator Power Up
              2. 28.4.4.4.2.6.2 PCIe PHY APLL Sequences
              3. 28.4.4.4.2.6.3 PCIe PHY APLL Locked Mode
          3. 28.4.4.4.3 ACSPCIE reference clock buffer
      5. 28.4.5 PCIePHY Subsystem Low-Level Programming Model
      6. 28.4.6 PCIe PHY Subsystem Register Manual
        1. 28.4.6.1 PCIe PHY Instance Summary
          1. 28.4.6.1.1 PCIe_PHY_RX Registers
            1. 28.4.6.1.1.1 PCIe_PHY_RX Register Summary
            2. 28.4.6.1.1.2 PCIe_PHY_RX Register Description
          2. 28.4.6.1.2 PCIe_PHY_TX Registers
            1. 28.4.6.1.2.1 PCIe_PHY_TX Register Summary
            2. 28.4.6.1.2.2 PCIe_PHY_TX Register Description
          3. 28.4.6.1.3 OCP2SCP Registers
            1. 28.4.6.1.3.1 OCP2SCP Register Summary
            2. 28.4.6.1.3.2 OCP2SCP Register Description
  31. 29General-Purpose Interface
    1. 29.1 General-Purpose Interface Overview
    2. 29.2 General-Purpose Interface Environment
      1. 29.2.1 General-Purpose Interface as a Keyboard Interface
      2. 29.2.2 General-Purpose Interface Signals
    3. 29.3 General-Purpose Interface Integration
    4. 29.4 General-Purpose Interface Functional Description
      1. 29.4.1 General-Purpose Interface Block Diagram
      2. 29.4.2 General-Purpose Interface Interrupt and Wake-Up Features
        1. 29.4.2.1 Synchronous Path: Interrupt Request Generation
        2. 29.4.2.2 Asynchronous Path: Wake-Up Request Generation
        3. 29.4.2.3 Wake-Up Event Conditions During Transition To/From IDLE State
        4. 29.4.2.4 Interrupt (or Wake-Up) Line Release
      3. 29.4.3 General-Purpose Interface Clock Configuration
        1. 29.4.3.1 Clocking
      4. 29.4.4 General-Purpose Interface Hardware and Software Reset
      5. 29.4.5 General-Purpose Interface Power Management
        1. 29.4.5.1 Power Domain
        2. 29.4.5.2 Power Management
          1. 29.4.5.2.1 Idle Scheme
          2. 29.4.5.2.2 Operating Modes
          3. 29.4.5.2.3 System Power Management and Wakeup
          4. 29.4.5.2.4 Module Power Saving
      6. 29.4.6 General-Purpose Interface Interrupt and Wake-Up Requests
        1. 29.4.6.1 Interrupt Requests Generation
        2. 29.4.6.2 Wake-Up Requests Generation
      7. 29.4.7 General-Purpose Interface Channels Description
      8. 29.4.8 General-Purpose Interface Data Input/Output Capabilities
      9. 29.4.9 General-Purpose Interface Set-and-Clear Protocol
        1. 29.4.9.1 Description
        2. 29.4.9.2 Clear Instruction
          1. 29.4.9.2.1 Clear Register Addresses
          2. 29.4.9.2.2 Clear Instruction Example
        3. 29.4.9.3 Set Instruction
          1. 29.4.9.3.1 Set Register Addresses
          2. 29.4.9.3.2 Set Instruction Example
    5. 29.5 General-Purpose Interface Programming Guide
      1. 29.5.1 General-Purpose Interface Low-Level Programming Models
        1. 29.5.1.1 Global Initialization
          1. 29.5.1.1.1 Surrounding Modules Global Initialization
          2. 29.5.1.1.2 General-Purpose Interface Module Global Initialization
        2. 29.5.1.2 General-Purpose Interface Operational Modes Configuration
          1. 29.5.1.2.1 General-Purpose Interface Read Input Register
          2. 29.5.1.2.2 General-Purpose Interface Set Bit Function
          3. 29.5.1.2.3 General-Purpose Interface Clear Bit Function
    6. 29.6 General-Purpose Interface Register Manual
      1. 29.6.1 General-Purpose Interface Instance Summary
      2. 29.6.2 General-Purpose Interface Registers
        1. 29.6.2.1 General-Purpose Interface Register Summary
        2. 29.6.2.2 General-Purpose Interface Register Description
  32. 30Keyboard Controller
    1. 30.1 Keyboard Controller Overview
    2. 30.2 Keyboard Controller Environment
      1. 30.2.1 Keyboard Controller Functions/Modes
      2. 30.2.2 Keyboard Controller Signals
      3. 30.2.3 Protocols and Data Formats
    3. 30.3 Keyboard Controller Integration
    4. 30.4 Keyboard Controller Functional Description
      1. 30.4.1 Keyboard Controller Block Diagram
      2. 30.4.2 Keyboard Controller Software Reset
      3. 30.4.3 Keyboard Controller Power Management
      4. 30.4.4 Keyboard Controller Interrupt Requests
      5. 30.4.5 Keyboard Controller Software Mode
      6. 30.4.6 Keyboard Controller Hardware Decoding Modes
        1. 30.4.6.1 Functional Modes
        2. 30.4.6.2 Keyboard Controller Timer
        3. 30.4.6.3 State-Machine Status
        4. 30.4.6.4 Keyboard Controller Interrupt Generation
          1. 30.4.6.4.1 Interrupt-Generation Scheme
          2. 30.4.6.4.2 Keyboard Buffer and Missed Events (Overrun Feature)
      7. 30.4.7 Keyboard Controller Key Coding Registers
      8. 30.4.8 Keyboard Controller Register Access
        1. 30.4.8.1 Write Registers Access
        2. 30.4.8.2 Read Registers Access
    5. 30.5 Keyboard Controller Programming Guide
      1. 30.5.1 Keyboard Controller Low-Level Programming Models
        1. 30.5.1.1 Global Initialization
          1. 30.5.1.1.1 Surrounding Modules Global Initialization
          2. 30.5.1.1.2 Keyboard Controller Global Initialization
            1. 30.5.1.1.2.1 Main Sequence – Keyboard Controller Global Initialization
        2. 30.5.1.2 Operational Modes Configuration
          1. 30.5.1.2.1 Keyboard Controller in Hardware Decoding Mode (Default Mode)
            1. 30.5.1.2.1.1 Main Sequence – Keyboard Controller Hardware Mode
          2. 30.5.1.2.2 Keyboard Controller Software Scanning Mode
            1. 30.5.1.2.2.1 Main Sequence – Keyboard Controller Software Mode
          3. 30.5.1.2.3 Using the Timer
          4. 30.5.1.2.4 State-Machine Status Register
        3. 30.5.1.3 Keyboard Controller Events Servicing
    6. 30.6 Keyboard Controller Register Manual
      1. 30.6.1 Keyboard Controller Instance Summary
      2. 30.6.2 Keyboard Controller Registers
        1. 30.6.2.1 Keyboard Controller Register Summary
        2. 30.6.2.2 Keyboard Controller Register Description
  33. 31Pulse-Width Modulation Subsystem
    1. 31.1 PWM Subsystem Resources
      1. 31.1.1 PWMSS Overview
        1. 31.1.1.1 PWMSS Key Features
        2. 31.1.1.2 PWMSS Unsupported Fetaures
      2. 31.1.2 PWMSS Environment
        1. 31.1.2.1 PWMSS I/O Interface
      3. 31.1.3 PWMSS Integration
        1. 31.1.3.1 PWMSS Module Interfaces Implementation
          1. 31.1.3.1.1 Device Specific PWMSS Features
          2. 31.1.3.1.2 Daisy-Chain Connectivity between PWMSS Modules
          3. 31.1.3.1.3 eHRPWM Modules Time Base Clock Gating
      4. 31.1.4 PWMSS Subsystem Power, Reset and Clock Configuration
        1. 31.1.4.1 PWMSS Local Clock Management
        2. 31.1.4.2 PWMSS Modules Local Clock Gating
        3. 31.1.4.3 PWMSS Software Reset
      5. 31.1.5 PWMSS_CFG Register Manual
        1. 31.1.5.1 PWMSS_CFG Instance Summary
        2. 31.1.5.2 PWMSS_CFG Registers
          1. 31.1.5.2.1 PWMSS_CFG Register Summary
          2. 31.1.5.2.2 PWMSS_CFG Register Description
    2. 31.2 Enhanced PWM (ePWM) Module
    3. 31.3 Enhanced Capture (eCAP) Module
    4. 31.4 Enhanced Quadrature Encoder Pulse (eQEP) Module
  34. 32Viterbi-Decoder Coprocessor
    1. 32.1 VCP Overview
      1. 32.1.1 VCP Features
    2. 32.2 VCP Integration
    3. 32.3 VCP Functional Description
      1. 32.3.1  VCP Block Diagram
      2. 32.3.2  VCP Internal Interfaces
        1. 32.3.2.1 VCP Power Management
          1. 32.3.2.1.1 Idle Mode
        2. 32.3.2.2 VCP Clocks
        3. 32.3.2.3 VCP Resets
        4. 32.3.2.4 Interrupt Requests
        5. 32.3.2.5 EDMA Requests
      3. 32.3.3  Functional Overview
        1. 32.3.3.1 Theoretical Basics of the Convolutional Code.
        2. 32.3.3.2 5161
      4. 32.3.4  VCP Architecture
        1. 32.3.4.1 Sliding Windows Processing
          1. 32.3.4.1.1 Tailed Traceback Mode
          2. 32.3.4.1.2 Mixed Traceback Mode
          3. 32.3.4.1.3 Convergent Traceback Mode
          4. 32.3.4.1.4 F, R, and C Limitations
          5. 32.3.4.1.5 Yamamoto Parameters
          6. 32.3.4.1.6 Input FIFO (Branch Metrics)
          7. 32.3.4.1.7 Output FIFO (Decisions)
      5. 32.3.5  VCP Input Data
        1. 32.3.5.1 Branch Metrics Calculations
      6. 32.3.6  Soft Input Dynamic Ranges
      7. 32.3.7  VCP Memory Sleep Mode
      8. 32.3.8  Decision Data
      9. 32.3.9  Endianness
        1. 32.3.9.1 Branch Metrics
          1. 32.3.9.1.1 Hard Decisions
          2. 32.3.9.1.2 Soft Decisions
      10. 32.3.10 VCP Output Parameters
      11. 32.3.11 Event Generation
        1. 32.3.11.1 VCPnXEVT Generation
        2. 32.3.11.2 VCPnREVT Generation
      12. 32.3.12 Operational Modes
        1. 32.3.12.1 Debugging Features
      13. 32.3.13 Errors and Status
    4. 32.4 VCP Modules Programming Guide
      1. 32.4.1 EDMA Resources
        1. 32.4.1.1 VCP1 and VCP2 Dedicated EDMA Resources
        2. 32.4.1.2 Special VCP EDMA Programming Considerations
          1. 32.4.1.2.1 Input Configuration Parameters Transfer
          2. 32.4.1.2.2 Branch Metrics Transfer
          3. 32.4.1.2.3 Decisions Transfer
          4. 32.4.1.2.4 Hard-Decisions Mode
          5. 32.4.1.2.5 Soft-Decisions Mode
          6. 32.4.1.2.6 Output Parameters Transfer
      2. 32.4.2 Input Configuration Words
    5. 32.5 VCP Register Manual
      1. 32.5.1 VCP1 and VCP2 Instance Summary
      2. 32.5.2 VCP Registers
        1. 32.5.2.1 VCP Register Summary
        2. 32.5.2.2 VCP1 and VCP2 Data Registers Description
        3. 32.5.2.3 VCP1 and VCP2 Configuration Registers Description
  35. 33Audio Tracking Logic
    1. 33.1 ATL Overview
    2. 33.2 ATL Environment
      1. 33.2.1 ATL Functions
      2. 33.2.2 ATL Signals Descriptions
    3. 33.3 ATL Integration
      1. 33.3.1 ATL Distribution on Interconnects
      2. 33.3.2 ATL Regions Allocations
    4. 33.4 ATL Functional Description
      1. 33.4.1 Block Diagram
      2. 33.4.2 Source Signal Control
      3. 33.4.3 ATL Clock and Reset Configuration
    5. 33.5 ATL Register Manual
      1. 33.5.1 ATL Instance Summary
      2. 33.5.2 ATL Register Summary
      3. 33.5.3 ATL Register Description
  36. 34Initialization
    1. 34.1 Initialization Overview
      1. 34.1.1 Terminology
      2. 34.1.2 Initialization Process
    2. 34.2 Preinitialization
      1. 34.2.1 Power Requirements
      2. 34.2.2 Interaction With the PMIC Companion
      3. 34.2.3 Clock, Reset, and Control
        1. 34.2.3.1 Overview
        2. 34.2.3.2 Clocking Scheme
        3. 34.2.3.3 Reset Configuration
          1. 34.2.3.3.1 ON/OFF Interconnect and Power-On-Reset
          2. 34.2.3.3.2 Warm Reset
          3. 34.2.3.3.3 Peripheral Reset by GPIO
          4. 34.2.3.3.4 Warm Reset Impact on GPIOs
        4. 34.2.3.4 PMIC Control
        5. 34.2.3.5 PMIC Request Signals
      4. 34.2.4 Sysboot Configuration
        1. 34.2.4.1 GPMC Configuration for XIP/NAND
        2. 34.2.4.2 System Clock Speed Selection
        3. 34.2.4.3 QSPI Redundant SBL Images Offset
        4. 34.2.4.4 Booting Device Order Selection
        5. 34.2.4.5 5242
        6. 34.2.4.6 Boot Peripheral Pin Multiplexing
    3. 34.3 Device Initialization by ROM Code
      1. 34.3.1 Booting Overview
        1. 34.3.1.1 Booting Types
        2. 34.3.1.2 ROM Code Architecture
      2. 34.3.2 Memory Maps
        1. 34.3.2.1 ROM Memory Map
        2. 34.3.2.2 RAM Memory Map
      3. 34.3.3 Overall Booting Sequence
      4. 34.3.4 Startup and Configuration
        1. 34.3.4.1 Startup
        2. 34.3.4.2 Control Module Configuration
        3. 34.3.4.3 PRCM Module Mode Configuration
        4. 34.3.4.4 Clocking Configuration
        5. 34.3.4.5 Booting Device List Setup
      5. 34.3.5 Peripheral Booting
        1. 34.3.5.1 Description
        2. 34.3.5.2 Initialization Phase for UART Boot
        3. 34.3.5.3 Initialization Phase for USB Boot
          1. 34.3.5.3.1 Initialization Procedure
          2. 34.3.5.3.2 SATA Peripheral Device Flashing over USB Interface
          3. 34.3.5.3.3 USB Driver Descriptors
          4. 34.3.5.3.4 5265
          5. 34.3.5.3.5 USB Customized Vendor and Product IDs
          6. 34.3.5.3.6 USB Driver Functionality
      6. 34.3.6 Fast External Booting
        1. 34.3.6.1 Overview
        2. 34.3.6.2 Fast External Booting Procedure
      7. 34.3.7 Memory Booting
        1. 34.3.7.1 Overview
        2. 34.3.7.2 Non-XIP Memory
        3. 34.3.7.3 XIP Memory
          1. 34.3.7.3.1 GPMC Initialization
        4. 34.3.7.4 NAND
          1. 34.3.7.4.1 Initialization and NAND Detection
          2. 34.3.7.4.2 NAND Read Sector Procedure
        5. 34.3.7.5 SPI/QSPI Flash Devices
        6. 34.3.7.6 eMMC Memories and SD Cards
          1. 34.3.7.6.1 eMMC Memories
            1. 34.3.7.6.1.1 System Conditions and Limitations
            2. 34.3.7.6.1.2 eMMC Memory Connection
          2. 34.3.7.6.2 SD Cards
            1. 34.3.7.6.2.1 System Conditions and Limitations
            2. 34.3.7.6.2.2 SD Card Connection
            3. 34.3.7.6.2.3 Booting Procedure
            4. 34.3.7.6.2.4 eMMC Partitions Handling in Alternative Boot Operation Mode
              1. 34.3.7.6.2.4.1 eMMC Devices Preflashing
              2. 34.3.7.6.2.4.2 eMMC Device State After ROM Code Execution
              3. 34.3.7.6.2.4.3 Consideration on device Global Warm Reset
              4. 34.3.7.6.2.4.4 Booting Image Size
              5. 34.3.7.6.2.4.5 Booting Image Layout
          3. 34.3.7.6.3 Initialization and Detection
          4. 34.3.7.6.4 Read Sector Procedure
          5. 34.3.7.6.5 File System Handling
            1. 34.3.7.6.5.1 MBR and FAT File System
        7. 34.3.7.7 SATA Device Boot Operation
          1. 34.3.7.7.1 SATA Booting Overview
          2. 34.3.7.7.2 SATA Power-Up Initialization Sequence
          3. 34.3.7.7.3 System Conditions and Limitations for SATA Boot
          4. 34.3.7.7.4 SATA Read Sector Procedure in FAT Mode
      8. 34.3.8 Image Format
        1. 34.3.8.1 Overview
        2. 34.3.8.2 Configuration Header
          1. 34.3.8.2.1 CHSETTINGS Item
          2. 34.3.8.2.2 CHFLASH Item
          3. 34.3.8.2.3 CHMMCSD Item
          4. 34.3.8.2.4 CHQSPI Item
        3. 34.3.8.3 GP Header
        4. 34.3.8.4 Image Execution
      9. 34.3.9 Tracing
    4. 34.4 Services for HLOS Support
      1. 34.4.1 Hypervisor
      2. 34.4.2 Caches Maintenance
      3. 34.4.3 CP15 Registers
      4. 34.4.4 Wakeup Generator
      5. 34.4.5 Arm Timer
      6. 34.4.6 MReq Domain
  37. 35On-Chip Debug Support
    1. 35.1  Introduction
      1. 35.1.1 Key Features
    2. 35.2  Debug Interfaces
      1. 35.2.1 IEEE1149.1
      2. 35.2.2 Debug (Trace) Port
      3. 35.2.3 Trace Connector and Board Layout Considerations
    3. 35.3  Debugger Connection
      1. 35.3.1 ICEPick Module
      2. 35.3.2 ICEPick Boot Modes
        1. 35.3.2.1 Default Boot Mode
        2. 35.3.2.2 Wait-In-Reset
      3. 35.3.3 Dynamic TAP Insertion
        1. 35.3.3.1 ICEPick Secondary TAPs
    4. 35.4  Primary Debug Support
      1. 35.4.1 Processor Native Debug Support
        1. 35.4.1.1 Cortex-A15 Processor
        2. 35.4.1.2 Cortex-M4 Processor
        3. 35.4.1.3 DSP C66x
        4. 35.4.1.4 IVA Arm968
        5. 35.4.1.5 ARP32
        6. 35.4.1.6 5341
      2. 35.4.2 Cross-Triggering
        1. 35.4.2.1 SoC-Level Cross-Triggering
        2. 35.4.2.2 Cross-Triggering With External Device
      3. 35.4.3 Suspend
        1. 35.4.3.1 Debug Aware Peripherals and Host Processors
    5. 35.5  Real-Time Debug
      1. 35.5.1 Real-Time Debug Events
        1. 35.5.1.1 Emulation Interrupts
    6. 35.6  Power, Reset, and Clock Management Debug Support
      1. 35.6.1 Power and Clock Management
        1. 35.6.1.1 Power and Clock Control Override From Debugger
          1. 35.6.1.1.1 Debugger Directives
            1. 35.6.1.1.1.1 FORCEACTIVE Debugger Directive
            2. 35.6.1.1.1.2 INHIBITSLEEP Debugger Directive
          2. 35.6.1.1.2 Intrusive Debug Model
        2. 35.6.1.2 Debug Across Power Transition
          1. 35.6.1.2.1 Nonintrusive Debug Model
          2. 35.6.1.2.2 Debug Context Save and Restore
            1. 35.6.1.2.2.1 Debug Context Save
            2. 35.6.1.2.2.2 Debug Context Restore
      2. 35.6.2 Reset Management
        1. 35.6.2.1 Debugger Directives
          1. 35.6.2.1.1 Assert Reset
          2. 35.6.2.1.2 Block Reset
          3. 35.6.2.1.3 Wait-In-Reset
    7. 35.7  Performance Monitoring
      1. 35.7.1 MPU Subsystem Performance Monitoring
        1. 35.7.1.1 Performance Monitoring Unit
        2. 35.7.1.2 L2 Cache Controller
      2. 35.7.2 IPU Subsystem Performance Monitoring
        1. 35.7.2.1 Subsystem Counter Timer Module
        2. 35.7.2.2 Cache Events
      3. 35.7.3 DSP Subsystem Performance Monitoring
        1. 35.7.3.1 Advanced Event Triggering
      4. 35.7.4 EVE Subsystem Performance Monitoring
        1. 35.7.4.1 EVE Subsystem Counter Timer Module
        2. 35.7.4.2 EVE Subsystem SCTM Events
    8. 35.8  MPU Memory Adaptor (MPU_MA) Watchpoint
    9. 35.9  Processor Trace
      1. 35.9.1 Cortex-A15 Processor Trace
      2. 35.9.2 DSP Processor Trace
      3. 35.9.3 Trace Export
        1. 35.9.3.1 Trace Exported to External Trace Receiver
        2. 35.9.3.2 Trace Captured Into On-Chip Trace Buffer
        3. 35.9.3.3 Trace Exported Through USB
    10. 35.10 System Instrumentation
      1. 35.10.1  MIPI STM (CT_STM)
      2. 35.10.2  System Trace Export
        1. 35.10.2.1 CT_STM ATB Export
        2. 35.10.2.2 Trace Streams Interleaving
      3. 35.10.3  Software Instrumentation
        1. 35.10.3.1 MPU Software Instrumentation
        2. 35.10.3.2 SoC Software Instrumentation
      4. 35.10.4  OCP Watchpoint
        1. 35.10.4.1 OCP Target Traffic Monitoring
        2. 35.10.4.2 Messages Triggered from System Events
        3. 35.10.4.3 DMA Transfer Profiling
      5. 35.10.5  IVA Pipeline
      6. 35.10.6  EVE SMSET
      7. 35.10.7  L3 NOC Statistics Collector
        1. 35.10.7.1 L3 Target Load Monitoring
        2. 35.10.7.2 L3 Master Latency Monitoring
          1. 35.10.7.2.1  SC_LAT0 Configuration
          2. 35.10.7.2.2  SC_LAT1 Configuration
          3. 35.10.7.2.3  SC_LAT2 Configuration
          4. 35.10.7.2.4  SC_LAT3 Configuration
          5. 35.10.7.2.5  SC_LAT4 Configuration
          6. 35.10.7.2.6  SC_LAT5 Configuration
          7. 35.10.7.2.7  SC_LAT6 Configuration
          8. 35.10.7.2.8  SC_LAT7 Configuration
          9. 35.10.7.2.9  SC_LAT8 Configuration
          10. 35.10.7.2.10 Statistics Collector Alarm Mode
          11. 35.10.7.2.11 Statistics Collector Suspend Mode
      8. 35.10.8  PM Instrumentation
      9. 35.10.9  CM Instrumentation
      10. 35.10.10 Master-ID Encoding
        1. 35.10.10.1 Software Masters
        2. 35.10.10.2 Hardware Masters
    11. 35.11 Concurrent Debug Modes
    12. 35.12 DRM Register Manual
      1. 35.12.1 DRM Instance Summary
      2. 35.12.2 DRM Registers
        1. 35.12.2.1 DRM Register Summary
        2. 35.12.2.2 DRM Register Description
  38. 36Revision History

20.7 IODELAYCONFIG Module Register Manual

20.7.1 IODELAYCONFIG Module Instance Summary

Table 20-918 IODELAYCONFIG Module Instance Summary
Module NameModule Base AddressSize
IODELAYCONFIG0x4844 A0004KiB

20.7.2 IODELAYCONFIG Registers

20.7.3 IODELAYCONFIG Register Summary

Table 20-919 IODELAYCONFIG Registers Mapping Summary
Register NameTypeRegister Width (Bits)Address OffsetIODELAYCONFIG Base Address
RESERVEDR320x0000 00000x4844 A000
RESERVEDR320x0000 00040x4844 A004
RESERVEDR320x0000 00080x4844 A008
CONFIG_REG_0RW320x0000 000C0x4844 A00C
RESERVEDR320x0000 00100x4844 A010
CONFIG_REG_2RW320x0000 00140x4844 A014
CONFIG_REG_3RW320x0000 00180x4844 A018
CONFIG_REG_4RW320x0000 001C0x4844 A01C
RESERVEDR320x0000 00200x4844 A020
RESERVEDR320x0000 00240x4844 A024
RESERVEDR320x0000 00280x4844 A028
CONFIG_REG_8RW320x0000 002C0x4844 A02C
CFG_RMII_MHZ_50_CLK_INRW320x0000 00300x4844 A030
CFG_RMII_MHZ_50_CLK_OENRW320x0000 00340x4844 A034
CFG_RMII_MHZ_50_CLK_OUTRW320x0000 00380x4844 A038
CFG_WAKEUP0_INRW320x0000 003C0x4844 A03C
CFG_WAKEUP0_OENRW320x0000 00400x4844 A040
CFG_WAKEUP0_OUTRW320x0000 00440x4844 A044
CFG_WAKEUP1_INRW320x0000 00480x4844 A048
CFG_WAKEUP1_OENRW320x0000 004C0x4844 A04C
CFG_WAKEUP1_OUTRW320x0000 00500x4844 A050
CFG_WAKEUP2_INRW320x0000 00540x4844 A054
CFG_WAKEUP2_OENRW320x0000 00580x4844 A058
CFG_WAKEUP2_OUTRW320x0000 005C0x4844 A05C
CFG_WAKEUP3_INRW320x0000 00600x4844 A060
CFG_WAKEUP3_OENRW320x0000 00640x4844 A064
CFG_WAKEUP3_OUTRW320x0000 00680x4844 A068
CFG_DCAN1_RX_INRW320x0000 006C0x4844 A06C
CFG_DCAN1_RX_OENRW320x0000 00700x4844 A070
CFG_DCAN1_RX_OUTRW320x0000 00740x4844 A074
CFG_DCAN1_TX_INRW320x0000 00780x4844 A078
CFG_DCAN1_TX_OENRW320x0000 007C0x4844 A07C
CFG_DCAN1_TX_OUTRW320x0000 00800x4844 A080
CFG_DCAN2_RX_INRW320x0000 00840x4844 A084
CFG_DCAN2_RX_OENRW320x0000 00880x4844 A088
CFG_DCAN2_RX_OUTRW320x0000 008C0x4844 A08C
CFG_DCAN2_TX_INRW320x0000 00900x4844 A090
CFG_DCAN2_TX_OENRW320x0000 00940x4844 A094
CFG_DCAN2_TX_OUTRW320x0000 00980x4844 A098
CFG_EMU0_INRW320x0000 009C0x4844 A09C
CFG_EMU0_OENRW320x0000 00A00x4844 A0A0
CFG_EMU0_OUTRW320x0000 00A40x4844 A0A4
CFG_EMU1_INRW320x0000 00A80x4844 A0A8
CFG_EMU1_OENRW320x0000 00AC0x4844 A0AC
CFG_EMU1_OUTRW320x0000 00B00x4844 A0B0
CFG_EMU2_INRW320x0000 00B40x4844 A0B4
CFG_EMU2_OENRW320x0000 00B80x4844 A0B8
CFG_EMU2_OUTRW320x0000 00BC0x4844 A0BC
CFG_EMU3_INRW320x0000 00C00x4844 A0C0
CFG_EMU3_OENRW320x0000 00C40x4844 A0C4
CFG_EMU3_OUTRW320x0000 00C80x4844 A0C8
CFG_EMU4_INRW320x0000 00CC0x4844 A0CC
CFG_EMU4_OENRW320x0000 00D00x4844 A0D0
CFG_EMU4_OUTRW320x0000 00D40x4844 A0D4
CFG_GPIO6_10_INRW320x0000 00D80x4844 A0D8
CFG_GPIO6_10_OENRW320x0000 00DC0x4844 A0DC
CFG_GPIO6_10_OUTRW320x0000 00E00x4844 A0E0
CFG_GPIO6_11_INRW320x0000 00E40x4844 A0E4
CFG_GPIO6_11_OENRW320x0000 00E80x4844 A0E8
CFG_GPIO6_11_OUTRW320x0000 00EC0x4844 A0EC
CFG_GPIO6_14_INRW320x0000 00F00x4844 A0F0
CFG_GPIO6_14_OENRW320x0000 00F40x4844 A0F4
CFG_GPIO6_14_OUTRW320x0000 00F80x4844 A0F8
CFG_GPIO6_15_INRW320x0000 00FC0x4844 A0FC
CFG_GPIO6_15_OENRW320x0000 01000x4844 A100
CFG_GPIO6_15_OUTRW320x0000 01040x4844 A104
CFG_GPIO6_16_INRW320x0000 01080x4844 A108
CFG_GPIO6_16_OENRW320x0000 010C0x4844 A10C
CFG_GPIO6_16_OUTRW320x0000 01100x4844 A110
CFG_GPMC_A0_INRW320x0000 01140x4844 A114
CFG_GPMC_A0_OENRW320x0000 01180x4844 A118
CFG_GPMC_A0_OUTRW320x0000 011C0x4844 A11C
CFG_GPMC_A10_INRW320x0000 01200x4844 A120
CFG_GPMC_A10_OENRW320x0000 01240x4844 A124
CFG_GPMC_A10_OUTRW320x0000 01280x4844 A128
CFG_GPMC_A11_INRW320x0000 012C0x4844 A12C
CFG_GPMC_A11_OENRW320x0000 01300x4844 A130
CFG_GPMC_A11_OUTRW320x0000 01340x4844 A134
CFG_GPMC_A12_INRW320x0000 01380x4844 A138
CFG_GPMC_A12_OENRW320x0000 013C0x4844 A13C
CFG_GPMC_A12_OUTRW320x0000 01400x4844 A140
CFG_GPMC_A13_INRW320x0000 01440x4844 A144
CFG_GPMC_A13_OENRW320x0000 01480x4844 A148
CFG_GPMC_A13_OUTRW320x0000 014C0x4844 A14C
CFG_GPMC_A14_INRW320x0000 01500x4844 A150
CFG_GPMC_A14_OENRW320x0000 01540x4844 A154
CFG_GPMC_A14_OUTRW320x0000 01580x4844 A158
CFG_GPMC_A15_INRW320x0000 015C0x4844 A15C
CFG_GPMC_A15_OENRW320x0000 01600x4844 A160
CFG_GPMC_A15_OUTRW320x0000 01640x4844 A164
CFG_GPMC_A16_INRW320x0000 01680x4844 A168
CFG_GPMC_A16_OENRW320x0000 016C0x4844 A16C
CFG_GPMC_A16_OUTRW320x0000 01700x4844 A170
CFG_GPMC_A17_INRW320x0000 01740x4844 A174
CFG_GPMC_A17_OENRW320x0000 01780x4844 A178
CFG_GPMC_A17_OUTRW320x0000 017C0x4844 A17C
CFG_GPMC_A18_INRW320x0000 01800x4844 A180
CFG_GPMC_A18_OENRW320x0000 01840x4844 A184
CFG_GPMC_A18_OUTRW320x0000 01880x4844 A188
CFG_GPMC_A19_INRW320x0000 018C0x4844 A18C
CFG_GPMC_A19_OENRW320x0000 01900x4844 A190
CFG_GPMC_A19_OUTRW320x0000 01940x4844 A194
CFG_GPMC_A1_INRW320x0000 01980x4844 A198
CFG_GPMC_A1_OENRW320x0000 019C0x4844 A19C
CFG_GPMC_A1_OUTRW320x0000 01A00x4844 A1A0
CFG_GPMC_A20_INRW320x0000 01A40x4844 A1A4
CFG_GPMC_A20_OENRW320x0000 01A80x4844 A1A8
CFG_GPMC_A20_OUTRW320x0000 01AC0x4844 A1AC
CFG_GPMC_A21_INRW320x0000 01B00x4844 A1B0
CFG_GPMC_A21_OENRW320x0000 01B40x4844 A1B4
CFG_GPMC_A21_OUTRW320x0000 01B80x4844 A1B8
CFG_GPMC_A22_INRW320x0000 01BC0x4844 A1BC
CFG_GPMC_A22_OENRW320x0000 01C00x4844 A1C0
CFG_GPMC_A22_OUTRW320x0000 01C40x4844 A1C4
CFG_GPMC_A23_INRW320x0000 01C80x4844 A1C8
CFG_GPMC_A23_OENRW320x0000 01CC0x4844 A1CC
CFG_GPMC_A23_OUTRW320x0000 01D00x4844 A1D0
CFG_GPMC_A24_INRW320x0000 01D40x4844 A1D4
CFG_GPMC_A24_OENRW320x0000 01D80x4844 A1D8
CFG_GPMC_A24_OUTRW320x0000 01DC0x4844 A1DC
CFG_GPMC_A25_INRW320x0000 01E00x4844 A1E0
CFG_GPMC_A25_OENRW320x0000 01E40x4844 A1E4
CFG_GPMC_A25_OUTRW320x0000 01E80x4844 A1E8
CFG_GPMC_A26_INRW320x0000 01EC0x4844 A1EC
CFG_GPMC_A26_OENRW320x0000 01F00x4844 A1F0
CFG_GPMC_A26_OUTRW320x0000 01F40x4844 A1F4
CFG_GPMC_A27_INRW320x0000 01F80x4844 A1F8
CFG_GPMC_A27_OENRW320x0000 01FC0x4844 A1FC
CFG_GPMC_A27_OUTRW320x0000 02000x4844 A200
CFG_GPMC_A2_INRW320x0000 02040x4844 A204
CFG_GPMC_A2_OENRW320x0000 02080x4844 A208
CFG_GPMC_A2_OUTRW320x0000 020C0x4844 A20C
CFG_GPMC_A3_INRW320x0000 02100x4844 A210
CFG_GPMC_A3_OENRW320x0000 02140x4844 A214
CFG_GPMC_A3_OUTRW320x0000 02180x4844 A218
CFG_GPMC_A4_INRW320x0000 021C0x4844 A21C
CFG_GPMC_A4_OENRW320x0000 02200x4844 A220
CFG_GPMC_A4_OUTRW320x0000 02240x4844 A224
CFG_GPMC_A5_INRW320x0000 02280x4844 A228
CFG_GPMC_A5_OENRW320x0000 022C0x4844 A22C
CFG_GPMC_A5_OUTRW320x0000 02300x4844 A230
CFG_GPMC_A6_INRW320x0000 02340x4844 A234
CFG_GPMC_A6_OENRW320x0000 02380x4844 A238
CFG_GPMC_A6_OUTRW320x0000 023C0x4844 A23C
CFG_GPMC_A7_INRW320x0000 02400x4844 A240
CFG_GPMC_A7_OENRW320x0000 02440x4844 A244
CFG_GPMC_A7_OUTRW320x0000 02480x4844 A248
CFG_GPMC_A8_INRW320x0000 024C0x4844 A24C
CFG_GPMC_A8_OENRW320x0000 02500x4844 A250
CFG_GPMC_A8_OUTRW320x0000 02540x4844 A254
CFG_GPMC_A9_INRW320x0000 02580x4844 A258
CFG_GPMC_A9_OENRW320x0000 025C0x4844 A25C
CFG_GPMC_A9_OUTRW320x0000 02600x4844 A260
CFG_GPMC_AD0_INRW320x0000 02640x4844 A264
CFG_GPMC_AD0_OENRW320x0000 02680x4844 A268
CFG_GPMC_AD0_OUTRW320x0000 026C0x4844 A26C
CFG_GPMC_AD10_INRW320x0000 02700x4844 A270
CFG_GPMC_AD10_OENRW320x0000 02740x4844 A274
CFG_GPMC_AD10_OUTRW320x0000 02780x4844 A278
CFG_GPMC_AD11_INRW320x0000 027C0x4844 A27C
CFG_GPMC_AD11_OENRW320x0000 02800x4844 A280
CFG_GPMC_AD11_OUTRW320x0000 02840x4844 A284
CFG_GPMC_AD12_INRW320x0000 02880x4844 A288
CFG_GPMC_AD12_OENRW320x0000 028C0x4844 A28C
CFG_GPMC_AD12_OUTRW320x0000 02900x4844 A290
CFG_GPMC_AD13_INRW320x0000 02940x4844 A294
CFG_GPMC_AD13_OENRW320x0000 02980x4844 A298
CFG_GPMC_AD13_OUTRW320x0000 029C0x4844 A29C
CFG_GPMC_AD14_INRW320x0000 02A00x4844 A2A0
CFG_GPMC_AD14_OENRW320x0000 02A40x4844 A2A4
CFG_GPMC_AD14_OUTRW320x0000 02A80x4844 A2A8
CFG_GPMC_AD15_INRW320x0000 02AC0x4844 A2AC
CFG_GPMC_AD15_OENRW320x0000 02B00x4844 A2B0
CFG_GPMC_AD15_OUTRW320x0000 02B40x4844 A2B4
CFG_GPMC_AD1_INRW320x0000 02B80x4844 A2B8
CFG_GPMC_AD1_OENRW320x0000 02BC0x4844 A2BC
CFG_GPMC_AD1_OUTRW320x0000 02C00x4844 A2C0
CFG_GPMC_AD2_INRW320x0000 02C40x4844 A2C4
CFG_GPMC_AD2_OENRW320x0000 02C80x4844 A2C8
CFG_GPMC_AD2_OUTRW320x0000 02CC0x4844 A2CC
CFG_GPMC_AD3_INRW320x0000 02D00x4844 A2D0
CFG_GPMC_AD3_OENRW320x0000 02D40x4844 A2D4
CFG_GPMC_AD3_OUTRW320x0000 02D80x4844 A2D8
CFG_GPMC_AD4_INRW320x0000 02DC0x4844 A2DC
CFG_GPMC_AD4_OENRW320x0000 02E00x4844 A2E0
CFG_GPMC_AD4_OUTRW320x0000 02E40x4844 A2E4
CFG_GPMC_AD5_INRW320x0000 02E80x4844 A2E8
CFG_GPMC_AD5_OENRW320x0000 02EC0x4844 A2EC
CFG_GPMC_AD5_OUTRW320x0000 02F00x4844 A2F0
CFG_GPMC_AD6_INRW320x0000 02F40x4844 A2F4
CFG_GPMC_AD6_OENRW320x0000 02F80x4844 A2F8
CFG_GPMC_AD6_OUTRW320x0000 02FC0x4844 A2FC
CFG_GPMC_AD7_INRW320x0000 03000x4844 A300
CFG_GPMC_AD7_OENRW320x0000 03040x4844 A304
CFG_GPMC_AD7_OUTRW320x0000 03080x4844 A308
CFG_GPMC_AD8_INRW320x0000 030C0x4844 A30C
CFG_GPMC_AD8_OENRW320x0000 03100x4844 A310
CFG_GPMC_AD8_OUTRW320x0000 03140x4844 A314
CFG_GPMC_AD9_INRW320x0000 03180x4844 A318
CFG_GPMC_AD9_OENRW320x0000 031C0x4844 A31C
CFG_GPMC_AD9_OUTRW320x0000 03200x4844 A320
CFG_GPMC_ADVN_ALE_INRW320x0000 03240x4844 A324
CFG_GPMC_ADVN_ALE_OENRW320x0000 03280x4844 A328
CFG_GPMC_ADVN_ALE_OUTRW320x0000 032C0x4844 A32C
CFG_GPMC_BEN0_INRW320x0000 03300x4844 A330
CFG_GPMC_BEN0_OENRW320x0000 03340x4844 A334
CFG_GPMC_BEN0_OUTRW320x0000 03380x4844 A338
CFG_GPMC_BEN1_INRW320x0000 033C0x4844 A33C
CFG_GPMC_BEN1_OENRW320x0000 03400x4844 A340
CFG_GPMC_BEN1_OUTRW320x0000 03440x4844 A344
CFG_GPMC_CLK_INRW320x0000 03480x4844 A348
CFG_GPMC_CLK_OENRW320x0000 034C0x4844 A34C
CFG_GPMC_CLK_OUTRW320x0000 03500x4844 A350
CFG_GPMC_CS0_INRW320x0000 03540x4844 A354
CFG_GPMC_CS0_OENRW320x0000 03580x4844 A358
CFG_GPMC_CS0_OUTRW320x0000 035C0x4844 A35C
CFG_GPMC_CS1_INRW320x0000 03600x4844 A360
CFG_GPMC_CS1_OENRW320x0000 03640x4844 A364
CFG_GPMC_CS1_OUTRW320x0000 03680x4844 A368
CFG_GPMC_CS2_INRW320x0000 036C0x4844 A36C
CFG_GPMC_CS2_OENRW320x0000 03700x4844 A370
CFG_GPMC_CS2_OUTRW320x0000 03740x4844 A374
CFG_GPMC_CS3_INRW320x0000 03780x4844 A378
CFG_GPMC_CS3_OENRW320x0000 037C0x4844 A37C
CFG_GPMC_CS3_OUTRW320x0000 03800x4844 A380
CFG_GPMC_OEN_REN_INRW320x0000 03840x4844 A384
CFG_GPMC_OEN_REN_OENRW320x0000 03880x4844 A388
CFG_GPMC_OEN_REN_OUTRW320x0000 038C0x4844 A38C
CFG_GPMC_WAIT0_INRW320x0000 03900x4844 A390
CFG_GPMC_WAIT0_OENRW320x0000 03940x4844 A394
CFG_GPMC_WAIT0_OUTRW320x0000 03980x4844 A398
CFG_GPMC_WEN_INRW320x0000 039C0x4844 A39C
CFG_GPMC_WEN_OENRW320x0000 03A00x4844 A3A0
CFG_GPMC_WEN_OUTRW320x0000 03A40x4844 A3A4
CFG_MCASP1_ACLKR_INRW320x0000 03A80x4844 A3A8
CFG_MCASP1_ACLKR_OENRW320x0000 03AC0x4844 A3AC
CFG_MCASP1_ACLKR_OUTRW320x0000 03B00x4844 A3B0
CFG_MCASP1_ACLKX_INRW320x0000 03B40x4844 A3B4
CFG_MCASP1_ACLKX_OENRW320x0000 03B80x4844 A3B8
CFG_MCASP1_ACLKX_OUTRW320x0000 03BC0x4844 A3BC
CFG_MCASP1_AXR0_INRW320x0000 03C00x4844 A3C0
CFG_MCASP1_AXR0_OENRW320x0000 03C40x4844 A3C4
CFG_MCASP1_AXR0_OUTRW320x0000 03C80x4844 A3C8
CFG_MCASP1_AXR10_INRW320x0000 03CC0x4844 A3CC
CFG_MCASP1_AXR10_OENRW320x0000 03D00x4844 A3D0
CFG_MCASP1_AXR10_OUTRW320x0000 03D40x4844 A3D4
CFG_MCASP1_AXR11_INRW320x0000 03D80x4844 A3D8
CFG_MCASP1_AXR11_OENRW320x0000 03DC0x4844 A3DC
CFG_MCASP1_AXR11_OUTRW320x0000 03E00x4844 A3E0
CFG_MCASP1_AXR12_INRW320x0000 03E40x4844 A3E4
CFG_MCASP1_AXR12_OENRW320x0000 03E80x4844 A3E8
CFG_MCASP1_AXR12_OUTRW320x0000 03EC0x4844 A3EC
CFG_MCASP1_AXR13_INRW320x0000 03F00x4844 A3F0
CFG_MCASP1_AXR13_OENRW320x0000 03F40x4844 A3F4
CFG_MCASP1_AXR13_OUTRW320x0000 03F80x4844 A3F8
CFG_MCASP1_AXR14_INRW320x0000 03FC0x4844 A3FC
CFG_MCASP1_AXR14_OENRW320x0000 04000x4844 A400
CFG_MCASP1_AXR14_OUTRW320x0000 04040x4844 A404
CFG_MCASP1_AXR15_INRW320x0000 04080x4844 A408
CFG_MCASP1_AXR15_OENRW320x0000 040C0x4844 A40C
CFG_MCASP1_AXR15_OUTRW320x0000 04100x4844 A410
CFG_MCASP1_AXR1_INRW320x0000 04140x4844 A414
CFG_MCASP1_AXR1_OENRW320x0000 04180x4844 A418
CFG_MCASP1_AXR1_OUTRW320x0000 041C0x4844 A41C
CFG_MCASP1_AXR2_INRW320x0000 04200x4844 A420
CFG_MCASP1_AXR2_OENRW320x0000 04240x4844 A424
CFG_MCASP1_AXR2_OUTRW320x0000 04280x4844 A428
CFG_MCASP1_AXR3_INRW320x0000 042C0x4844 A42C
CFG_MCASP1_AXR3_OENRW320x0000 04300x4844 A430
CFG_MCASP1_AXR3_OUTRW320x0000 04340x4844 A434
CFG_MCASP1_AXR4_INRW320x0000 04380x4844 A438
CFG_MCASP1_AXR4_OENRW320x0000 043C0x4844 A43C
CFG_MCASP1_AXR4_OUTRW320x0000 04400x4844 A440
CFG_MCASP1_AXR5_INRW320x0000 04440x4844 A444
CFG_MCASP1_AXR5_OENRW320x0000 04480x4844 A448
CFG_MCASP1_AXR5_OUTRW320x0000 044C0x4844 A44C
CFG_MCASP1_AXR6_INRW320x0000 04500x4844 A450
CFG_MCASP1_AXR6_OENRW320x0000 04540x4844 A454
CFG_MCASP1_AXR6_OUTRW320x0000 04580x4844 A458
CFG_MCASP1_AXR7_INRW320x0000 045C0x4844 A45C
CFG_MCASP1_AXR7_OENRW320x0000 04600x4844 A460
CFG_MCASP1_AXR7_OUTRW320x0000 04640x4844 A464
CFG_MCASP1_AXR8_INRW320x0000 04680x4844 A468
CFG_MCASP1_AXR8_OENRW320x0000 046C0x4844 A46C
CFG_MCASP1_AXR8_OUTRW320x0000 04700x4844 A470
CFG_MCASP1_AXR9_INRW320x0000 04740x4844 A474
CFG_MCASP1_AXR9_OENRW320x0000 04780x4844 A478
CFG_MCASP1_AXR9_OUTRW320x0000 047C0x4844 A47C
CFG_MCASP1_FSR_INRW320x0000 04800x4844 A480
CFG_MCASP1_FSR_OENRW320x0000 04840x4844 A484
CFG_MCASP1_FSR_OUTRW320x0000 04880x4844 A488
CFG_MCASP1_FSX_INRW320x0000 048C0x4844 A48C
CFG_MCASP1_FSX_OENRW320x0000 04900x4844 A490
CFG_MCASP1_FSX_OUTRW320x0000 04940x4844 A494
CFG_MCASP2_ACLKR_INRW320x0000 04980x4844 A498
CFG_MCASP2_ACLKR_OENRW320x0000 049C0x4844 A49C
CFG_MCASP2_ACLKR_OUTRW320x0000 04A00x4844 A4A0
CFG_MCASP2_ACLKX_INRW320x0000 04A40x4844 A4A4
CFG_MCASP2_ACLKX_OENRW320x0000 04A80x4844 A4A8
CFG_MCASP2_ACLKX_OUTRW320x0000 04AC0x4844 A4AC
CFG_MCASP2_AXR0_INRW320x0000 04B00x4844 A4B0
CFG_MCASP2_AXR0_OENRW320x0000 04B40x4844 A4B4
CFG_MCASP2_AXR0_OUTRW320x0000 04B80x4844 A4B8
CFG_MCASP2_AXR1_INRW320x0000 04BC0x4844 A4BC
CFG_MCASP2_AXR1_OENRW320x0000 04C00x4844 A4C0
CFG_MCASP2_AXR1_OUTRW320x0000 04C40x4844 A4C4
CFG_MCASP2_AXR2_INRW320x0000 04C80x4844 A4C8
CFG_MCASP2_AXR2_OENRW320x0000 04CC0x4844 A4CC
CFG_MCASP2_AXR2_OUTRW320x0000 04D00x4844 A4D0
CFG_MCASP2_AXR3_INRW320x0000 04D40x4844 A4D4
CFG_MCASP2_AXR3_OENRW320x0000 04D80x4844 A4D8
CFG_MCASP2_AXR3_OUTRW320x0000 04DC0x4844 A4DC
CFG_MCASP2_AXR4_INRW320x0000 04E00x4844 A4E0
CFG_MCASP2_AXR4_OENRW320x0000 04E40x4844 A4E4
CFG_MCASP2_AXR4_OUTRW320x0000 04E80x4844 A4E8
CFG_MCASP2_AXR5_INRW320x0000 04EC0x4844 A4EC
CFG_MCASP2_AXR5_OENRW320x0000 04F00x4844 A4F0
CFG_MCASP2_AXR5_OUTRW320x0000 04F40x4844 A4F4
CFG_MCASP2_AXR6_INRW320x0000 04F80x4844 A4F8
CFG_MCASP2_AXR6_OENRW320x0000 04FC0x4844 A4FC
CFG_MCASP2_AXR6_OUTRW320x0000 05000x4844 A500
CFG_MCASP2_AXR7_INRW320x0000 05040x4844 A504
CFG_MCASP2_AXR7_OENRW320x0000 05080x4844 A508
CFG_MCASP2_AXR7_OUTRW320x0000 050C0x4844 A50C
CFG_MCASP2_FSR_INRW320x0000 05100x4844 A510
CFG_MCASP2_FSR_OENRW320x0000 05140x4844 A514
CFG_MCASP2_FSR_OUTRW320x0000 05180x4844 A518
CFG_MCASP2_FSX_INRW320x0000 051C0x4844 A51C
CFG_MCASP2_FSX_OENRW320x0000 05200x4844 A520
CFG_MCASP2_FSX_OUTRW320x0000 05240x4844 A524
CFG_MCASP3_ACLKX_INRW320x0000 05280x4844 A528
CFG_MCASP3_ACLKX_OENRW320x0000 052C0x4844 A52C
CFG_MCASP3_ACLKX_OUTRW320x0000 05300x4844 A530
CFG_MCASP3_AXR0_INRW320x0000 05340x4844 A534
CFG_MCASP3_AXR0_OENRW320x0000 05380x4844 A538
CFG_MCASP3_AXR0_OUTRW320x0000 053C0x4844 A53C
CFG_MCASP3_AXR1_INRW320x0000 05400x4844 A540
CFG_MCASP3_AXR1_OENRW320x0000 05440x4844 A544
CFG_MCASP3_AXR1_OUTRW320x0000 05480x4844 A548
CFG_MCASP3_FSX_INRW320x0000 054C0x4844 A54C
CFG_MCASP3_FSX_OENRW320x0000 05500x4844 A550
CFG_MCASP3_FSX_OUTRW320x0000 05540x4844 A554
CFG_MCASP4_ACLKX_INRW320x0000 05580x4844 A558
CFG_MCASP4_ACLKX_OENRW320x0000 055C0x4844 A55C
CFG_MCASP4_ACLKX_OUTRW320x0000 05600x4844 A560
CFG_MCASP4_AXR0_INRW320x0000 05640x4844 A564
CFG_MCASP4_AXR0_OENRW320x0000 05680x4844 A568
CFG_MCASP4_AXR0_OUTRW320x0000 056C0x4844 A56C
CFG_MCASP4_AXR1_INRW320x0000 05700x4844 A570
CFG_MCASP4_AXR1_OENRW320x0000 05740x4844 A574
CFG_MCASP4_AXR1_OUTRW320x0000 05780x4844 A578
CFG_MCASP4_FSX_INRW320x0000 057C0x4844 A57C
CFG_MCASP4_FSX_OENRW320x0000 05800x4844 A580
CFG_MCASP4_FSX_OUTRW320x0000 05840x4844 A584
CFG_MCASP5_ACLKX_INRW320x0000 05880x4844 A588
CFG_MCASP5_ACLKX_OENRW320x0000 058C0x4844 A58C
CFG_MCASP5_ACLKX_OUTRW320x0000 05900x4844 A590
CFG_MCASP5_AXR0_INRW320x0000 05940x4844 A594
CFG_MCASP5_AXR0_OENRW320x0000 05980x4844 A598
CFG_MCASP5_AXR0_OUTRW320x0000 059C0x4844 A59C
CFG_MCASP5_AXR1_INRW320x0000 05A00x4844 A5A0
CFG_MCASP5_AXR1_OENRW320x0000 05A40x4844 A5A4
CFG_MCASP5_AXR1_OUTRW320x0000 05A80x4844 A5A8
CFG_MCASP5_FSX_INRW320x0000 05AC0x4844 A5AC
CFG_MCASP5_FSX_OENRW320x0000 05B00x4844 A5B0
CFG_MCASP5_FSX_OUTRW320x0000 05B40x4844 A5B4
CFG_MDIO_D_INRW320x0000 05B80x4844 A5B8
CFG_MDIO_D_OENRW320x0000 05BC0x4844 A5BC
CFG_MDIO_D_OUTRW320x0000 05C00x4844 A5C0
CFG_MDIO_MCLK_INRW320x0000 05C40x4844 A5C4
CFG_MDIO_MCLK_OENRW320x0000 05C80x4844 A5C8
CFG_MDIO_MCLK_OUTRW320x0000 05CC0x4844 A5CC
CFG_MLBP_CLK_N_INRW320x0000 05D00x4844 A5D0
CFG_MLBP_CLK_N_OENRW320x0000 05D40x4844 A5D4
CFG_MLBP_CLK_N_OUTRW320x0000 05D80x4844 A5D8
CFG_MLBP_CLK_P_INRW320x0000 05DC0x4844 A5DC
CFG_MLBP_CLK_P_OENRW320x0000 05E00x4844 A5E0
CFG_MLBP_CLK_P_OUTRW320x0000 05E40x4844 A5E4
CFG_MLBP_DAT_N_INRW320x0000 05E80x4844 A5E8
CFG_MLBP_DAT_N_OENRW320x0000 05EC0x4844 A5EC
CFG_MLBP_DAT_N_OUTRW320x0000 05F00x4844 A5F0
CFG_MLBP_DAT_P_INRW320x0000 05F40x4844 A5F4
CFG_MLBP_DAT_P_OENRW320x0000 05F80x4844 A5F8
CFG_MLBP_DAT_P_OUTRW320x0000 05FC0x4844 A5FC
CFG_MLBP_SIG_N_INRW320x0000 06000x4844 A600
CFG_MLBP_SIG_N_OENRW320x0000 06040x4844 A604
CFG_MLBP_SIG_N_OUTRW320x0000 06080x4844 A608
CFG_MLBP_SIG_P_INRW320x0000 060C0x4844 A60C
CFG_MLBP_SIG_P_OENRW320x0000 06100x4844 A610
CFG_MLBP_SIG_P_OUTRW320x0000 06140x4844 A614
CFG_MMC1_CLK_INRW320x0000 06180x4844 A618
CFG_MMC1_CLK_OENRW320x0000 061C0x4844 A61C
CFG_MMC1_CLK_OUTRW320x0000 06200x4844 A620
CFG_MMC1_CMD_INRW320x0000 06240x4844 A624
CFG_MMC1_CMD_OENRW320x0000 06280x4844 A628
CFG_MMC1_CMD_OUTRW320x0000 062C0x4844 A62C
CFG_MMC1_DAT0_INRW320x0000 06300x4844 A630
CFG_MMC1_DAT0_OENRW320x0000 06340x4844 A634
CFG_MMC1_DAT0_OUTRW320x0000 06380x4844 A638
CFG_MMC1_DAT1_INRW320x0000 063C0x4844 A63C
CFG_MMC1_DAT1_OENRW320x0000 06400x4844 A640
CFG_MMC1_DAT1_OUTRW320x0000 06440x4844 A644
CFG_MMC1_DAT2_INRW320x0000 06480x4844 A648
CFG_MMC1_DAT2_OENRW320x0000 064C0x4844 A64C
CFG_MMC1_DAT2_OUTRW320x0000 06500x4844 A650
CFG_MMC1_DAT3_INRW320x0000 06540x4844 A654
CFG_MMC1_DAT3_OENRW320x0000 06580x4844 A658
CFG_MMC1_DAT3_OUTRW320x0000 065C0x4844 A65C
CFG_MMC1_SDCD_INRW320x0000 06600x4844 A660
CFG_MMC1_SDCD_OENRW320x0000 06640x4844 A664
CFG_MMC1_SDCD_OUTRW320x0000 06680x4844 A668
CFG_MMC1_SDWP_INRW320x0000 066C0x4844 A66C
CFG_MMC1_SDWP_OENRW320x0000 06700x4844 A670
CFG_MMC1_SDWP_OUTRW320x0000 06740x4844 A674
CFG_MMC3_CLK_INRW320x0000 06780x4844 A678
CFG_MMC3_CLK_OENRW320x0000 067C0x4844 A67C
CFG_MMC3_CLK_OUTRW320x0000 06800x4844 A680
CFG_MMC3_CMD_INRW320x0000 06840x4844 A684
CFG_MMC3_CMD_OENRW320x0000 06880x4844 A688
CFG_MMC3_CMD_OUTRW320x0000 068C0x4844 A68C
CFG_MMC3_DAT0_INRW320x0000 06900x4844 A690
CFG_MMC3_DAT0_OENRW320x0000 06940x4844 A694
CFG_MMC3_DAT0_OUTRW320x0000 06980x4844 A698
CFG_MMC3_DAT1_INRW320x0000 069C0x4844 A69C
CFG_MMC3_DAT1_OENRW320x0000 06A00x4844 A6A0
CFG_MMC3_DAT1_OUTRW320x0000 06A40x4844 A6A4
CFG_MMC3_DAT2_INRW320x0000 06A80x4844 A6A8
CFG_MMC3_DAT2_OENRW320x0000 06AC0x4844 A6AC
CFG_MMC3_DAT2_OUTRW320x0000 06B00x4844 A6B0
CFG_MMC3_DAT3_INRW320x0000 06B40x4844 A6B4
CFG_MMC3_DAT3_OENRW320x0000 06B80x4844 A6B8
CFG_MMC3_DAT3_OUTRW320x0000 06BC0x4844 A6BC
CFG_MMC3_DAT4_INRW320x0000 06C00x4844 A6C0
CFG_MMC3_DAT4_OENRW320x0000 06C40x4844 A6C4
CFG_MMC3_DAT4_OUTRW320x0000 06C80x4844 A6C8
CFG_MMC3_DAT5_INRW320x0000 06CC0x4844 A6CC
CFG_MMC3_DAT5_OENRW320x0000 06D00x4844 A6D0
CFG_MMC3_DAT5_OUTRW320x0000 06D40x4844 A6D4
CFG_MMC3_DAT6_INRW320x0000 06D80x4844 A6D8
CFG_MMC3_DAT6_OENRW320x0000 06DC0x4844 A6DC
CFG_MMC3_DAT6_OUTRW320x0000 06E00x4844 A6E0
CFG_MMC3_DAT7_INRW320x0000 06E40x4844 A6E4
CFG_MMC3_DAT7_OENRW320x0000 06E80x4844 A6E8
CFG_MMC3_DAT7_OUTRW320x0000 06EC0x4844 A6EC
CFG_RGMII0_RXC_INRW320x0000 06F00x4844 A6F0
CFG_RGMII0_RXC_OENRW320x0000 06F40x4844 A6F4
CFG_RGMII0_RXC_OUTRW320x0000 06F80x4844 A6F8
CFG_RGMII0_RXCTL_INRW320x0000 06FC0x4844 A6FC
CFG_RGMII0_RXCTL_OENRW320x0000 07000x4844 A700
CFG_RGMII0_RXCTL_OUTRW320x0000 07040x4844 A704
CFG_RGMII0_RXD0_INRW320x0000 07080x4844 A708
CFG_RGMII0_RXD0_OENRW320x0000 070C0x4844 A70C
CFG_RGMII0_RXD0_OUTRW320x0000 07100x4844 A710
CFG_RGMII0_RXD1_INRW320x0000 07140x4844 A714
CFG_RGMII0_RXD1_OENRW320x0000 07180x4844 A718
CFG_RGMII0_RXD1_OUTRW320x0000 071C0x4844 A71C
CFG_RGMII0_RXD2_INRW320x0000 07200x4844 A720
CFG_RGMII0_RXD2_OENRW320x0000 07240x4844 A724
CFG_RGMII0_RXD2_OUTRW320x0000 07280x4844 A728
CFG_RGMII0_RXD3_INRW320x0000 072C0x4844 A72C
CFG_RGMII0_RXD3_OENRW320x0000 07300x4844 A730
CFG_RGMII0_RXD3_OUTRW320x0000 07340x4844 A734
CFG_RGMII0_TXC_INRW320x0000 07380x4844 A738
CFG_RGMII0_TXC_OENRW320x0000 073C0x4844 A73C
CFG_RGMII0_TXC_OUTRW320x0000 07400x4844 A740
CFG_RGMII0_TXCTL_INRW320x0000 07440x4844 A744
CFG_RGMII0_TXCTL_OENRW320x0000 07480x4844 A748
CFG_RGMII0_TXCTL_OUTRW320x0000 074C0x4844 A74C
CFG_RGMII0_TXD0_INRW320x0000 07500x4844 A750
CFG_RGMII0_TXD0_OENRW320x0000 07540x4844 A754
CFG_RGMII0_TXD0_OUTRW320x0000 07580x4844 A758
CFG_RGMII0_TXD1_INRW320x0000 075C0x4844 A75C
CFG_RGMII0_TXD1_OENRW320x0000 07600x4844 A760
CFG_RGMII0_TXD1_OUTRW320x0000 07640x4844 A764
CFG_RGMII0_TXD2_INRW320x0000 07680x4844 A768
CFG_RGMII0_TXD2_OENRW320x0000 076C0x4844 A76C
CFG_RGMII0_TXD2_OUTRW320x0000 07700x4844 A770
CFG_RGMII0_TXD3_INRW320x0000 07740x4844 A774
CFG_RGMII0_TXD3_OENRW320x0000 07780x4844 A778
CFG_RGMII0_TXD3_OUTRW320x0000 077C0x4844 A77C
CFG_RTCK_INRW320x0000 07800x4844 A780
CFG_RTCK_OENRW320x0000 07840x4844 A784
CFG_RTCK_OUTRW320x0000 07880x4844 A788
CFG_SPI1_CS0_INRW320x0000 078C0x4844 A78C
CFG_SPI1_CS0_OENRW320x0000 07900x4844 A790
CFG_SPI1_CS0_OUTRW320x0000 07940x4844 A794
CFG_SPI1_CS1_INRW320x0000 07980x4844 A798
CFG_SPI1_CS1_OENRW320x0000 079C0x4844 A79C
CFG_SPI1_CS1_OUTRW320x0000 07A00x4844 A7A0
CFG_SPI1_CS2_INRW320x0000 07A40x4844 A7A4
CFG_SPI1_CS2_OENRW320x0000 07A80x4844 A7A8
CFG_SPI1_CS2_OUTRW320x0000 07AC0x4844 A7AC
CFG_SPI1_CS3_INRW320x0000 07B00x4844 A7B0
CFG_SPI1_CS3_OENRW320x0000 07B40x4844 A7B4
CFG_SPI1_CS3_OUTRW320x0000 07B80x4844 A7B8
CFG_SPI1_D0_INRW320x0000 07BC0x4844 A7BC
CFG_SPI1_D0_OENRW320x0000 07C00x4844 A7C0
CFG_SPI1_D0_OUTRW320x0000 07C40x4844 A7C4
CFG_SPI1_D1_INRW320x0000 07C80x4844 A7C8
CFG_SPI1_D1_OENRW320x0000 07CC0x4844 A7CC
CFG_SPI1_D1_OUTRW320x0000 07D00x4844 A7D0
CFG_SPI1_SCLK_INRW320x0000 07D40x4844 A7D4
CFG_SPI1_SCLK_OENRW320x0000 07D80x4844 A7D8
CFG_SPI1_SCLK_OUTRW320x0000 07DC0x4844 A7DC
CFG_SPI2_CS0_INRW320x0000 07E00x4844 A7E0
CFG_SPI2_CS0_OENRW320x0000 07E40x4844 A7E4
CFG_SPI2_CS0_OUTRW320x0000 07E80x4844 A7E8
CFG_SPI2_D0_INRW320x0000 07EC0x4844 A7EC
CFG_SPI2_D0_OENRW320x0000 07F00x4844 A7F0
CFG_SPI2_D0_OUTRW320x0000 07F40x4844 A7F4
CFG_SPI2_D1_INRW320x0000 07F80x4844 A7F8
CFG_SPI2_D1_OENRW320x0000 07FC0x4844 A7FC
CFG_SPI2_D1_OUTRW320x0000 08000x4844 A800
CFG_SPI2_SCLK_INRW320x0000 08040x4844 A804
CFG_SPI2_SCLK_OENRW320x0000 08080x4844 A808
CFG_SPI2_SCLK_OUTRW320x0000 080C0x4844 A80C
CFG_TDI_INRW320x0000 08100x4844 A810
CFG_TDI_OENRW320x0000 08140x4844 A814
CFG_TDI_OUTRW320x0000 08180x4844 A818
CFG_TDO_INRW320x0000 081C0x4844 A81C
CFG_TDO_OENRW320x0000 08200x4844 A820
CFG_TDO_OUTRW320x0000 08240x4844 A824
CFG_TMS_INRW320x0000 08280x4844 A828
CFG_TMS_OENRW320x0000 082C0x4844 A82C
CFG_TMS_OUTRW320x0000 08300x4844 A830
CFG_TRSTN_INRW320x0000 08340x4844 A834
CFG_TRSTN_OENRW320x0000 08380x4844 A838
CFG_TRSTN_OUTRW320x0000 083C0x4844 A83C
CFG_UART1_CTSN_INRW320x0000 08400x4844 A840
CFG_UART1_CTSN_OENRW320x0000 08440x4844 A844
CFG_UART1_CTSN_OUTRW320x0000 08480x4844 A848
CFG_UART1_RTSN_INRW320x0000 084C0x4844 A84C
CFG_UART1_RTSN_OENRW320x0000 08500x4844 A850
CFG_UART1_RTSN_OUTRW320x0000 08540x4844 A854
CFG_UART1_RXD_INRW320x0000 08580x4844 A858
CFG_UART1_RXD_OENRW320x0000 085C0x4844 A85C
CFG_UART1_RXD_OUTRW320x0000 08600x4844 A860
CFG_UART1_TXD_INRW320x0000 08640x4844 A864
CFG_UART1_TXD_OENRW320x0000 08680x4844 A868
CFG_UART1_TXD_OUTRW320x0000 086C0x4844 A86C
CFG_UART2_CTSN_INRW320x0000 08700x4844 A870
CFG_UART2_CTSN_OENRW320x0000 08740x4844 A874
CFG_UART2_CTSN_OUTRW320x0000 08780x4844 A878
CFG_UART2_RTSN_INRW320x0000 087C0x4844 A87C
CFG_UART2_RTSN_OENRW320x0000 08800x4844 A880
CFG_UART2_RTSN_OUTRW320x0000 08840x4844 A884
CFG_UART2_RXD_INRW320x0000 08880x4844 A888
CFG_UART2_RXD_OENRW320x0000 088C0x4844 A88C
CFG_UART2_RXD_OUTRW320x0000 08900x4844 A890
CFG_UART2_TXD_INRW320x0000 08940x4844 A894
CFG_UART2_TXD_OENRW320x0000 08980x4844 A898
CFG_UART2_TXD_OUTRW320x0000 089C0x4844 A89C
CFG_UART3_RXD_INRW320x0000 08A00x4844 A8A0
CFG_UART3_RXD_OENRW320x0000 08A40x4844 A8A4
CFG_UART3_RXD_OUTRW320x0000 08A80x4844 A8A8
CFG_UART3_TXD_INRW320x0000 08AC0x4844 A8AC
CFG_UART3_TXD_OENRW320x0000 08B00x4844 A8B0
CFG_UART3_TXD_OUTRW320x0000 08B40x4844 A8B4
CFG_USB1_DRVVBUS_INRW320x0000 08B80x4844 A8B8
CFG_USB1_DRVVBUS_OENRW320x0000 08BC0x4844 A8BC
CFG_USB1_DRVVBUS_OUTRW320x0000 08C00x4844 A8C0
CFG_USB2_DRVVBUS_INRW320x0000 08C40x4844 A8C4
CFG_USB2_DRVVBUS_OENRW320x0000 08C80x4844 A8C8
CFG_USB2_DRVVBUS_OUTRW320x0000 08CC0x4844 A8CC
CFG_VIN1A_CLK0_INRW320x0000 08D00x4844 A8D0
CFG_VIN1A_CLK0_OENRW320x0000 08D40x4844 A8D4
CFG_VIN1A_CLK0_OUTRW320x0000 08D80x4844 A8D8
CFG_VIN1A_D0_INRW320x0000 08DC0x4844 A8DC
CFG_VIN1A_D0_OENRW320x0000 08E00x4844 A8E0
CFG_VIN1A_D0_OUTRW320x0000 08E40x4844 A8E4
CFG_VIN1A_D10_INRW320x0000 08E80x4844 A8E8
CFG_VIN1A_D10_OENRW320x0000 08EC0x4844 A8EC
CFG_VIN1A_D10_OUTRW320x0000 08F00x4844 A8F0
CFG_VIN1A_D11_INRW320x0000 08F40x4844 A8F4
CFG_VIN1A_D11_OENRW320x0000 08F80x4844 A8F8
CFG_VIN1A_D11_OUTRW320x0000 08FC0x4844 A8FC
CFG_VIN1A_D12_INRW320x0000 09000x4844 A900
CFG_VIN1A_D12_OENRW320x0000 09040x4844 A904
CFG_VIN1A_D12_OUTRW320x0000 09080x4844 A908
CFG_VIN1A_D13_INRW320x0000 090C0x4844 A90C
CFG_VIN1A_D13_OENRW320x0000 09100x4844 A910
CFG_VIN1A_D13_OUTRW320x0000 09140x4844 A914
CFG_VIN1A_D14_INRW320x0000 09180x4844 A918
CFG_VIN1A_D14_OENRW320x0000 091C0x4844 A91C
CFG_VIN1A_D14_OUTRW320x0000 09200x4844 A920
CFG_VIN1A_D15_INRW320x0000 09240x4844 A924
CFG_VIN1A_D15_OENRW320x0000 09280x4844 A928
CFG_VIN1A_D15_OUTRW320x0000 092C0x4844 A92C
CFG_VIN1A_D16_INRW320x0000 09300x4844 A930
CFG_VIN1A_D16_OENRW320x0000 09340x4844 A934
CFG_VIN1A_D16_OUTRW320x0000 09380x4844 A938
CFG_VIN1A_D17_INRW320x0000 093C0x4844 A93C
CFG_VIN1A_D17_OENRW320x0000 09400x4844 A940
CFG_VIN1A_D17_OUTRW320x0000 09440x4844 A944
CFG_VIN1A_D18_INRW320x0000 09480x4844 A948
CFG_VIN1A_D18_OENRW320x0000 094C0x4844 A94C
CFG_VIN1A_D18_OUTRW320x0000 09500x4844 A950
CFG_VIN1A_D19_INRW320x0000 09540x4844 A954
CFG_VIN1A_D19_OENRW320x0000 09580x4844 A958
CFG_VIN1A_D19_OUTRW320x0000 095C0x4844 A95C
CFG_VIN1A_D1_INRW320x0000 09600x4844 A960
CFG_VIN1A_D1_OENRW320x0000 09640x4844 A964
CFG_VIN1A_D1_OUTRW320x0000 09680x4844 A968
CFG_VIN1A_D20_INRW320x0000 096C0x4844 A96C
CFG_VIN1A_D20_OENRW320x0000 09700x4844 A970
CFG_VIN1A_D20_OUTRW320x0000 09740x4844 A974
CFG_VIN1A_D21_INRW320x0000 09780x4844 A978
CFG_VIN1A_D21_OENRW320x0000 097C0x4844 A97C
CFG_VIN1A_D21_OUTRW320x0000 09800x4844 A980
CFG_VIN1A_D22_INRW320x0000 09840x4844 A984
CFG_VIN1A_D22_OENRW320x0000 09880x4844 A988
CFG_VIN1A_D22_OUTRW320x0000 098C0x4844 A98C
CFG_VIN1A_D23_INRW320x0000 09900x4844 A990
CFG_VIN1A_D23_OENRW320x0000 09940x4844 A994
CFG_VIN1A_D23_OUTRW320x0000 09980x4844 A998
CFG_VIN1A_D2_INRW320x0000 099C0x4844 A99C
CFG_VIN1A_D2_OENRW320x0000 09A00x4844 A9A0
CFG_VIN1A_D2_OUTRW320x0000 09A40x4844 A9A4
CFG_VIN1A_D3_INRW320x0000 09A80x4844 A9A8
CFG_VIN1A_D3_OENRW320x0000 09AC0x4844 A9AC
CFG_VIN1A_D3_OUTRW320x0000 09B00x4844 A9B0
CFG_VIN1A_D4_INRW320x0000 09B40x4844 A9B4
CFG_VIN1A_D4_OENRW320x0000 09B80x4844 A9B8
CFG_VIN1A_D4_OUTRW320x0000 09BC0x4844 A9BC
CFG_VIN1A_D5_INRW320x0000 09C00x4844 A9C0
CFG_VIN1A_D5_OENRW320x0000 09C40x4844 A9C4
CFG_VIN1A_D5_OUTRW320x0000 09C80x4844 A9C8
CFG_VIN1A_D6_INRW320x0000 09CC0x4844 A9CC
CFG_VIN1A_D6_OENRW320x0000 09D00x4844 A9D0
CFG_VIN1A_D6_OUTRW320x0000 09D40x4844 A9D4
CFG_VIN1A_D7_INRW320x0000 09D80x4844 A9D8
CFG_VIN1A_D7_OENRW320x0000 09DC0x4844 A9DC
CFG_VIN1A_D7_OUTRW320x0000 09E00x4844 A9E0
CFG_VIN1A_D8_INRW320x0000 09E40x4844 A9E4
CFG_VIN1A_D8_OENRW320x0000 09E80x4844 A9E8
CFG_VIN1A_D8_OUTRW320x0000 09EC0x4844 A9EC
CFG_VIN1A_D9_INRW320x0000 09F00x4844 A9F0
CFG_VIN1A_D9_OENRW320x0000 09F40x4844 A9F4
CFG_VIN1A_D9_OUTRW320x0000 09F80x4844 A9F8
CFG_VIN1A_DE0_INRW320x0000 09FC0x4844 A9FC
CFG_VIN1A_DE0_OENRW320x0000 0A000x4844 AA00
CFG_VIN1A_DE0_OUTRW320x0000 0A040x4844 AA04
CFG_VIN1A_FLD0_INRW320x0000 0A080x4844 AA08
CFG_VIN1A_FLD0_OENRW320x0000 0A0C0x4844 AA0C
CFG_VIN1A_FLD0_OUTRW320x0000 0A100x4844 AA10
CFG_VIN1A_HSYNC0_INRW320x0000 0A140x4844 AA14
CFG_VIN1A_HSYNC0_OENRW320x0000 0A180x4844 AA18
CFG_VIN1A_HSYNC0_OUTRW320x0000 0A1C0x4844 AA1C
CFG_VIN1A_VSYNC0_INRW320x0000 0A200x4844 AA20
CFG_VIN1A_VSYNC0_OENRW320x0000 0A240x4844 AA24
CFG_VIN1A_VSYNC0_OUTRW320x0000 0A280x4844 AA28
CFG_VIN1B_CLK1_INRW320x0000 0A2C0x4844 AA2C
CFG_VIN1B_CLK1_OENRW320x0000 0A300x4844 AA30
CFG_VIN1B_CLK1_OUTRW320x0000 0A340x4844 AA34
CFG_VIN2A_CLK0_INRW320x0000 0A380x4844 AA38
CFG_VIN2A_CLK0_OENRW320x0000 0A3C0x4844 AA3C
CFG_VIN2A_CLK0_OUTRW320x0000 0A400x4844 AA40
CFG_VIN2A_D0_INRW320x0000 0A440x4844 AA44
CFG_VIN2A_D0_OENRW320x0000 0A480x4844 AA48
CFG_VIN2A_D0_OUTRW320x0000 0A4C0x4844 AA4C
CFG_VIN2A_D10_INRW320x0000 0A500x4844 AA50
CFG_VIN2A_D10_OENRW320x0000 0A540x4844 AA54
CFG_VIN2A_D10_OUTRW320x0000 0A580x4844 AA58
CFG_VIN2A_D11_INRW320x0000 0A5C0x4844 AA5C
CFG_VIN2A_D11_OENRW320x0000 0A600x4844 AA60
CFG_VIN2A_D11_OUTRW320x0000 0A640x4844 AA64
CFG_VIN2A_D12_INRW320x0000 0A680x4844 AA68
CFG_VIN2A_D12_OENRW320x0000 0A6C0x4844 AA6C
CFG_VIN2A_D12_OUTRW320x0000 0A700x4844 AA70
CFG_VIN2A_D13_INRW320x0000 0A740x4844 AA74
CFG_VIN2A_D13_OENRW320x0000 0A780x4844 AA78
CFG_VIN2A_D13_OUTRW320x0000 0A7C0x4844 AA7C
CFG_VIN2A_D14_INRW320x0000 0A800x4844 AA80
CFG_VIN2A_D14_OENRW320x0000 0A840x4844 AA84
CFG_VIN2A_D14_OUTRW320x0000 0A880x4844 AA88
CFG_VIN2A_D15_INRW320x0000 0A8C0x4844 AA8C
CFG_VIN2A_D15_OENRW320x0000 0A900x4844 AA90
CFG_VIN2A_D15_OUTRW320x0000 0A940x4844 AA94
CFG_VIN2A_D16_INRW320x0000 0A980x4844 AA98
CFG_VIN2A_D16_OENRW320x0000 0A9C0x4844 AA9C
CFG_VIN2A_D16_OUTRW320x0000 0AA00x4844 AAA0
CFG_VIN2A_D17_INRW320x0000 0AA40x4844 AAA4
CFG_VIN2A_D17_OENRW320x0000 0AA80x4844 AAA8
CFG_VIN2A_D17_OUTRW320x0000 0AAC0x4844 AAAC
CFG_VIN2A_D18_INRW320x0000 0AB00x4844 AAB0
CFG_VIN2A_D18_OENRW320x0000 0AB40x4844 AAB4
CFG_VIN2A_D18_OUTRW320x0000 0AB80x4844 AAB8
CFG_VIN2A_D19_INRW320x0000 0ABC0x4844 AABC
CFG_VIN2A_D19_OENRW320x0000 0AC00x4844 AAC0
CFG_VIN2A_D19_OUTRW320x0000 0AC40x4844 AAC4
CFG_VIN2A_D1_INRW320x0000 0AC80x4844 AAC8
CFG_VIN2A_D1_OENRW320x0000 0ACC0x4844 AACC
CFG_VIN2A_D1_OUTRW320x0000 0AD00x4844 AAD0
CFG_VIN2A_D20_INRW320x0000 0AD40x4844 AAD4
CFG_VIN2A_D20_OENRW320x0000 0AD80x4844 AAD8
CFG_VIN2A_D20_OUTRW320x0000 0ADC0x4844 AADC
CFG_VIN2A_D21_INRW320x0000 0AE00x4844 AAE0
CFG_VIN2A_D21_OENRW320x0000 0AE40x4844 AAE4
CFG_VIN2A_D21_OUTRW320x0000 0AE80x4844 AAE8
CFG_VIN2A_D22_INRW320x0000 0AEC0x4844 AAEC
CFG_VIN2A_D22_OENRW320x0000 0AF00x4844 AAF0
CFG_VIN2A_D22_OUTRW320x0000 0AF40x4844 AAF4
CFG_VIN2A_D23_INRW320x0000 0AF80x4844 AAF8
CFG_VIN2A_D23_OENRW320x0000 0AFC0x4844 AAFC
CFG_VIN2A_D23_OUTRW320x0000 0B000x4844 AB00
CFG_VIN2A_D2_INRW320x0000 0B040x4844 AB04
CFG_VIN2A_D2_OENRW320x0000 0B080x4844 AB08
CFG_VIN2A_D2_OUTRW320x0000 0B0C0x4844 AB0C
CFG_VIN2A_D3_INRW320x0000 0B100x4844 AB10
CFG_VIN2A_D3_OENRW320x0000 0B140x4844 AB14
CFG_VIN2A_D3_OUTRW320x0000 0B180x4844 AB18
CFG_VIN2A_D4_INRW320x0000 0B1C0x4844 AB1C
CFG_VIN2A_D4_OENRW320x0000 0B200x4844 AB20
CFG_VIN2A_D4_OUTRW320x0000 0B240x4844 AB24
CFG_VIN2A_D5_INRW320x0000 0B280x4844 AB28
CFG_VIN2A_D5_OENRW320x0000 0B2C0x4844 AB2C
CFG_VIN2A_D5_OUTRW320x0000 0B300x4844 AB30
CFG_VIN2A_D6_INRW320x0000 0B340x4844 AB34
CFG_VIN2A_D6_OENRW320x0000 0B380x4844 AB38
CFG_VIN2A_D6_OUTRW320x0000 0B3C0x4844 AB3C
CFG_VIN2A_D7_INRW320x0000 0B400x4844 AB40
CFG_VIN2A_D7_OENRW320x0000 0B440x4844 AB44
CFG_VIN2A_D7_OUTRW320x0000 0B480x4844 AB48
CFG_VIN2A_D8_INRW320x0000 0B4C0x4844 AB4C
CFG_VIN2A_D8_OENRW320x0000 0B500x4844 AB50
CFG_VIN2A_D8_OUTRW320x0000 0B540x4844 AB54
CFG_VIN2A_D9_INRW320x0000 0B580x4844 AB58
CFG_VIN2A_D9_OENRW320x0000 0B5C0x4844 AB5C
CFG_VIN2A_D9_OUTRW320x0000 0B600x4844 AB60
CFG_VIN2A_DE0_INRW320x0000 0B640x4844 AB64
CFG_VIN2A_DE0_OENRW320x0000 0B680x4844 AB68
CFG_VIN2A_DE0_OUTRW320x0000 0B6C0x4844 AB6C
CFG_VIN2A_FLD0_INRW320x0000 0B700x4844 AB70
CFG_VIN2A_FLD0_OENRW320x0000 0B740x4844 AB74
CFG_VIN2A_FLD0_OUTRW320x0000 0B780x4844 AB78
CFG_VIN2A_HSYNC0_INRW320x0000 0B7C0x4844 AB7C
CFG_VIN2A_HSYNC0_OENRW320x0000 0B800x4844 AB80
CFG_VIN2A_HSYNC0_OUTRW320x0000 0B840x4844 AB84
CFG_VIN2A_VSYNC0_INRW320x0000 0B880x4844 AB88
CFG_VIN2A_VSYNC0_OENRW320x0000 0B8C0x4844 AB8C
CFG_VIN2A_VSYNC0_OUTRW320x0000 0B900x4844 AB90
CFG_VOUT1_CLK_INRW320x0000 0B940x4844 AB94
CFG_VOUT1_CLK_OENRW320x0000 0B980x4844 AB98
CFG_VOUT1_CLK_OUTRW320x0000 0B9C0x4844 AB9C
CFG_VOUT1_D0_INRW320x0000 0BA00x4844 ABA0
CFG_VOUT1_D0_OENRW320x0000 0BA40x4844 ABA4
CFG_VOUT1_D0_OUTRW320x0000 0BA80x4844 ABA8
CFG_VOUT1_D10_INRW320x0000 0BAC0x4844 ABAC
CFG_VOUT1_D10_OENRW320x0000 0BB00x4844 ABB0
CFG_VOUT1_D10_OUTRW320x0000 0BB40x4844 ABB4
CFG_VOUT1_D11_INRW320x0000 0BB80x4844 ABB8
CFG_VOUT1_D11_OENRW320x0000 0BBC0x4844 ABBC
CFG_VOUT1_D11_OUTRW320x0000 0BC00x4844 ABC0
CFG_VOUT1_D12_INRW320x0000 0BC40x4844 ABC4
CFG_VOUT1_D12_OENRW320x0000 0BC80x4844 ABC8
CFG_VOUT1_D12_OUTRW320x0000 0BCC0x4844 ABCC
CFG_VOUT1_D13_INRW320x0000 0BD00x4844 ABD0
CFG_VOUT1_D13_OENRW320x0000 0BD40x4844 ABD4
CFG_VOUT1_D13_OUTRW320x0000 0BD80x4844 ABD8
CFG_VOUT1_D14_INRW320x0000 0BDC0x4844 ABDC
CFG_VOUT1_D14_OENRW320x0000 0BE00x4844 ABE0
CFG_VOUT1_D14_OUTRW320x0000 0BE40x4844 ABE4
CFG_VOUT1_D15_INRW320x0000 0BE80x4844 ABE8
CFG_VOUT1_D15_OENRW320x0000 0BEC0x4844 ABEC
CFG_VOUT1_D15_OUTRW320x0000 0BF00x4844 ABF0
CFG_VOUT1_D16_INRW320x0000 0BF40x4844 ABF4
CFG_VOUT1_D16_OENRW320x0000 0BF80x4844 ABF8
CFG_VOUT1_D16_OUTRW320x0000 0BFC0x4844 ABFC
CFG_VOUT1_D17_INRW320x0000 0C000x4844 AC00
CFG_VOUT1_D17_OENRW320x0000 0C040x4844 AC04
CFG_VOUT1_D17_OUTRW320x0000 0C080x4844 AC08
CFG_VOUT1_D18_INRW320x0000 0C0C0x4844 AC0C
CFG_VOUT1_D18_OENRW320x0000 0C100x4844 AC10
CFG_VOUT1_D18_OUTRW320x0000 0C140x4844 AC14
CFG_VOUT1_D19_INRW320x0000 0C180x4844 AC18
CFG_VOUT1_D19_OENRW320x0000 0C1C0x4844 AC1C
CFG_VOUT1_D19_OUTRW320x0000 0C200x4844 AC20
CFG_VOUT1_D1_INRW320x0000 0C240x4844 AC24
CFG_VOUT1_D1_OENRW320x0000 0C280x4844 AC28
CFG_VOUT1_D1_OUTRW320x0000 0C2C0x4844 AC2C
CFG_VOUT1_D20_INRW320x0000 0C300x4844 AC30
CFG_VOUT1_D20_OENRW320x0000 0C340x4844 AC34
CFG_VOUT1_D20_OUTRW320x0000 0C380x4844 AC38
CFG_VOUT1_D21_INRW320x0000 0C3C0x4844 AC3C
CFG_VOUT1_D21_OENRW320x0000 0C400x4844 AC40
CFG_VOUT1_D21_OUTRW320x0000 0C440x4844 AC44
CFG_VOUT1_D22_INRW320x0000 0C480x4844 AC48
CFG_VOUT1_D22_OENRW320x0000 0C4C0x4844 AC4C
CFG_VOUT1_D22_OUTRW320x0000 0C500x4844 AC50
CFG_VOUT1_D23_INRW320x0000 0C540x4844 AC54
CFG_VOUT1_D23_OENRW320x0000 0C580x4844 AC58
CFG_VOUT1_D23_OUTRW320x0000 0C5C0x4844 AC5C
CFG_VOUT1_D2_INRW320x0000 0C600x4844 AC60
CFG_VOUT1_D2_OENRW320x0000 0C640x4844 AC64
CFG_VOUT1_D2_OUTRW320x0000 0C680x4844 AC68
CFG_VOUT1_D3_INRW320x0000 0C6C0x4844 AC6C
CFG_VOUT1_D3_OENRW320x0000 0C700x4844 AC70
CFG_VOUT1_D3_OUTRW320x0000 0C740x4844 AC74
CFG_VOUT1_D4_INRW320x0000 0C780x4844 AC78
CFG_VOUT1_D4_OENRW320x0000 0C7C0x4844 AC7C
CFG_VOUT1_D4_OUTRW320x0000 0C800x4844 AC80
CFG_VOUT1_D5_INRW320x0000 0C840x4844 AC84
CFG_VOUT1_D5_OENRW320x0000 0C880x4844 AC88
CFG_VOUT1_D5_OUTRW320x0000 0C8C0x4844 AC8C
CFG_VOUT1_D6_INRW320x0000 0C900x4844 AC90
CFG_VOUT1_D6_OENRW320x0000 0C940x4844 AC94
CFG_VOUT1_D6_OUTRW320x0000 0C980x4844 AC98
CFG_VOUT1_D7_INRW320x0000 0C9C0x4844 AC9C
CFG_VOUT1_D7_OENRW320x0000 0CA00x4844 ACA0
CFG_VOUT1_D7_OUTRW320x0000 0CA40x4844 ACA4
CFG_VOUT1_D8_INRW320x0000 0CA80x4844 ACA8
CFG_VOUT1_D8_OENRW320x0000 0CAC0x4844 ACAC
CFG_VOUT1_D8_OUTRW320x0000 0CB00x4844 ACB0
CFG_VOUT1_D9_INRW320x0000 0CB40x4844 ACB4
CFG_VOUT1_D9_OENRW320x0000 0CB80x4844 ACB8
CFG_VOUT1_D9_OUTRW320x0000 0CBC0x4844 ACBC
CFG_VOUT1_DE_INRW320x0000 0CC00x4844 ACC0
CFG_VOUT1_DE_OENRW320x0000 0CC40x4844 ACC4
CFG_VOUT1_DE_OUTRW320x0000 0CC80x4844 ACC8
CFG_VOUT1_FLD_INRW320x0000 0CCC0x4844 ACCC
CFG_VOUT1_FLD_OENRW320x0000 0CD00x4844 ACD0
CFG_VOUT1_FLD_OUTRW320x0000 0CD40x4844 ACD4
CFG_VOUT1_HSYNC_INRW320x0000 0CD80x4844 ACD8
CFG_VOUT1_HSYNC_OENRW320x0000 0CDC0x4844 ACDC
CFG_VOUT1_HSYNC_OUTRW320x0000 0CE00x4844 ACE0
CFG_VOUT1_VSYNC_INRW320x0000 0CE40x4844 ACE4
CFG_VOUT1_VSYNC_OENRW320x0000 0CE80x4844 ACE8
CFG_VOUT1_VSYNC_OUTRW320x0000 0CEC0x4844 ACEC
CFG_XREF_CLK0_INRW320x0000 0CF00x4844 ACF0
CFG_XREF_CLK0_OENRW320x0000 0CF40x4844 ACF4
CFG_XREF_CLK0_OUTRW320x0000 0CF80x4844 ACF8
CFG_XREF_CLK1_INRW320x0000 0CFC0x4844 ACFC
CFG_XREF_CLK1_OENRW320x0000 0D000x4844 AD00
CFG_XREF_CLK1_OUTRW320x0000 0D040x4844 AD04
CFG_XREF_CLK2_INRW320x0000 0D080x4844 AD08
CFG_XREF_CLK2_OENRW320x0000 0D0C0x4844 AD0C
CFG_XREF_CLK2_OUTRW320x0000 0D100x4844 AD10
CFG_XREF_CLK3_INRW320x0000 0D140x4844 AD14
CFG_XREF_CLK3_OENRW320x0000 0D180x4844 AD18
CFG_XREF_CLK3_OUTRW320x0000 0D1C0x4844 AD1C

20.7.4 IODELAYCONFIG Register Description

Table 20-920 CONFIG_REG_0
Address Offset0x0000 000C
Physical Address0x4844 A00CInstanceIODELAYCONFIG
DescriptionCalibration Control Register
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDROM_READCALIBRATION_START
BitsField NameDescriptionTypeReset
31:2RESERVEDR0x0
1ROM_READTriggers complete ROM read when '1' is written. Cleared when ROM read is complete.RW0x0
0CALIBRATION_STARTTriggers hardware calibration when '1' is written. Cleared when hardware completes calibration.RW0x0
Table 20-921 Register Call Summary for Register CONFIG_REG_0
Control Module Functional Description
IODELAYCONFIG Module Register Manual
Table 20-922 CONFIG_REG_2
Address Offset0x0000 0014
Physical Address0x4844 A014InstanceIODELAYCONFIG
DescriptionReference Clock Period Register.
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDREFCLK_PERIOD
BitsField NameDescriptionTypeReset
31:16RESERVEDR0x0
15:0REFCLK_PERIOD15:0 stores the binary equivalent of reference clock period in units of 10ps. This value (along with calibration results) is used for computing the coarse/fine element delay Example: 0xF0 means 2400ps.RW0x21D2
Table 20-923 Register Call Summary for Register CONFIG_REG_2
Control Module Functional Description
IODELAYCONFIG Module Register Manual
Table 20-924 CONFIG_REG_3
Address Offset0x0000 0018
Physical Address0x4844 A018InstanceIODELAYCONFIG
Descriptioncoarse calibration results register
TypeRW
313029282726252423222120191817161514131211109876543210
COARSE_DELAY_COUNTCOARSE_REF_COUNT
BitsField NameDescriptionTypeReset
31:16COARSE_DELAY_COUNTResults of 16 bit counter clocked by "delay line oscillator" clock during calibration.RW0x0
15:0COARSE_REF_COUNTResults of 16 bit counter clocked by "reference" clock during coarse calibration.RW0x0
Table 20-925 Register Call Summary for Register CONFIG_REG_3
IODELAYCONFIG Module Register Manual
Table 20-926 CONFIG_REG_4
Address Offset0x0000 001C
Physical Address0x4844 A01CInstanceIODELAYCONFIG
Descriptionfine calibration results register
TypeRW
313029282726252423222120191817161514131211109876543210
FINE_DELAY_COUNTFINE_REF_COUNT
BitsField NameDescriptionTypeReset
31:16FINE_DELAY_COUNTResults of 16 bit counter clocked by "delay line oscillator" clock during fine calibration.RW0x0
15:0FINE_REF_COUNTResults of 16 bit counter clocked by "reference" clock during fine calibration.RW0x0
Table 20-927 Register Call Summary for Register CONFIG_REG_4
IODELAYCONFIG Module Register Manual
Table 20-928 CONFIG_REG_8
Address Offset0x0000 002C
Physical Address0x4844 A02CInstanceIODELAYCONFIG
DescriptionGlobal Lock Register.
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDGLOBAL_LOCK_BIT
BitsField NameDescriptionTypeReset
31:1RESERVEDR0x0
0GLOBAL_LOCK_BITGlobal Lock Bit Register. A '1' in this bit protects the writes to MMRs that store delay line select values. A '0' in this bit indicates that MMRs that store delay line select values are writeable. To write a '0' to this bit, signature of 0x5555 must be used on the MSB bits 16:1 of mdata.RW0x1
Table 20-929 Register Call Summary for Register CONFIG_REG_8
Control Module Functional Description
IODELAYCONFIG Module Register Manual
Table 20-930 CFG_RMII_MHZ_50_CLK_IN
Address Offset0x0000 0030
Physical Address0x4844 A030InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_RMII_MHZ_50_CLK_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-931 Register Call Summary for Register CFG_RMII_MHZ_50_CLK_IN
IODELAYCONFIG Module Register Manual
Table 20-932 CFG_RMII_MHZ_50_CLK_OEN
Address Offset0x0000 0034
Physical Address0x4844 A034InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_RMII_MHZ_50_CLK_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-933 Register Call Summary for Register CFG_RMII_MHZ_50_CLK_OEN
IODELAYCONFIG Module Register Manual
Table 20-934 CFG_RMII_MHZ_50_CLK_OUT
Address Offset0x0000 0038
Physical Address0x4844 A038InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_RMII_MHZ_50_CLK_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-935 Register Call Summary for Register CFG_RMII_MHZ_50_CLK_OUT
IODELAYCONFIG Module Register Manual
Table 20-936 CFG_WAKEUP0_IN
Address Offset0x0000 003C
Physical Address0x4844 A03CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_Wakeup0_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-937 Register Call Summary for Register CFG_WAKEUP0_IN
IODELAYCONFIG Module Register Manual
Table 20-938 CFG_WAKEUP0_OEN
Address Offset0x0000 0040
Physical Address0x4844 A040InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_Wakeup0_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-939 Register Call Summary for Register CFG_WAKEUP0_OEN
IODELAYCONFIG Module Register Manual
Table 20-940 CFG_WAKEUP0_OUT
Address Offset0x0000 0044
Physical Address0x4844 A044InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_Wakeup0_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-941 Register Call Summary for Register CFG_WAKEUP0_OUT
IODELAYCONFIG Module Register Manual
Table 20-942 CFG_WAKEUP1_IN
Address Offset0x0000 0048
Physical Address0x4844 A048InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_Wakeup1_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-943 Register Call Summary for Register CFG_WAKEUP1_IN
IODELAYCONFIG Module Register Manual
Table 20-944 CFG_WAKEUP1_OEN
Address Offset0x0000 004C
Physical Address0x4844 A04CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_Wakeup1_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-945 Register Call Summary for Register CFG_WAKEUP1_OEN
IODELAYCONFIG Module Register Manual
Table 20-946 CFG_WAKEUP1_OUT
Address Offset0x0000 0050
Physical Address0x4844 A050InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_Wakeup1_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-947 Register Call Summary for Register CFG_WAKEUP1_OUT
IODELAYCONFIG Module Register Manual
Table 20-948 CFG_WAKEUP2_IN
Address Offset0x0000 0054
Physical Address0x4844 A054InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_Wakeup2_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-949 Register Call Summary for Register CFG_WAKEUP2_IN
IODELAYCONFIG Module Register Manual
Table 20-950 CFG_WAKEUP2_OEN
Address Offset0x0000 0058
Physical Address0x4844 A058InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_Wakeup2_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-951 Register Call Summary for Register CFG_WAKEUP2_OEN
IODELAYCONFIG Module Register Manual
Table 20-952 CFG_WAKEUP2_OUT
Address Offset0x0000 005C
Physical Address0x4844 A05CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_Wakeup2_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-953 Register Call Summary for Register CFG_WAKEUP2_OUT
IODELAYCONFIG Module Register Manual
Table 20-954 CFG_WAKEUP3_IN
Address Offset0x0000 0060
Physical Address0x4844 A060InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_Wakeup3_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-955 Register Call Summary for Register CFG_WAKEUP3_IN
IODELAYCONFIG Module Register Manual
Table 20-956 CFG_WAKEUP3_OEN
Address Offset0x0000 0064
Physical Address0x4844 A064InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_Wakeup3_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-957 Register Call Summary for Register CFG_WAKEUP3_OEN
IODELAYCONFIG Module Register Manual
Table 20-958 CFG_WAKEUP3_OUT
Address Offset0x0000 0068
Physical Address0x4844 A068InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_Wakeup3_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-959 Register Call Summary for Register CFG_WAKEUP3_OUT
IODELAYCONFIG Module Register Manual
Table 20-960 CFG_DCAN1_RX_IN
Address Offset0x0000 006C
Physical Address0x4844 A06CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_dcan1_rx_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-961 Register Call Summary for Register CFG_DCAN1_RX_IN
IODELAYCONFIG Module Register Manual
Table 20-962 CFG_DCAN1_RX_OEN
Address Offset0x0000 0070
Physical Address0x4844 A070InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_dcan1_rx_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-963 Register Call Summary for Register CFG_DCAN1_RX_OEN
IODELAYCONFIG Module Register Manual
Table 20-964 CFG_DCAN1_RX_OUT
Address Offset0x0000 0074
Physical Address0x4844 A074InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_dcan1_rx_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-965 Register Call Summary for Register CFG_DCAN1_RX_OUT
IODELAYCONFIG Module Register Manual
Table 20-966 CFG_DCAN1_TX_IN
Address Offset0x0000 0078
Physical Address0x4844 A078InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_dcan1_tx_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-967 Register Call Summary for Register CFG_DCAN1_TX_IN
IODELAYCONFIG Module Register Manual
Table 20-968 CFG_DCAN1_TX_OEN
Address Offset0x0000 007C
Physical Address0x4844 A07CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_dcan1_tx_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-969 Register Call Summary for Register CFG_DCAN1_TX_OEN
IODELAYCONFIG Module Register Manual
Table 20-970 CFG_DCAN1_TX_OUT
Address Offset0x0000 0080
Physical Address0x4844 A080InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_dcan1_tx_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-971 Register Call Summary for Register CFG_DCAN1_TX_OUT
IODELAYCONFIG Module Register Manual
Table 20-972 CFG_DCAN2_RX_IN
Address Offset0x0000 0084
Physical Address0x4844 A084InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_dcan2_rx_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-973 Register Call Summary for Register CFG_DCAN2_RX_IN
IODELAYCONFIG Module Register Manual
Table 20-974 CFG_DCAN2_RX_OEN
Address Offset0x0000 0088
Physical Address0x4844 A088InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_dcan2_rx_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-975 Register Call Summary for Register CFG_DCAN2_RX_OEN
IODELAYCONFIG Module Register Manual
Table 20-976 CFG_DCAN2_RX_OUT
Address Offset0x0000 008C
Physical Address0x4844 A08CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_dcan2_rx_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-977 Register Call Summary for Register CFG_DCAN2_RX_OUT
IODELAYCONFIG Module Register Manual
Table 20-978 CFG_DCAN2_TX_IN
Address Offset0x0000 0090
Physical Address0x4844 A090InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_dcan2_tx_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-979 Register Call Summary for Register CFG_DCAN2_TX_IN
IODELAYCONFIG Module Register Manual
Table 20-980 CFG_DCAN2_TX_OEN
Address Offset0x0000 0094
Physical Address0x4844 A094InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_dcan2_tx_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-981 Register Call Summary for Register CFG_DCAN2_TX_OEN
IODELAYCONFIG Module Register Manual
Table 20-982 CFG_DCAN2_TX_OUT
Address Offset0x0000 0098
Physical Address0x4844 A098InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_dcan2_tx_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-983 Register Call Summary for Register CFG_DCAN2_TX_OUT
IODELAYCONFIG Module Register Manual
Table 20-984 CFG_EMU0_IN
Address Offset0x0000 009C
Physical Address0x4844 A09CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_emu0_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-985 Register Call Summary for Register CFG_EMU0_IN
IODELAYCONFIG Module Register Manual
Table 20-986 CFG_EMU0_OEN
Address Offset0x0000 00A0
Physical Address0x4844 A0A0InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_emu0_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-987 Register Call Summary for Register CFG_EMU0_OEN
IODELAYCONFIG Module Register Manual
Table 20-988 CFG_EMU0_OUT
Address Offset0x0000 00A4
Physical Address0x4844 A0A4InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_emu0_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-989 Register Call Summary for Register CFG_EMU0_OUT
IODELAYCONFIG Module Register Manual
Table 20-990 CFG_EMU1_IN
Address Offset0x0000 00A8
Physical Address0x4844 A0A8InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_emu1_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-991 Register Call Summary for Register CFG_EMU1_IN
IODELAYCONFIG Module Register Manual
Table 20-992 CFG_EMU1_OEN
Address Offset0x0000 00AC
Physical Address0x4844 A0ACInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_emu1_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-993 Register Call Summary for Register CFG_EMU1_OEN
IODELAYCONFIG Module Register Manual
Table 20-994 CFG_EMU1_OUT
Address Offset0x0000 00B0
Physical Address0x4844 A0B0InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_emu1_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-995 Register Call Summary for Register CFG_EMU1_OUT
IODELAYCONFIG Module Register Manual
Table 20-996 CFG_EMU2_IN
Address Offset0x0000 00B4
Physical Address0x4844 A0B4InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_emu2_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-997 Register Call Summary for Register CFG_EMU2_IN
IODELAYCONFIG Module Register Manual
Table 20-998 CFG_EMU2_OEN
Address Offset0x0000 00B8
Physical Address0x4844 A0B8InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_emu2_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-999 Register Call Summary for Register CFG_EMU2_OEN
IODELAYCONFIG Module Register Manual
Table 20-1000 CFG_EMU2_OUT
Address Offset0x0000 00BC
Physical Address0x4844 A0BCInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_emu2_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1001 Register Call Summary for Register CFG_EMU2_OUT
IODELAYCONFIG Module Register Manual
Table 20-1002 CFG_EMU3_IN
Address Offset0x0000 00C0
Physical Address0x4844 A0C0InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_emu3_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1003 Register Call Summary for Register CFG_EMU3_IN
IODELAYCONFIG Module Register Manual
Table 20-1004 CFG_EMU3_OEN
Address Offset0x0000 00C4
Physical Address0x4844 A0C4InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_emu3_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1005 Register Call Summary for Register CFG_EMU3_OEN
IODELAYCONFIG Module Register Manual
Table 20-1006 CFG_EMU3_OUT
Address Offset0x0000 00C8
Physical Address0x4844 A0C8InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_emu3_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1007 Register Call Summary for Register CFG_EMU3_OUT
IODELAYCONFIG Module Register Manual
Table 20-1008 CFG_EMU4_IN
Address Offset0x0000 00CC
Physical Address0x4844 A0CCInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_emu4_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1009 Register Call Summary for Register CFG_EMU4_IN
IODELAYCONFIG Module Register Manual
Table 20-1010 CFG_EMU4_OEN
Address Offset0x0000 00D0
Physical Address0x4844 A0D0InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_emu4_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1011 Register Call Summary for Register CFG_EMU4_OEN
IODELAYCONFIG Module Register Manual
Table 20-1012 CFG_EMU4_OUT
Address Offset0x0000 00D4
Physical Address0x4844 A0D4InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_emu4_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1013 Register Call Summary for Register CFG_EMU4_OUT
IODELAYCONFIG Module Register Manual
Table 20-1014 CFG_GPIO6_10_IN
Address Offset0x0000 00D8
Physical Address0x4844 A0D8InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpio6_10_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1015 Register Call Summary for Register CFG_GPIO6_10_IN
IODELAYCONFIG Module Register Manual
Table 20-1016 CFG_GPIO6_10_OEN
Address Offset0x0000 00DC
Physical Address0x4844 A0DCInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpio6_10_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1017 Register Call Summary for Register CFG_GPIO6_10_OEN
IODELAYCONFIG Module Register Manual
Table 20-1018 CFG_GPIO6_10_OUT
Address Offset0x0000 00E0
Physical Address0x4844 A0E0InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpio6_10_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1019 Register Call Summary for Register CFG_GPIO6_10_OUT
IODELAYCONFIG Module Register Manual
Table 20-1020 CFG_GPIO6_11_IN
Address Offset0x0000 00E4
Physical Address0x4844 A0E4InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpio6_11_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1021 Register Call Summary for Register CFG_GPIO6_11_IN
IODELAYCONFIG Module Register Manual
Table 20-1022 CFG_GPIO6_11_OEN
Address Offset0x0000 00E8
Physical Address0x4844 A0E8InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpio6_11_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1023 Register Call Summary for Register CFG_GPIO6_11_OEN
IODELAYCONFIG Module Register Manual
Table 20-1024 CFG_GPIO6_11_OUT
Address Offset0x0000 00EC
Physical Address0x4844 A0ECInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpio6_11_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1025 Register Call Summary for Register CFG_GPIO6_11_OUT
IODELAYCONFIG Module Register Manual
Table 20-1026 CFG_GPIO6_14_IN
Address Offset0x0000 00F0
Physical Address0x4844 A0F0InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpio6_14_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1027 Register Call Summary for Register CFG_GPIO6_14_IN
IODELAYCONFIG Module Register Manual
Table 20-1028 CFG_GPIO6_14_OEN
Address Offset0x0000 00F4
Physical Address0x4844 A0F4InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpio6_14_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1029 Register Call Summary for Register CFG_GPIO6_14_OEN
IODELAYCONFIG Module Register Manual
Table 20-1030 CFG_GPIO6_14_OUT
Address Offset0x0000 00F8
Physical Address0x4844 A0F8InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpio6_14_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1031 Register Call Summary for Register CFG_GPIO6_14_OUT
IODELAYCONFIG Module Register Manual
Table 20-1032 CFG_GPIO6_15_IN
Address Offset0x0000 00FC
Physical Address0x4844 A0FCInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpio6_15_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1033 Register Call Summary for Register CFG_GPIO6_15_IN
IODELAYCONFIG Module Register Manual
Table 20-1034 CFG_GPIO6_15_OEN
Address Offset0x0000 0100
Physical Address0x4844 A100InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpio6_15_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1035 Register Call Summary for Register CFG_GPIO6_15_OEN
IODELAYCONFIG Module Register Manual
Table 20-1036 CFG_GPIO6_15_OUT
Address Offset0x0000 0104
Physical Address0x4844 A104InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpio6_15_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1037 Register Call Summary for Register CFG_GPIO6_15_OUT
IODELAYCONFIG Module Register Manual
Table 20-1038 CFG_GPIO6_16_IN
Address Offset0x0000 0108
Physical Address0x4844 A108InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpio6_16_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1039 Register Call Summary for Register CFG_GPIO6_16_IN
IODELAYCONFIG Module Register Manual
Table 20-1040 CFG_GPIO6_16_OEN
Address Offset0x0000 010C
Physical Address0x4844 A10CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpio6_16_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1041 Register Call Summary for Register CFG_GPIO6_16_OEN
IODELAYCONFIG Module Register Manual
Table 20-1042 CFG_GPIO6_16_OUT
Address Offset0x0000 0110
Physical Address0x4844 A110InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpio6_16_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1043 Register Call Summary for Register CFG_GPIO6_16_OUT
IODELAYCONFIG Module Register Manual
Table 20-1044 CFG_GPMC_A0_IN
Address Offset0x0000 0114
Physical Address0x4844 A114InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a0_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1045 Register Call Summary for Register CFG_GPMC_A0_IN
IODELAYCONFIG Module Register Manual
Table 20-1046 CFG_GPMC_A0_OEN
Address Offset0x0000 0118
Physical Address0x4844 A118InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a0_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1047 Register Call Summary for Register CFG_GPMC_A0_OEN
IODELAYCONFIG Module Register Manual
Table 20-1048 CFG_GPMC_A0_OUT
Address Offset0x0000 011C
Physical Address0x4844 A11CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a0_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1049 Register Call Summary for Register CFG_GPMC_A0_OUT
IODELAYCONFIG Module Register Manual
Table 20-1050 CFG_GPMC_A10_IN
Address Offset0x0000 0120
Physical Address0x4844 A120InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a10_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1051 Register Call Summary for Register CFG_GPMC_A10_IN
IODELAYCONFIG Module Register Manual
Table 20-1052 CFG_GPMC_A10_OEN
Address Offset0x0000 0124
Physical Address0x4844 A124InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a10_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1053 Register Call Summary for Register CFG_GPMC_A10_OEN
IODELAYCONFIG Module Register Manual
Table 20-1054 CFG_GPMC_A10_OUT
Address Offset0x0000 0128
Physical Address0x4844 A128InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a10_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1055 Register Call Summary for Register CFG_GPMC_A10_OUT
IODELAYCONFIG Module Register Manual
Table 20-1056 CFG_GPMC_A11_IN
Address Offset0x0000 012C
Physical Address0x4844 A12CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a11_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1057 Register Call Summary for Register CFG_GPMC_A11_IN
IODELAYCONFIG Module Register Manual
Table 20-1058 CFG_GPMC_A11_OEN
Address Offset0x0000 0130
Physical Address0x4844 A130InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a11_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1059 Register Call Summary for Register CFG_GPMC_A11_OEN
IODELAYCONFIG Module Register Manual
Table 20-1060 CFG_GPMC_A11_OUT
Address Offset0x0000 0134
Physical Address0x4844 A134InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a11_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1061 Register Call Summary for Register CFG_GPMC_A11_OUT
IODELAYCONFIG Module Register Manual
Table 20-1062 CFG_GPMC_A12_IN
Address Offset0x0000 0138
Physical Address0x4844 A138InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a12_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1063 Register Call Summary for Register CFG_GPMC_A12_IN
IODELAYCONFIG Module Register Manual
Table 20-1064 CFG_GPMC_A12_OEN
Address Offset0x0000 013C
Physical Address0x4844 A13CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a12_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1065 Register Call Summary for Register CFG_GPMC_A12_OEN
IODELAYCONFIG Module Register Manual
Table 20-1066 CFG_GPMC_A12_OUT
Address Offset0x0000 0140
Physical Address0x4844 A140InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a12_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1067 Register Call Summary for Register CFG_GPMC_A12_OUT
IODELAYCONFIG Module Register Manual
Table 20-1068 CFG_GPMC_A13_IN
Address Offset0x0000 0144
Physical Address0x4844 A144InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a13_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1069 Register Call Summary for Register CFG_GPMC_A13_IN
IODELAYCONFIG Module Register Manual
Table 20-1070 CFG_GPMC_A13_OEN
Address Offset0x0000 0148
Physical Address0x4844 A148InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a13_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1071 Register Call Summary for Register CFG_GPMC_A13_OEN
IODELAYCONFIG Module Register Manual
Table 20-1072 CFG_GPMC_A13_OUT
Address Offset0x0000 014C
Physical Address0x4844 A14CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a13_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1073 Register Call Summary for Register CFG_GPMC_A13_OUT
IODELAYCONFIG Module Register Manual
Table 20-1074 CFG_GPMC_A14_IN
Address Offset0x0000 0150
Physical Address0x4844 A150InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a14_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1075 Register Call Summary for Register CFG_GPMC_A14_IN
IODELAYCONFIG Module Register Manual
Table 20-1076 CFG_GPMC_A14_OEN
Address Offset0x0000 0154
Physical Address0x4844 A154InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a14_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1077 Register Call Summary for Register CFG_GPMC_A14_OEN
IODELAYCONFIG Module Register Manual
Table 20-1078 CFG_GPMC_A14_OUT
Address Offset0x0000 0158
Physical Address0x4844 A158InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a14_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1079 Register Call Summary for Register CFG_GPMC_A14_OUT
IODELAYCONFIG Module Register Manual
Table 20-1080 CFG_GPMC_A15_IN
Address Offset0x0000 015C
Physical Address0x4844 A15CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a15_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1081 Register Call Summary for Register CFG_GPMC_A15_IN
IODELAYCONFIG Module Register Manual
Table 20-1082 CFG_GPMC_A15_OEN
Address Offset0x0000 0160
Physical Address0x4844 A160InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a15_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1083 Register Call Summary for Register CFG_GPMC_A15_OEN
IODELAYCONFIG Module Register Manual
Table 20-1084 CFG_GPMC_A15_OUT
Address Offset0x0000 0164
Physical Address0x4844 A164InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a15_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1085 Register Call Summary for Register CFG_GPMC_A15_OUT
IODELAYCONFIG Module Register Manual
Table 20-1086 CFG_GPMC_A16_IN
Address Offset0x0000 0168
Physical Address0x4844 A168InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a16_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1087 Register Call Summary for Register CFG_GPMC_A16_IN
IODELAYCONFIG Module Register Manual
Table 20-1088 CFG_GPMC_A16_OEN
Address Offset0x0000 016C
Physical Address0x4844 A16CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a16_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1089 Register Call Summary for Register CFG_GPMC_A16_OEN
IODELAYCONFIG Module Register Manual
Table 20-1090 CFG_GPMC_A16_OUT
Address Offset0x0000 0170
Physical Address0x4844 A170InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a16_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1091 Register Call Summary for Register CFG_GPMC_A16_OUT
IODELAYCONFIG Module Register Manual
Table 20-1092 CFG_GPMC_A17_IN
Address Offset0x0000 0174
Physical Address0x4844 A174InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a17_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1093 Register Call Summary for Register CFG_GPMC_A17_IN
IODELAYCONFIG Module Register Manual
Table 20-1094 CFG_GPMC_A17_OEN
Address Offset0x0000 0178
Physical Address0x4844 A178InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a17_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1095 Register Call Summary for Register CFG_GPMC_A17_OEN
IODELAYCONFIG Module Register Manual
Table 20-1096 CFG_GPMC_A17_OUT
Address Offset0x0000 017C
Physical Address0x4844 A17CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a17_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1097 Register Call Summary for Register CFG_GPMC_A17_OUT
IODELAYCONFIG Module Register Manual
Table 20-1098 CFG_GPMC_A18_IN
Address Offset0x0000 0180
Physical Address0x4844 A180InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a18_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1099 Register Call Summary for Register CFG_GPMC_A18_IN
IODELAYCONFIG Module Register Manual
Table 20-1100 CFG_GPMC_A18_OEN
Address Offset0x0000 0184
Physical Address0x4844 A184InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a18_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1101 Register Call Summary for Register CFG_GPMC_A18_OEN
IODELAYCONFIG Module Register Manual
Table 20-1102 CFG_GPMC_A18_OUT
Address Offset0x0000 0188
Physical Address0x4844 A188InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a18_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1103 Register Call Summary for Register CFG_GPMC_A18_OUT
IODELAYCONFIG Module Register Manual
Table 20-1104 CFG_GPMC_A19_IN
Address Offset0x0000 018C
Physical Address0x4844 A18CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a19_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1105 Register Call Summary for Register CFG_GPMC_A19_IN
IODELAYCONFIG Module Register Manual
Table 20-1106 CFG_GPMC_A19_OEN
Address Offset0x0000 0190
Physical Address0x4844 A190InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a19_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1107 Register Call Summary for Register CFG_GPMC_A19_OEN
IODELAYCONFIG Module Register Manual
Table 20-1108 CFG_GPMC_A19_OUT
Address Offset0x0000 0194
Physical Address0x4844 A194InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a19_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1109 Register Call Summary for Register CFG_GPMC_A19_OUT
IODELAYCONFIG Module Register Manual
Table 20-1110 CFG_GPMC_A1_IN
Address Offset0x0000 0198
Physical Address0x4844 A198InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a1_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1111 Register Call Summary for Register CFG_GPMC_A1_IN
IODELAYCONFIG Module Register Manual
Table 20-1112 CFG_GPMC_A1_OEN
Address Offset0x0000 019C
Physical Address0x4844 A19CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a1_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1113 Register Call Summary for Register CFG_GPMC_A1_OEN
IODELAYCONFIG Module Register Manual
Table 20-1114 CFG_GPMC_A1_OUT
Address Offset0x0000 01A0
Physical Address0x4844 A1A0InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a1_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1115 Register Call Summary for Register CFG_GPMC_A1_OUT
IODELAYCONFIG Module Register Manual
Table 20-1116 CFG_GPMC_A20_IN
Address Offset0x0000 01A4
Physical Address0x4844 A1A4InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a20_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1117 Register Call Summary for Register CFG_GPMC_A20_IN
IODELAYCONFIG Module Register Manual
Table 20-1118 CFG_GPMC_A20_OEN
Address Offset0x0000 01A8
Physical Address0x4844 A1A8InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a20_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1119 Register Call Summary for Register CFG_GPMC_A20_OEN
IODELAYCONFIG Module Register Manual
Table 20-1120 CFG_GPMC_A20_OUT
Address Offset0x0000 01AC
Physical Address0x4844 A1ACInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a20_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1121 Register Call Summary for Register CFG_GPMC_A20_OUT
IODELAYCONFIG Module Register Manual
Table 20-1122 CFG_GPMC_A21_IN
Address Offset0x0000 01B0
Physical Address0x4844 A1B0InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a21_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1123 Register Call Summary for Register CFG_GPMC_A21_IN
IODELAYCONFIG Module Register Manual
Table 20-1124 CFG_GPMC_A21_OEN
Address Offset0x0000 01B4
Physical Address0x4844 A1B4InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a21_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1125 Register Call Summary for Register CFG_GPMC_A21_OEN
IODELAYCONFIG Module Register Manual
Table 20-1126 CFG_GPMC_A21_OUT
Address Offset0x0000 01B8
Physical Address0x4844 A1B8InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a21_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1127 Register Call Summary for Register CFG_GPMC_A21_OUT
IODELAYCONFIG Module Register Manual
Table 20-1128 CFG_GPMC_A22_IN
Address Offset0x0000 01BC
Physical Address0x4844 A1BCInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a22_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1129 Register Call Summary for Register CFG_GPMC_A22_IN
IODELAYCONFIG Module Register Manual
Table 20-1130 CFG_GPMC_A22_OEN
Address Offset0x0000 01C0
Physical Address0x4844 A1C0InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a22_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1131 Register Call Summary for Register CFG_GPMC_A22_OEN
IODELAYCONFIG Module Register Manual
Table 20-1132 CFG_GPMC_A22_OUT
Address Offset0x0000 01C4
Physical Address0x4844 A1C4InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a22_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1133 Register Call Summary for Register CFG_GPMC_A22_OUT
IODELAYCONFIG Module Register Manual
Table 20-1134 CFG_GPMC_A23_IN
Address Offset0x0000 01C8
Physical Address0x4844 A1C8InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a23_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1135 Register Call Summary for Register CFG_GPMC_A23_IN
IODELAYCONFIG Module Register Manual
Table 20-1136 CFG_GPMC_A23_OEN
Address Offset0x0000 01CC
Physical Address0x4844 A1CCInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a23_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1137 Register Call Summary for Register CFG_GPMC_A23_OEN
IODELAYCONFIG Module Register Manual
Table 20-1138 CFG_GPMC_A23_OUT
Address Offset0x0000 01D0
Physical Address0x4844 A1D0InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a23_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1139 Register Call Summary for Register CFG_GPMC_A23_OUT
IODELAYCONFIG Module Register Manual
Table 20-1140 CFG_GPMC_A24_IN
Address Offset0x0000 01D4
Physical Address0x4844 A1D4InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a24_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1141 Register Call Summary for Register CFG_GPMC_A24_IN
IODELAYCONFIG Module Register Manual
Table 20-1142 CFG_GPMC_A24_OEN
Address Offset0x0000 01D8
Physical Address0x4844 A1D8InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a24_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1143 Register Call Summary for Register CFG_GPMC_A24_OEN
IODELAYCONFIG Module Register Manual
Table 20-1144 CFG_GPMC_A24_OUT
Address Offset0x0000 01DC
Physical Address0x4844 A1DCInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a24_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1145 Register Call Summary for Register CFG_GPMC_A24_OUT
IODELAYCONFIG Module Register Manual
Table 20-1146 CFG_GPMC_A25_IN
Address Offset0x0000 01E0
Physical Address0x4844 A1E0InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a25_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1147 Register Call Summary for Register CFG_GPMC_A25_IN
IODELAYCONFIG Module Register Manual
Table 20-1148 CFG_GPMC_A25_OEN
Address Offset0x0000 01E4
Physical Address0x4844 A1E4InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a25_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1149 Register Call Summary for Register CFG_GPMC_A25_OEN
IODELAYCONFIG Module Register Manual
Table 20-1150 CFG_GPMC_A25_OUT
Address Offset0x0000 01E8
Physical Address0x4844 A1E8InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a25_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1151 Register Call Summary for Register CFG_GPMC_A25_OUT
IODELAYCONFIG Module Register Manual
Table 20-1152 CFG_GPMC_A26_IN
Address Offset0x0000 01EC
Physical Address0x4844 A1ECInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a26_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1153 Register Call Summary for Register CFG_GPMC_A26_IN
IODELAYCONFIG Module Register Manual
Table 20-1154 CFG_GPMC_A26_OEN
Address Offset0x0000 01F0
Physical Address0x4844 A1F0InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a26_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1155 Register Call Summary for Register CFG_GPMC_A26_OEN
IODELAYCONFIG Module Register Manual
Table 20-1156 CFG_GPMC_A26_OUT
Address Offset0x0000 01F4
Physical Address0x4844 A1F4InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a26_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1157 Register Call Summary for Register CFG_GPMC_A26_OUT
IODELAYCONFIG Module Register Manual
Table 20-1158 CFG_GPMC_A27_IN
Address Offset0x0000 01F8
Physical Address0x4844 A1F8InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a27_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1159 Register Call Summary for Register CFG_GPMC_A27_IN
IODELAYCONFIG Module Register Manual
Table 20-1160 CFG_GPMC_A27_OEN
Address Offset0x0000 01FC
Physical Address0x4844 A1FCInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a27_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1161 Register Call Summary for Register CFG_GPMC_A27_OEN
IODELAYCONFIG Module Register Manual
Table 20-1162 CFG_GPMC_A27_OUT
Address Offset0x0000 0200
Physical Address0x4844 A200InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a27_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1163 Register Call Summary for Register CFG_GPMC_A27_OUT
IODELAYCONFIG Module Register Manual
Table 20-1164 CFG_GPMC_A2_IN
Address Offset0x0000 0204
Physical Address0x4844 A204InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a2_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1165 Register Call Summary for Register CFG_GPMC_A2_IN
IODELAYCONFIG Module Register Manual
Table 20-1166 CFG_GPMC_A2_OEN
Address Offset0x0000 0208
Physical Address0x4844 A208InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a2_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1167 Register Call Summary for Register CFG_GPMC_A2_OEN
IODELAYCONFIG Module Register Manual
Table 20-1168 CFG_GPMC_A2_OUT
Address Offset0x0000 020C
Physical Address0x4844 A20CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a2_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1169 Register Call Summary for Register CFG_GPMC_A2_OUT
IODELAYCONFIG Module Register Manual
Table 20-1170 CFG_GPMC_A3_IN
Address Offset0x0000 0210
Physical Address0x4844 A210InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a3_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1171 Register Call Summary for Register CFG_GPMC_A3_IN
IODELAYCONFIG Module Register Manual
Table 20-1172 CFG_GPMC_A3_OEN
Address Offset0x0000 0214
Physical Address0x4844 A214InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a3_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1173 Register Call Summary for Register CFG_GPMC_A3_OEN
IODELAYCONFIG Module Register Manual
Table 20-1174 CFG_GPMC_A3_OUT
Address Offset0x0000 0218
Physical Address0x4844 A218InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a3_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1175 Register Call Summary for Register CFG_GPMC_A3_OUT
IODELAYCONFIG Module Register Manual
Table 20-1176 CFG_GPMC_A4_IN
Address Offset0x0000 021C
Physical Address0x4844 A21CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a4_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1177 Register Call Summary for Register CFG_GPMC_A4_IN
IODELAYCONFIG Module Register Manual
Table 20-1178 CFG_GPMC_A4_OEN
Address Offset0x0000 0220
Physical Address0x4844 A220InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a4_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1179 Register Call Summary for Register CFG_GPMC_A4_OEN
IODELAYCONFIG Module Register Manual
Table 20-1180 CFG_GPMC_A4_OUT
Address Offset0x0000 0224
Physical Address0x4844 A224InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a4_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1181 Register Call Summary for Register CFG_GPMC_A4_OUT
IODELAYCONFIG Module Register Manual
Table 20-1182 CFG_GPMC_A5_IN
Address Offset0x0000 0228
Physical Address0x4844 A228InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a5_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1183 Register Call Summary for Register CFG_GPMC_A5_IN
IODELAYCONFIG Module Register Manual
Table 20-1184 CFG_GPMC_A5_OEN
Address Offset0x0000 022C
Physical Address0x4844 A22CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a5_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1185 Register Call Summary for Register CFG_GPMC_A5_OEN
IODELAYCONFIG Module Register Manual
Table 20-1186 CFG_GPMC_A5_OUT
Address Offset0x0000 0230
Physical Address0x4844 A230InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a5_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1187 Register Call Summary for Register CFG_GPMC_A5_OUT
IODELAYCONFIG Module Register Manual
Table 20-1188 CFG_GPMC_A6_IN
Address Offset0x0000 0234
Physical Address0x4844 A234InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a6_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1189 Register Call Summary for Register CFG_GPMC_A6_IN
IODELAYCONFIG Module Register Manual
Table 20-1190 CFG_GPMC_A6_OEN
Address Offset0x0000 0238
Physical Address0x4844 A238InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a6_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1191 Register Call Summary for Register CFG_GPMC_A6_OEN
IODELAYCONFIG Module Register Manual
Table 20-1192 CFG_GPMC_A6_OUT
Address Offset0x0000 023C
Physical Address0x4844 A23CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a6_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1193 Register Call Summary for Register CFG_GPMC_A6_OUT
IODELAYCONFIG Module Register Manual
Table 20-1194 CFG_GPMC_A7_IN
Address Offset0x0000 0240
Physical Address0x4844 A240InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a7_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1195 Register Call Summary for Register CFG_GPMC_A7_IN
IODELAYCONFIG Module Register Manual
Table 20-1196 CFG_GPMC_A7_OEN
Address Offset0x0000 0244
Physical Address0x4844 A244InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a7_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1197 Register Call Summary for Register CFG_GPMC_A7_OEN
IODELAYCONFIG Module Register Manual
Table 20-1198 CFG_GPMC_A7_OUT
Address Offset0x0000 0248
Physical Address0x4844 A248InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a7_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1199 Register Call Summary for Register CFG_GPMC_A7_OUT
IODELAYCONFIG Module Register Manual
Table 20-1200 CFG_GPMC_A8_IN
Address Offset0x0000 024C
Physical Address0x4844 A24CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a8_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1201 Register Call Summary for Register CFG_GPMC_A8_IN
IODELAYCONFIG Module Register Manual
Table 20-1202 CFG_GPMC_A8_OEN
Address Offset0x0000 0250
Physical Address0x4844 A250InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a8_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1203 Register Call Summary for Register CFG_GPMC_A8_OEN
IODELAYCONFIG Module Register Manual
Table 20-1204 CFG_GPMC_A8_OUT
Address Offset0x0000 0254
Physical Address0x4844 A254InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a8_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1205 Register Call Summary for Register CFG_GPMC_A8_OUT
IODELAYCONFIG Module Register Manual
Table 20-1206 CFG_GPMC_A9_IN
Address Offset0x0000 0258
Physical Address0x4844 A258InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a9_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1207 Register Call Summary for Register CFG_GPMC_A9_IN
IODELAYCONFIG Module Register Manual
Table 20-1208 CFG_GPMC_A9_OEN
Address Offset0x0000 025C
Physical Address0x4844 A25CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a9_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1209 Register Call Summary for Register CFG_GPMC_A9_OEN
IODELAYCONFIG Module Register Manual
Table 20-1210 CFG_GPMC_A9_OUT
Address Offset0x0000 0260
Physical Address0x4844 A260InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_a9_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1211 Register Call Summary for Register CFG_GPMC_A9_OUT
IODELAYCONFIG Module Register Manual
Table 20-1212 CFG_GPMC_AD0_IN
Address Offset0x0000 0264
Physical Address0x4844 A264InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_ad0_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1213 Register Call Summary for Register CFG_GPMC_AD0_IN
IODELAYCONFIG Module Register Manual
Table 20-1214 CFG_GPMC_AD0_OEN
Address Offset0x0000 0268
Physical Address0x4844 A268InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_ad0_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1215 Register Call Summary for Register CFG_GPMC_AD0_OEN
IODELAYCONFIG Module Register Manual
Table 20-1216 CFG_GPMC_AD0_OUT
Address Offset0x0000 026C
Physical Address0x4844 A26CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_ad0_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1217 Register Call Summary for Register CFG_GPMC_AD0_OUT
IODELAYCONFIG Module Register Manual
Table 20-1218 CFG_GPMC_AD10_IN
Address Offset0x0000 0270
Physical Address0x4844 A270InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_ad10_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1219 Register Call Summary for Register CFG_GPMC_AD10_IN
IODELAYCONFIG Module Register Manual
Table 20-1220 CFG_GPMC_AD10_OEN
Address Offset0x0000 0274
Physical Address0x4844 A274InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_ad10_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1221 Register Call Summary for Register CFG_GPMC_AD10_OEN
IODELAYCONFIG Module Register Manual
Table 20-1222 CFG_GPMC_AD10_OUT
Address Offset0x0000 0278
Physical Address0x4844 A278InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_ad10_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1223 Register Call Summary for Register CFG_GPMC_AD10_OUT
IODELAYCONFIG Module Register Manual
Table 20-1224 CFG_GPMC_AD11_IN
Address Offset0x0000 027C
Physical Address0x4844 A27CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_ad11_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1225 Register Call Summary for Register CFG_GPMC_AD11_IN
IODELAYCONFIG Module Register Manual
Table 20-1226 CFG_GPMC_AD11_OEN
Address Offset0x0000 0280
Physical Address0x4844 A280InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_ad11_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1227 Register Call Summary for Register CFG_GPMC_AD11_OEN
IODELAYCONFIG Module Register Manual
Table 20-1228 CFG_GPMC_AD11_OUT
Address Offset0x0000 0284
Physical Address0x4844 A284InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_ad11_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1229 Register Call Summary for Register CFG_GPMC_AD11_OUT
IODELAYCONFIG Module Register Manual
Table 20-1230 CFG_GPMC_AD12_IN
Address Offset0x0000 0288
Physical Address0x4844 A288InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_ad12_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1231 Register Call Summary for Register CFG_GPMC_AD12_IN
IODELAYCONFIG Module Register Manual
Table 20-1232 CFG_GPMC_AD12_OEN
Address Offset0x0000 028C
Physical Address0x4844 A28CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_ad12_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1233 Register Call Summary for Register CFG_GPMC_AD12_OEN
IODELAYCONFIG Module Register Manual
Table 20-1234 CFG_GPMC_AD12_OUT
Address Offset0x0000 0290
Physical Address0x4844 A290InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_ad12_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1235 Register Call Summary for Register CFG_GPMC_AD12_OUT
IODELAYCONFIG Module Register Manual
Table 20-1236 CFG_GPMC_AD13_IN
Address Offset0x0000 0294
Physical Address0x4844 A294InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_ad13_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1237 Register Call Summary for Register CFG_GPMC_AD13_IN
IODELAYCONFIG Module Register Manual
Table 20-1238 CFG_GPMC_AD13_OEN
Address Offset0x0000 0298
Physical Address0x4844 A298InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_ad13_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1239 Register Call Summary for Register CFG_GPMC_AD13_OEN
IODELAYCONFIG Module Register Manual
Table 20-1240 CFG_GPMC_AD13_OUT
Address Offset0x0000 029C
Physical Address0x4844 A29CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_ad13_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1241 Register Call Summary for Register CFG_GPMC_AD13_OUT
IODELAYCONFIG Module Register Manual
Table 20-1242 CFG_GPMC_AD14_IN
Address Offset0x0000 02A0
Physical Address0x4844 A2A0InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_ad14_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1243 Register Call Summary for Register CFG_GPMC_AD14_IN
IODELAYCONFIG Module Register Manual
Table 20-1244 CFG_GPMC_AD14_OEN
Address Offset0x0000 02A4
Physical Address0x4844 A2A4InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_ad14_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1245 Register Call Summary for Register CFG_GPMC_AD14_OEN
IODELAYCONFIG Module Register Manual
Table 20-1246 CFG_GPMC_AD14_OUT
Address Offset0x0000 02A8
Physical Address0x4844 A2A8InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_ad14_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1247 Register Call Summary for Register CFG_GPMC_AD14_OUT
IODELAYCONFIG Module Register Manual
Table 20-1248 CFG_GPMC_AD15_IN
Address Offset0x0000 02AC
Physical Address0x4844 A2ACInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_ad15_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1249 Register Call Summary for Register CFG_GPMC_AD15_IN
IODELAYCONFIG Module Register Manual
Table 20-1250 CFG_GPMC_AD15_OEN
Address Offset0x0000 02B0
Physical Address0x4844 A2B0InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_ad15_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1251 Register Call Summary for Register CFG_GPMC_AD15_OEN
IODELAYCONFIG Module Register Manual
Table 20-1252 CFG_GPMC_AD15_OUT
Address Offset0x0000 02B4
Physical Address0x4844 A2B4InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_ad15_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1253 Register Call Summary for Register CFG_GPMC_AD15_OUT
IODELAYCONFIG Module Register Manual
Table 20-1254 CFG_GPMC_AD1_IN
Address Offset0x0000 02B8
Physical Address0x4844 A2B8InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_ad1_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1255 Register Call Summary for Register CFG_GPMC_AD1_IN
IODELAYCONFIG Module Register Manual
Table 20-1256 CFG_GPMC_AD1_OEN
Address Offset0x0000 02BC
Physical Address0x4844 A2BCInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_ad1_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1257 Register Call Summary for Register CFG_GPMC_AD1_OEN
IODELAYCONFIG Module Register Manual
Table 20-1258 CFG_GPMC_AD1_OUT
Address Offset0x0000 02C0
Physical Address0x4844 A2C0InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_ad1_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1259 Register Call Summary for Register CFG_GPMC_AD1_OUT
IODELAYCONFIG Module Register Manual
Table 20-1260 CFG_GPMC_AD2_IN
Address Offset0x0000 02C4
Physical Address0x4844 A2C4InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_ad2_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1261 Register Call Summary for Register CFG_GPMC_AD2_IN
IODELAYCONFIG Module Register Manual
Table 20-1262 CFG_GPMC_AD2_OEN
Address Offset0x0000 02C8
Physical Address0x4844 A2C8InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_ad2_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1263 Register Call Summary for Register CFG_GPMC_AD2_OEN
IODELAYCONFIG Module Register Manual
Table 20-1264 CFG_GPMC_AD2_OUT
Address Offset0x0000 02CC
Physical Address0x4844 A2CCInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_ad2_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1265 Register Call Summary for Register CFG_GPMC_AD2_OUT
IODELAYCONFIG Module Register Manual
Table 20-1266 CFG_GPMC_AD3_IN
Address Offset0x0000 02D0
Physical Address0x4844 A2D0InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_ad3_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1267 Register Call Summary for Register CFG_GPMC_AD3_IN
IODELAYCONFIG Module Register Manual
Table 20-1268 CFG_GPMC_AD3_OEN
Address Offset0x0000 02D4
Physical Address0x4844 A2D4InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_ad3_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1269 Register Call Summary for Register CFG_GPMC_AD3_OEN
IODELAYCONFIG Module Register Manual
Table 20-1270 CFG_GPMC_AD3_OUT
Address Offset0x0000 02D8
Physical Address0x4844 A2D8InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_ad3_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1271 Register Call Summary for Register CFG_GPMC_AD3_OUT
IODELAYCONFIG Module Register Manual
Table 20-1272 CFG_GPMC_AD4_IN
Address Offset0x0000 02DC
Physical Address0x4844 A2DCInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_ad4_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1273 Register Call Summary for Register CFG_GPMC_AD4_IN
IODELAYCONFIG Module Register Manual
Table 20-1274 CFG_GPMC_AD4_OEN
Address Offset0x0000 02E0
Physical Address0x4844 A2E0InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_ad4_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1275 Register Call Summary for Register CFG_GPMC_AD4_OEN
IODELAYCONFIG Module Register Manual
Table 20-1276 CFG_GPMC_AD4_OUT
Address Offset0x0000 02E4
Physical Address0x4844 A2E4InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_ad4_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1277 Register Call Summary for Register CFG_GPMC_AD4_OUT
IODELAYCONFIG Module Register Manual
Table 20-1278 CFG_GPMC_AD5_IN
Address Offset0x0000 02E8
Physical Address0x4844 A2E8InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_ad5_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1279 Register Call Summary for Register CFG_GPMC_AD5_IN
IODELAYCONFIG Module Register Manual
Table 20-1280 CFG_GPMC_AD5_OEN
Address Offset0x0000 02EC
Physical Address0x4844 A2ECInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_ad5_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1281 Register Call Summary for Register CFG_GPMC_AD5_OEN
IODELAYCONFIG Module Register Manual
Table 20-1282 CFG_GPMC_AD5_OUT
Address Offset0x0000 02F0
Physical Address0x4844 A2F0InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_ad5_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1283 Register Call Summary for Register CFG_GPMC_AD5_OUT
IODELAYCONFIG Module Register Manual
Table 20-1284 CFG_GPMC_AD6_IN
Address Offset0x0000 02F4
Physical Address0x4844 A2F4InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_ad6_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1285 Register Call Summary for Register CFG_GPMC_AD6_IN
IODELAYCONFIG Module Register Manual
Table 20-1286 CFG_GPMC_AD6_OEN
Address Offset0x0000 02F8
Physical Address0x4844 A2F8InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_ad6_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1287 Register Call Summary for Register CFG_GPMC_AD6_OEN
IODELAYCONFIG Module Register Manual
Table 20-1288 CFG_GPMC_AD6_OUT
Address Offset0x0000 02FC
Physical Address0x4844 A2FCInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_ad6_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1289 Register Call Summary for Register CFG_GPMC_AD6_OUT
IODELAYCONFIG Module Register Manual
Table 20-1290 CFG_GPMC_AD7_IN
Address Offset0x0000 0300
Physical Address0x4844 A300InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_ad7_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1291 Register Call Summary for Register CFG_GPMC_AD7_IN
IODELAYCONFIG Module Register Manual
Table 20-1292 CFG_GPMC_AD7_OEN
Address Offset0x0000 0304
Physical Address0x4844 A304InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_ad7_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1293 Register Call Summary for Register CFG_GPMC_AD7_OEN
IODELAYCONFIG Module Register Manual
Table 20-1294 CFG_GPMC_AD7_OUT
Address Offset0x0000 0308
Physical Address0x4844 A308InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_ad7_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1295 Register Call Summary for Register CFG_GPMC_AD7_OUT
IODELAYCONFIG Module Register Manual
Table 20-1296 CFG_GPMC_AD8_IN
Address Offset0x0000 030C
Physical Address0x4844 A30CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_ad8_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1297 Register Call Summary for Register CFG_GPMC_AD8_IN
IODELAYCONFIG Module Register Manual
Table 20-1298 CFG_GPMC_AD8_OEN
Address Offset0x0000 0310
Physical Address0x4844 A310InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_ad8_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1299 Register Call Summary for Register CFG_GPMC_AD8_OEN
IODELAYCONFIG Module Register Manual
Table 20-1300 CFG_GPMC_AD8_OUT
Address Offset0x0000 0314
Physical Address0x4844 A314InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_ad8_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1301 Register Call Summary for Register CFG_GPMC_AD8_OUT
IODELAYCONFIG Module Register Manual
Table 20-1302 CFG_GPMC_AD9_IN
Address Offset0x0000 0318
Physical Address0x4844 A318InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_ad9_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1303 Register Call Summary for Register CFG_GPMC_AD9_IN
IODELAYCONFIG Module Register Manual
Table 20-1304 CFG_GPMC_AD9_OEN
Address Offset0x0000 031C
Physical Address0x4844 A31CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_ad9_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1305 Register Call Summary for Register CFG_GPMC_AD9_OEN
IODELAYCONFIG Module Register Manual
Table 20-1306 CFG_GPMC_AD9_OUT
Address Offset0x0000 0320
Physical Address0x4844 A320InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_ad9_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1307 Register Call Summary for Register CFG_GPMC_AD9_OUT
IODELAYCONFIG Module Register Manual
Table 20-1308 CFG_GPMC_ADVN_ALE_IN
Address Offset0x0000 0324
Physical Address0x4844 A324InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_advn_ale_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1309 Register Call Summary for Register CFG_GPMC_ADVN_ALE_IN
IODELAYCONFIG Module Register Manual
Table 20-1310 CFG_GPMC_ADVN_ALE_OEN
Address Offset0x0000 0328
Physical Address0x4844 A328InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_advn_ale_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1311 Register Call Summary for Register CFG_GPMC_ADVN_ALE_OEN
IODELAYCONFIG Module Register Manual
Table 20-1312 CFG_GPMC_ADVN_ALE_OUT
Address Offset0x0000 032C
Physical Address0x4844 A32CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_advn_ale_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1313 Register Call Summary for Register CFG_GPMC_ADVN_ALE_OUT
IODELAYCONFIG Module Register Manual
Table 20-1314 CFG_GPMC_BEN0_IN
Address Offset0x0000 0330
Physical Address0x4844 A330InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_ben0_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1315 Register Call Summary for Register CFG_GPMC_BEN0_IN
IODELAYCONFIG Module Register Manual
Table 20-1316 CFG_GPMC_BEN0_OEN
Address Offset0x0000 0334
Physical Address0x4844 A334InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_ben0_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1317 Register Call Summary for Register CFG_GPMC_BEN0_OEN
IODELAYCONFIG Module Register Manual
Table 20-1318 CFG_GPMC_BEN0_OUT
Address Offset0x0000 0338
Physical Address0x4844 A338InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_ben0_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1319 Register Call Summary for Register CFG_GPMC_BEN0_OUT
IODELAYCONFIG Module Register Manual
Table 20-1320 CFG_GPMC_BEN1_IN
Address Offset0x0000 033C
Physical Address0x4844 A33CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_ben1_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1321 Register Call Summary for Register CFG_GPMC_BEN1_IN
IODELAYCONFIG Module Register Manual
Table 20-1322 CFG_GPMC_BEN1_OEN
Address Offset0x0000 0340
Physical Address0x4844 A340InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_ben1_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1323 Register Call Summary for Register CFG_GPMC_BEN1_OEN
IODELAYCONFIG Module Register Manual
Table 20-1324 CFG_GPMC_BEN1_OUT
Address Offset0x0000 0344
Physical Address0x4844 A344InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_ben1_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1325 Register Call Summary for Register CFG_GPMC_BEN1_OUT
IODELAYCONFIG Module Register Manual
Table 20-1326 CFG_GPMC_CLK_IN
Address Offset0x0000 0348
Physical Address0x4844 A348InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_clk_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1327 Register Call Summary for Register CFG_GPMC_CLK_IN
IODELAYCONFIG Module Register Manual
Table 20-1328 CFG_GPMC_CLK_OEN
Address Offset0x0000 034C
Physical Address0x4844 A34CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_clk_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1329 Register Call Summary for Register CFG_GPMC_CLK_OEN
IODELAYCONFIG Module Register Manual
Table 20-1330 CFG_GPMC_CLK_OUT
Address Offset0x0000 0350
Physical Address0x4844 A350InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_clk_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1331 Register Call Summary for Register CFG_GPMC_CLK_OUT
IODELAYCONFIG Module Register Manual
Table 20-1332 CFG_GPMC_CS0_IN
Address Offset0x0000 0354
Physical Address0x4844 A354InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_cs0_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1333 Register Call Summary for Register CFG_GPMC_CS0_IN
IODELAYCONFIG Module Register Manual
Table 20-1334 CFG_GPMC_CS0_OEN
Address Offset0x0000 0358
Physical Address0x4844 A358InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_cs0_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1335 Register Call Summary for Register CFG_GPMC_CS0_OEN
IODELAYCONFIG Module Register Manual
Table 20-1336 CFG_GPMC_CS0_OUT
Address Offset0x0000 035C
Physical Address0x4844 A35CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_cs0_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1337 Register Call Summary for Register CFG_GPMC_CS0_OUT
IODELAYCONFIG Module Register Manual
Table 20-1338 CFG_GPMC_CS1_IN
Address Offset0x0000 0360
Physical Address0x4844 A360InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_cs1_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1339 Register Call Summary for Register CFG_GPMC_CS1_IN
IODELAYCONFIG Module Register Manual
Table 20-1340 CFG_GPMC_CS1_OEN
Address Offset0x0000 0364
Physical Address0x4844 A364InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_cs1_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1341 Register Call Summary for Register CFG_GPMC_CS1_OEN
IODELAYCONFIG Module Register Manual
Table 20-1342 CFG_GPMC_CS1_OUT
Address Offset0x0000 0368
Physical Address0x4844 A368InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_cs1_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1343 Register Call Summary for Register CFG_GPMC_CS1_OUT
IODELAYCONFIG Module Register Manual
Table 20-1344 CFG_GPMC_CS2_IN
Address Offset0x0000 036C
Physical Address0x4844 A36CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_cs2_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1345 Register Call Summary for Register CFG_GPMC_CS2_IN
IODELAYCONFIG Module Register Manual
Table 20-1346 CFG_GPMC_CS2_OEN
Address Offset0x0000 0370
Physical Address0x4844 A370InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_cs2_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1347 Register Call Summary for Register CFG_GPMC_CS2_OEN
IODELAYCONFIG Module Register Manual
Table 20-1348 CFG_GPMC_CS2_OUT
Address Offset0x0000 0374
Physical Address0x4844 A374InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_cs2_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1349 Register Call Summary for Register CFG_GPMC_CS2_OUT
IODELAYCONFIG Module Register Manual
Table 20-1350 CFG_GPMC_CS3_IN
Address Offset0x0000 0378
Physical Address0x4844 A378InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_cs3_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1351 Register Call Summary for Register CFG_GPMC_CS3_IN
IODELAYCONFIG Module Register Manual
Table 20-1352 CFG_GPMC_CS3_OEN
Address Offset0x0000 037C
Physical Address0x4844 A37CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_cs3_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1353 Register Call Summary for Register CFG_GPMC_CS3_OEN
IODELAYCONFIG Module Register Manual
Table 20-1354 CFG_GPMC_CS3_OUT
Address Offset0x0000 0380
Physical Address0x4844 A380InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_cs3_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1355 Register Call Summary for Register CFG_GPMC_CS3_OUT
IODELAYCONFIG Module Register Manual
Table 20-1356 CFG_GPMC_OEN_REN_IN
Address Offset0x0000 0384
Physical Address0x4844 A384InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_oen_ren_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1357 Register Call Summary for Register CFG_GPMC_OEN_REN_IN
IODELAYCONFIG Module Register Manual
Table 20-1358 CFG_GPMC_OEN_REN_OEN
Address Offset0x0000 0388
Physical Address0x4844 A388InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_oen_ren_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1359 Register Call Summary for Register CFG_GPMC_OEN_REN_OEN
IODELAYCONFIG Module Register Manual
Table 20-1360 CFG_GPMC_OEN_REN_OUT
Address Offset0x0000 038C
Physical Address0x4844 A38CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_oen_ren_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1361 Register Call Summary for Register CFG_GPMC_OEN_REN_OUT
IODELAYCONFIG Module Register Manual
Table 20-1362 CFG_GPMC_WAIT0_IN
Address Offset0x0000 0390
Physical Address0x4844 A390InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_wait0_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1363 Register Call Summary for Register CFG_GPMC_WAIT0_IN
IODELAYCONFIG Module Register Manual
Table 20-1364 CFG_GPMC_WAIT0_OEN
Address Offset0x0000 0394
Physical Address0x4844 A394InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_wait0_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1365 Register Call Summary for Register CFG_GPMC_WAIT0_OEN
IODELAYCONFIG Module Register Manual
Table 20-1366 CFG_GPMC_WAIT0_OUT
Address Offset0x0000 0398
Physical Address0x4844 A398InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_wait0_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1367 Register Call Summary for Register CFG_GPMC_WAIT0_OUT
IODELAYCONFIG Module Register Manual
Table 20-1368 CFG_GPMC_WEN_IN
Address Offset0x0000 039C
Physical Address0x4844 A39CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_wen_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1369 Register Call Summary for Register CFG_GPMC_WEN_IN
IODELAYCONFIG Module Register Manual
Table 20-1370 CFG_GPMC_WEN_OEN
Address Offset0x0000 03A0
Physical Address0x4844 A3A0InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_wen_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1371 Register Call Summary for Register CFG_GPMC_WEN_OEN
IODELAYCONFIG Module Register Manual
Table 20-1372 CFG_GPMC_WEN_OUT
Address Offset0x0000 03A4
Physical Address0x4844 A3A4InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_gpmc_wen_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1373 Register Call Summary for Register CFG_GPMC_WEN_OUT
IODELAYCONFIG Module Register Manual
Table 20-1374 CFG_MCASP1_ACLKR_IN
Address Offset0x0000 03A8
Physical Address0x4844 A3A8InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp1_aclkr_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1375 Register Call Summary for Register CFG_MCASP1_ACLKR_IN
IODELAYCONFIG Module Register Manual
Table 20-1376 CFG_MCASP1_ACLKR_OEN
Address Offset0x0000 03AC
Physical Address0x4844 A3ACInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp1_aclkr_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1377 Register Call Summary for Register CFG_MCASP1_ACLKR_OEN
IODELAYCONFIG Module Register Manual
Table 20-1378 CFG_MCASP1_ACLKR_OUT
Address Offset0x0000 03B0
Physical Address0x4844 A3B0InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp1_aclkr_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1379 Register Call Summary for Register CFG_MCASP1_ACLKR_OUT
IODELAYCONFIG Module Register Manual
Table 20-1380 CFG_MCASP1_ACLKX_IN
Address Offset0x0000 03B4
Physical Address0x4844 A3B4InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp1_aclkx_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1381 Register Call Summary for Register CFG_MCASP1_ACLKX_IN
IODELAYCONFIG Module Register Manual
Table 20-1382 CFG_MCASP1_ACLKX_OEN
Address Offset0x0000 03B8
Physical Address0x4844 A3B8InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp1_aclkx_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1383 Register Call Summary for Register CFG_MCASP1_ACLKX_OEN
IODELAYCONFIG Module Register Manual
Table 20-1384 CFG_MCASP1_ACLKX_OUT
Address Offset0x0000 03BC
Physical Address0x4844 A3BCInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp1_aclkx_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1385 Register Call Summary for Register CFG_MCASP1_ACLKX_OUT
IODELAYCONFIG Module Register Manual
Table 20-1386 CFG_MCASP1_AXR0_IN
Address Offset0x0000 03C0
Physical Address0x4844 A3C0InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp1_axr0_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1387 Register Call Summary for Register CFG_MCASP1_AXR0_IN
IODELAYCONFIG Module Register Manual
Table 20-1388 CFG_MCASP1_AXR0_OEN
Address Offset0x0000 03C4
Physical Address0x4844 A3C4InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp1_axr0_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1389 Register Call Summary for Register CFG_MCASP1_AXR0_OEN
IODELAYCONFIG Module Register Manual
Table 20-1390 CFG_MCASP1_AXR0_OUT
Address Offset0x0000 03C8
Physical Address0x4844 A3C8InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp1_axr0_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1391 Register Call Summary for Register CFG_MCASP1_AXR0_OUT
IODELAYCONFIG Module Register Manual
Table 20-1392 CFG_MCASP1_AXR10_IN
Address Offset0x0000 03CC
Physical Address0x4844 A3CCInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp1_axr10_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1393 Register Call Summary for Register CFG_MCASP1_AXR10_IN
IODELAYCONFIG Module Register Manual
Table 20-1394 CFG_MCASP1_AXR10_OEN
Address Offset0x0000 03D0
Physical Address0x4844 A3D0InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp1_axr10_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1395 Register Call Summary for Register CFG_MCASP1_AXR10_OEN
IODELAYCONFIG Module Register Manual
Table 20-1396 CFG_MCASP1_AXR10_OUT
Address Offset0x0000 03D4
Physical Address0x4844 A3D4InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp1_axr10_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1397 Register Call Summary for Register CFG_MCASP1_AXR10_OUT
IODELAYCONFIG Module Register Manual
Table 20-1398 CFG_MCASP1_AXR11_IN
Address Offset0x0000 03D8
Physical Address0x4844 A3D8InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp1_axr11_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1399 Register Call Summary for Register CFG_MCASP1_AXR11_IN
IODELAYCONFIG Module Register Manual
Table 20-1400 CFG_MCASP1_AXR11_OEN
Address Offset0x0000 03DC
Physical Address0x4844 A3DCInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp1_axr11_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1401 Register Call Summary for Register CFG_MCASP1_AXR11_OEN
IODELAYCONFIG Module Register Manual
Table 20-1402 CFG_MCASP1_AXR11_OUT
Address Offset0x0000 03E0
Physical Address0x4844 A3E0InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp1_axr11_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1403 Register Call Summary for Register CFG_MCASP1_AXR11_OUT
IODELAYCONFIG Module Register Manual
Table 20-1404 CFG_MCASP1_AXR12_IN
Address Offset0x0000 03E4
Physical Address0x4844 A3E4InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp1_axr12_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1405 Register Call Summary for Register CFG_MCASP1_AXR12_IN
IODELAYCONFIG Module Register Manual
Table 20-1406 CFG_MCASP1_AXR12_OEN
Address Offset0x0000 03E8
Physical Address0x4844 A3E8InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp1_axr12_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1407 Register Call Summary for Register CFG_MCASP1_AXR12_OEN
IODELAYCONFIG Module Register Manual
Table 20-1408 CFG_MCASP1_AXR12_OUT
Address Offset0x0000 03EC
Physical Address0x4844 A3ECInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp1_axr12_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1409 Register Call Summary for Register CFG_MCASP1_AXR12_OUT
IODELAYCONFIG Module Register Manual
Table 20-1410 CFG_MCASP1_AXR13_IN
Address Offset0x0000 03F0
Physical Address0x4844 A3F0InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp1_axr13_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1411 Register Call Summary for Register CFG_MCASP1_AXR13_IN
IODELAYCONFIG Module Register Manual
Table 20-1412 CFG_MCASP1_AXR13_OEN
Address Offset0x0000 03F4
Physical Address0x4844 A3F4InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp1_axr13_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1413 Register Call Summary for Register CFG_MCASP1_AXR13_OEN
IODELAYCONFIG Module Register Manual
Table 20-1414 CFG_MCASP1_AXR13_OUT
Address Offset0x0000 03F8
Physical Address0x4844 A3F8InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp1_axr13_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1415 Register Call Summary for Register CFG_MCASP1_AXR13_OUT
IODELAYCONFIG Module Register Manual
Table 20-1416 CFG_MCASP1_AXR14_IN
Address Offset0x0000 03FC
Physical Address0x4844 A3FCInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp1_axr14_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1417 Register Call Summary for Register CFG_MCASP1_AXR14_IN
IODELAYCONFIG Module Register Manual
Table 20-1418 CFG_MCASP1_AXR14_OEN
Address Offset0x0000 0400
Physical Address0x4844 A400InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp1_axr14_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1419 Register Call Summary for Register CFG_MCASP1_AXR14_OEN
IODELAYCONFIG Module Register Manual
Table 20-1420 CFG_MCASP1_AXR14_OUT
Address Offset0x0000 0404
Physical Address0x4844 A404InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp1_axr14_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1421 Register Call Summary for Register CFG_MCASP1_AXR14_OUT
IODELAYCONFIG Module Register Manual
Table 20-1422 CFG_MCASP1_AXR15_IN
Address Offset0x0000 0408
Physical Address0x4844 A408InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp1_axr15_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1423 Register Call Summary for Register CFG_MCASP1_AXR15_IN
IODELAYCONFIG Module Register Manual
Table 20-1424 CFG_MCASP1_AXR15_OEN
Address Offset0x0000 040C
Physical Address0x4844 A40CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp1_axr15_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1425 Register Call Summary for Register CFG_MCASP1_AXR15_OEN
IODELAYCONFIG Module Register Manual
Table 20-1426 CFG_MCASP1_AXR15_OUT
Address Offset0x0000 0410
Physical Address0x4844 A410InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp1_axr15_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1427 Register Call Summary for Register CFG_MCASP1_AXR15_OUT
IODELAYCONFIG Module Register Manual
Table 20-1428 CFG_MCASP1_AXR1_IN
Address Offset0x0000 0414
Physical Address0x4844 A414InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp1_axr1_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1429 Register Call Summary for Register CFG_MCASP1_AXR1_IN
IODELAYCONFIG Module Register Manual
Table 20-1430 CFG_MCASP1_AXR1_OEN
Address Offset0x0000 0418
Physical Address0x4844 A418InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp1_axr1_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1431 Register Call Summary for Register CFG_MCASP1_AXR1_OEN
IODELAYCONFIG Module Register Manual
Table 20-1432 CFG_MCASP1_AXR1_OUT
Address Offset0x0000 041C
Physical Address0x4844 A41CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp1_axr1_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1433 Register Call Summary for Register CFG_MCASP1_AXR1_OUT
IODELAYCONFIG Module Register Manual
Table 20-1434 CFG_MCASP1_AXR2_IN
Address Offset0x0000 0420
Physical Address0x4844 A420InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp1_axr2_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1435 Register Call Summary for Register CFG_MCASP1_AXR2_IN
IODELAYCONFIG Module Register Manual
Table 20-1436 CFG_MCASP1_AXR2_OEN
Address Offset0x0000 0424
Physical Address0x4844 A424InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp1_axr2_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1437 Register Call Summary for Register CFG_MCASP1_AXR2_OEN
IODELAYCONFIG Module Register Manual
Table 20-1438 CFG_MCASP1_AXR2_OUT
Address Offset0x0000 0428
Physical Address0x4844 A428InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp1_axr2_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1439 Register Call Summary for Register CFG_MCASP1_AXR2_OUT
IODELAYCONFIG Module Register Manual
Table 20-1440 CFG_MCASP1_AXR3_IN
Address Offset0x0000 042C
Physical Address0x4844 A42CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp1_axr3_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1441 Register Call Summary for Register CFG_MCASP1_AXR3_IN
IODELAYCONFIG Module Register Manual
Table 20-1442 CFG_MCASP1_AXR3_OEN
Address Offset0x0000 0430
Physical Address0x4844 A430InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp1_axr3_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1443 Register Call Summary for Register CFG_MCASP1_AXR3_OEN
IODELAYCONFIG Module Register Manual
Table 20-1444 CFG_MCASP1_AXR3_OUT
Address Offset0x0000 0434
Physical Address0x4844 A434InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp1_axr3_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1445 Register Call Summary for Register CFG_MCASP1_AXR3_OUT
IODELAYCONFIG Module Register Manual
Table 20-1446 CFG_MCASP1_AXR4_IN
Address Offset0x0000 0438
Physical Address0x4844 A438InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp1_axr4_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1447 Register Call Summary for Register CFG_MCASP1_AXR4_IN
IODELAYCONFIG Module Register Manual
Table 20-1448 CFG_MCASP1_AXR4_OEN
Address Offset0x0000 043C
Physical Address0x4844 A43CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp1_axr4_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1449 Register Call Summary for Register CFG_MCASP1_AXR4_OEN
IODELAYCONFIG Module Register Manual
Table 20-1450 CFG_MCASP1_AXR4_OUT
Address Offset0x0000 0440
Physical Address0x4844 A440InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp1_axr4_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1451 Register Call Summary for Register CFG_MCASP1_AXR4_OUT
IODELAYCONFIG Module Register Manual
Table 20-1452 CFG_MCASP1_AXR5_IN
Address Offset0x0000 0444
Physical Address0x4844 A444InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp1_axr5_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1453 Register Call Summary for Register CFG_MCASP1_AXR5_IN
IODELAYCONFIG Module Register Manual
Table 20-1454 CFG_MCASP1_AXR5_OEN
Address Offset0x0000 0448
Physical Address0x4844 A448InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp1_axr5_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1455 Register Call Summary for Register CFG_MCASP1_AXR5_OEN
IODELAYCONFIG Module Register Manual
Table 20-1456 CFG_MCASP1_AXR5_OUT
Address Offset0x0000 044C
Physical Address0x4844 A44CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp1_axr5_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1457 Register Call Summary for Register CFG_MCASP1_AXR5_OUT
IODELAYCONFIG Module Register Manual
Table 20-1458 CFG_MCASP1_AXR6_IN
Address Offset0x0000 0450
Physical Address0x4844 A450InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp1_axr6_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1459 Register Call Summary for Register CFG_MCASP1_AXR6_IN
IODELAYCONFIG Module Register Manual
Table 20-1460 CFG_MCASP1_AXR6_OEN
Address Offset0x0000 0454
Physical Address0x4844 A454InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp1_axr6_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1461 Register Call Summary for Register CFG_MCASP1_AXR6_OEN
IODELAYCONFIG Module Register Manual
Table 20-1462 CFG_MCASP1_AXR6_OUT
Address Offset0x0000 0458
Physical Address0x4844 A458InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp1_axr6_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1463 Register Call Summary for Register CFG_MCASP1_AXR6_OUT
IODELAYCONFIG Module Register Manual
Table 20-1464 CFG_MCASP1_AXR7_IN
Address Offset0x0000 045C
Physical Address0x4844 A45CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp1_axr7_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1465 Register Call Summary for Register CFG_MCASP1_AXR7_IN
IODELAYCONFIG Module Register Manual
Table 20-1466 CFG_MCASP1_AXR7_OEN
Address Offset0x0000 0460
Physical Address0x4844 A460InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp1_axr7_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1467 Register Call Summary for Register CFG_MCASP1_AXR7_OEN
IODELAYCONFIG Module Register Manual
Table 20-1468 CFG_MCASP1_AXR7_OUT
Address Offset0x0000 0464
Physical Address0x4844 A464InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp1_axr7_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1469 Register Call Summary for Register CFG_MCASP1_AXR7_OUT
IODELAYCONFIG Module Register Manual
Table 20-1470 CFG_MCASP1_AXR8_IN
Address Offset0x0000 0468
Physical Address0x4844 A468InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp1_axr8_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1471 Register Call Summary for Register CFG_MCASP1_AXR8_IN
IODELAYCONFIG Module Register Manual
Table 20-1472 CFG_MCASP1_AXR8_OEN
Address Offset0x0000 046C
Physical Address0x4844 A46CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp1_axr8_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1473 Register Call Summary for Register CFG_MCASP1_AXR8_OEN
IODELAYCONFIG Module Register Manual
Table 20-1474 CFG_MCASP1_AXR8_OUT
Address Offset0x0000 0470
Physical Address0x4844 A470InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp1_axr8_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1475 Register Call Summary for Register CFG_MCASP1_AXR8_OUT
IODELAYCONFIG Module Register Manual
Table 20-1476 CFG_MCASP1_AXR9_IN
Address Offset0x0000 0474
Physical Address0x4844 A474InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp1_axr9_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1477 Register Call Summary for Register CFG_MCASP1_AXR9_IN
IODELAYCONFIG Module Register Manual
Table 20-1478 CFG_MCASP1_AXR9_OEN
Address Offset0x0000 0478
Physical Address0x4844 A478InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp1_axr9_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1479 Register Call Summary for Register CFG_MCASP1_AXR9_OEN
IODELAYCONFIG Module Register Manual
Table 20-1480 CFG_MCASP1_AXR9_OUT
Address Offset0x0000 047C
Physical Address0x4844 A47CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp1_axr9_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1481 Register Call Summary for Register CFG_MCASP1_AXR9_OUT
IODELAYCONFIG Module Register Manual
Table 20-1482 CFG_MCASP1_FSR_IN
Address Offset0x0000 0480
Physical Address0x4844 A480InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp1_fsr_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1483 Register Call Summary for Register CFG_MCASP1_FSR_IN
IODELAYCONFIG Module Register Manual
Table 20-1484 CFG_MCASP1_FSR_OEN
Address Offset0x0000 0484
Physical Address0x4844 A484InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp1_fsr_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1485 Register Call Summary for Register CFG_MCASP1_FSR_OEN
IODELAYCONFIG Module Register Manual
Table 20-1486 CFG_MCASP1_FSR_OUT
Address Offset0x0000 0488
Physical Address0x4844 A488InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp1_fsr_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1487 Register Call Summary for Register CFG_MCASP1_FSR_OUT
IODELAYCONFIG Module Register Manual
Table 20-1488 CFG_MCASP1_FSX_IN
Address Offset0x0000 048C
Physical Address0x4844 A48CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp1_fsx_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1489 Register Call Summary for Register CFG_MCASP1_FSX_IN
IODELAYCONFIG Module Register Manual
Table 20-1490 CFG_MCASP1_FSX_OEN
Address Offset0x0000 0490
Physical Address0x4844 A490InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp1_fsx_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1491 Register Call Summary for Register CFG_MCASP1_FSX_OEN
IODELAYCONFIG Module Register Manual
Table 20-1492 CFG_MCASP1_FSX_OUT
Address Offset0x0000 0494
Physical Address0x4844 A494InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp1_fsx_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1493 Register Call Summary for Register CFG_MCASP1_FSX_OUT
IODELAYCONFIG Module Register Manual
Table 20-1494 CFG_MCASP2_ACLKR_IN
Address Offset0x0000 0498
Physical Address0x4844 A498InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp2_aclkr_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1495 Register Call Summary for Register CFG_MCASP2_ACLKR_IN
IODELAYCONFIG Module Register Manual
Table 20-1496 CFG_MCASP2_ACLKR_OEN
Address Offset0x0000 049C
Physical Address0x4844 A49CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp2_aclkr_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1497 Register Call Summary for Register CFG_MCASP2_ACLKR_OEN
IODELAYCONFIG Module Register Manual
Table 20-1498 CFG_MCASP2_ACLKR_OUT
Address Offset0x0000 04A0
Physical Address0x4844 A4A0InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp2_aclkr_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1499 Register Call Summary for Register CFG_MCASP2_ACLKR_OUT
IODELAYCONFIG Module Register Manual
Table 20-1500 CFG_MCASP2_ACLKX_IN
Address Offset0x0000 04A4
Physical Address0x4844 A4A4InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp2_aclkx_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1501 Register Call Summary for Register CFG_MCASP2_ACLKX_IN
IODELAYCONFIG Module Register Manual
Table 20-1502 CFG_MCASP2_ACLKX_OEN
Address Offset0x0000 04A8
Physical Address0x4844 A4A8InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp2_aclkx_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1503 Register Call Summary for Register CFG_MCASP2_ACLKX_OEN
IODELAYCONFIG Module Register Manual
Table 20-1504 CFG_MCASP2_ACLKX_OUT
Address Offset0x0000 04AC
Physical Address0x4844 A4ACInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp2_aclkx_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1505 Register Call Summary for Register CFG_MCASP2_ACLKX_OUT
IODELAYCONFIG Module Register Manual
Table 20-1506 CFG_MCASP2_AXR0_IN
Address Offset0x0000 04B0
Physical Address0x4844 A4B0InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp2_axr0_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1507 Register Call Summary for Register CFG_MCASP2_AXR0_IN
IODELAYCONFIG Module Register Manual
Table 20-1508 CFG_MCASP2_AXR0_OEN
Address Offset0x0000 04B4
Physical Address0x4844 A4B4InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp2_axr0_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1509 Register Call Summary for Register CFG_MCASP2_AXR0_OEN
IODELAYCONFIG Module Register Manual
Table 20-1510 CFG_MCASP2_AXR0_OUT
Address Offset0x0000 04B8
Physical Address0x4844 A4B8InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp2_axr0_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1511 Register Call Summary for Register CFG_MCASP2_AXR0_OUT
IODELAYCONFIG Module Register Manual
Table 20-1512 CFG_MCASP2_AXR1_IN
Address Offset0x0000 04BC
Physical Address0x4844 A4BCInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp2_axr1_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1513 Register Call Summary for Register CFG_MCASP2_AXR1_IN
IODELAYCONFIG Module Register Manual
Table 20-1514 CFG_MCASP2_AXR1_OEN
Address Offset0x0000 04C0
Physical Address0x4844 A4C0InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp2_axr1_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1515 Register Call Summary for Register CFG_MCASP2_AXR1_OEN
IODELAYCONFIG Module Register Manual
Table 20-1516 CFG_MCASP2_AXR1_OUT
Address Offset0x0000 04C4
Physical Address0x4844 A4C4InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp2_axr1_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1517 Register Call Summary for Register CFG_MCASP2_AXR1_OUT
IODELAYCONFIG Module Register Manual
Table 20-1518 CFG_MCASP2_AXR2_IN
Address Offset0x0000 04C8
Physical Address0x4844 A4C8InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp2_axr2_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1519 Register Call Summary for Register CFG_MCASP2_AXR2_IN
IODELAYCONFIG Module Register Manual
Table 20-1520 CFG_MCASP2_AXR2_OEN
Address Offset0x0000 04CC
Physical Address0x4844 A4CCInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp2_axr2_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1521 Register Call Summary for Register CFG_MCASP2_AXR2_OEN
IODELAYCONFIG Module Register Manual
Table 20-1522 CFG_MCASP2_AXR2_OUT
Address Offset0x0000 04D0
Physical Address0x4844 A4D0InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp2_axr2_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1523 Register Call Summary for Register CFG_MCASP2_AXR2_OUT
IODELAYCONFIG Module Register Manual
Table 20-1524 CFG_MCASP2_AXR3_IN
Address Offset0x0000 04D4
Physical Address0x4844 A4D4InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp2_axr3_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1525 Register Call Summary for Register CFG_MCASP2_AXR3_IN
IODELAYCONFIG Module Register Manual
Table 20-1526 CFG_MCASP2_AXR3_OEN
Address Offset0x0000 04D8
Physical Address0x4844 A4D8InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp2_axr3_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1527 Register Call Summary for Register CFG_MCASP2_AXR3_OEN
IODELAYCONFIG Module Register Manual
Table 20-1528 CFG_MCASP2_AXR3_OUT
Address Offset0x0000 04DC
Physical Address0x4844 A4DCInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp2_axr3_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1529 Register Call Summary for Register CFG_MCASP2_AXR3_OUT
IODELAYCONFIG Module Register Manual
Table 20-1530 CFG_MCASP2_AXR4_IN
Address Offset0x0000 04E0
Physical Address0x4844 A4E0InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp2_axr4_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1531 Register Call Summary for Register CFG_MCASP2_AXR4_IN
IODELAYCONFIG Module Register Manual
Table 20-1532 CFG_MCASP2_AXR4_OEN
Address Offset0x0000 04E4
Physical Address0x4844 A4E4InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp2_axr4_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1533 Register Call Summary for Register CFG_MCASP2_AXR4_OEN
IODELAYCONFIG Module Register Manual
Table 20-1534 CFG_MCASP2_AXR4_OUT
Address Offset0x0000 04E8
Physical Address0x4844 A4E8InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp2_axr4_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1535 Register Call Summary for Register CFG_MCASP2_AXR4_OUT
IODELAYCONFIG Module Register Manual
Table 20-1536 CFG_MCASP2_AXR5_IN
Address Offset0x0000 04EC
Physical Address0x4844 A4ECInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp2_axr5_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1537 Register Call Summary for Register CFG_MCASP2_AXR5_IN
IODELAYCONFIG Module Register Manual
Table 20-1538 CFG_MCASP2_AXR5_OEN
Address Offset0x0000 04F0
Physical Address0x4844 A4F0InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp2_axr5_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1539 Register Call Summary for Register CFG_MCASP2_AXR5_OEN
IODELAYCONFIG Module Register Manual
Table 20-1540 CFG_MCASP2_AXR5_OUT
Address Offset0x0000 04F4
Physical Address0x4844 A4F4InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp2_axr5_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1541 Register Call Summary for Register CFG_MCASP2_AXR5_OUT
IODELAYCONFIG Module Register Manual
Table 20-1542 CFG_MCASP2_AXR6_IN
Address Offset0x0000 04F8
Physical Address0x4844 A4F8InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp2_axr6_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1543 Register Call Summary for Register CFG_MCASP2_AXR6_IN
IODELAYCONFIG Module Register Manual
Table 20-1544 CFG_MCASP2_AXR6_OEN
Address Offset0x0000 04FC
Physical Address0x4844 A4FCInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp2_axr6_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1545 Register Call Summary for Register CFG_MCASP2_AXR6_OEN
IODELAYCONFIG Module Register Manual
Table 20-1546 CFG_MCASP2_AXR6_OUT
Address Offset0x0000 0500
Physical Address0x4844 A500InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp2_axr6_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1547 Register Call Summary for Register CFG_MCASP2_AXR6_OUT
IODELAYCONFIG Module Register Manual
Table 20-1548 CFG_MCASP2_AXR7_IN
Address Offset0x0000 0504
Physical Address0x4844 A504InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp2_axr7_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1549 Register Call Summary for Register CFG_MCASP2_AXR7_IN
IODELAYCONFIG Module Register Manual
Table 20-1550 CFG_MCASP2_AXR7_OEN
Address Offset0x0000 0508
Physical Address0x4844 A508InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp2_axr7_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1551 Register Call Summary for Register CFG_MCASP2_AXR7_OEN
IODELAYCONFIG Module Register Manual
Table 20-1552 CFG_MCASP2_AXR7_OUT
Address Offset0x0000 050C
Physical Address0x4844 A50CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp2_axr7_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1553 Register Call Summary for Register CFG_MCASP2_AXR7_OUT
IODELAYCONFIG Module Register Manual
Table 20-1554 CFG_MCASP2_FSR_IN
Address Offset0x0000 0510
Physical Address0x4844 A510InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp2_fsr_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1555 Register Call Summary for Register CFG_MCASP2_FSR_IN
IODELAYCONFIG Module Register Manual
Table 20-1556 CFG_MCASP2_FSR_OEN
Address Offset0x0000 0514
Physical Address0x4844 A514InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp2_fsr_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1557 Register Call Summary for Register CFG_MCASP2_FSR_OEN
IODELAYCONFIG Module Register Manual
Table 20-1558 CFG_MCASP2_FSR_OUT
Address Offset0x0000 0518
Physical Address0x4844 A518InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp2_fsr_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1559 Register Call Summary for Register CFG_MCASP2_FSR_OUT
IODELAYCONFIG Module Register Manual
Table 20-1560 CFG_MCASP2_FSX_IN
Address Offset0x0000 051C
Physical Address0x4844 A51CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp2_fsx_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1561 Register Call Summary for Register CFG_MCASP2_FSX_IN
IODELAYCONFIG Module Register Manual
Table 20-1562 CFG_MCASP2_FSX_OEN
Address Offset0x0000 0520
Physical Address0x4844 A520InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp2_fsx_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1563 Register Call Summary for Register CFG_MCASP2_FSX_OEN
IODELAYCONFIG Module Register Manual
Table 20-1564 CFG_MCASP2_FSX_OUT
Address Offset0x0000 0524
Physical Address0x4844 A524InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp2_fsx_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1565 Register Call Summary for Register CFG_MCASP2_FSX_OUT
IODELAYCONFIG Module Register Manual
Table 20-1566 CFG_MCASP3_ACLKX_IN
Address Offset0x0000 0528
Physical Address0x4844 A528InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp3_aclkx_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1567 Register Call Summary for Register CFG_MCASP3_ACLKX_IN
IODELAYCONFIG Module Register Manual
Table 20-1568 CFG_MCASP3_ACLKX_OEN
Address Offset0x0000 052C
Physical Address0x4844 A52CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp3_aclkx_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1569 Register Call Summary for Register CFG_MCASP3_ACLKX_OEN
IODELAYCONFIG Module Register Manual
Table 20-1570 CFG_MCASP3_ACLKX_OUT
Address Offset0x0000 0530
Physical Address0x4844 A530InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp3_aclkx_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1571 Register Call Summary for Register CFG_MCASP3_ACLKX_OUT
IODELAYCONFIG Module Register Manual
Table 20-1572 CFG_MCASP3_AXR0_IN
Address Offset0x0000 0534
Physical Address0x4844 A534InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp3_axr0_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1573 Register Call Summary for Register CFG_MCASP3_AXR0_IN
IODELAYCONFIG Module Register Manual
Table 20-1574 CFG_MCASP3_AXR0_OEN
Address Offset0x0000 0538
Physical Address0x4844 A538InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp3_axr0_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1575 Register Call Summary for Register CFG_MCASP3_AXR0_OEN
IODELAYCONFIG Module Register Manual
Table 20-1576 CFG_MCASP3_AXR0_OUT
Address Offset0x0000 053C
Physical Address0x4844 A53CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp3_axr0_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1577 Register Call Summary for Register CFG_MCASP3_AXR0_OUT
IODELAYCONFIG Module Register Manual
Table 20-1578 CFG_MCASP3_AXR1_IN
Address Offset0x0000 0540
Physical Address0x4844 A540InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp3_axr1_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1579 Register Call Summary for Register CFG_MCASP3_AXR1_IN
IODELAYCONFIG Module Register Manual
Table 20-1580 CFG_MCASP3_AXR1_OEN
Address Offset0x0000 0544
Physical Address0x4844 A544InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp3_axr1_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1581 Register Call Summary for Register CFG_MCASP3_AXR1_OEN
IODELAYCONFIG Module Register Manual
Table 20-1582 CFG_MCASP3_AXR1_OUT
Address Offset0x0000 0548
Physical Address0x4844 A548InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp3_axr1_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1583 Register Call Summary for Register CFG_MCASP3_AXR1_OUT
IODELAYCONFIG Module Register Manual
Table 20-1584 CFG_MCASP3_FSX_IN
Address Offset0x0000 054C
Physical Address0x4844 A54CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp3_fsx_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1585 Register Call Summary for Register CFG_MCASP3_FSX_IN
IODELAYCONFIG Module Register Manual
Table 20-1586 CFG_MCASP3_FSX_OEN
Address Offset0x0000 0550
Physical Address0x4844 A550InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp3_fsx_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1587 Register Call Summary for Register CFG_MCASP3_FSX_OEN
IODELAYCONFIG Module Register Manual
Table 20-1588 CFG_MCASP3_FSX_OUT
Address Offset0x0000 0554
Physical Address0x4844 A554InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp3_fsx_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1589 Register Call Summary for Register CFG_MCASP3_FSX_OUT
IODELAYCONFIG Module Register Manual
Table 20-1590 CFG_MCASP4_ACLKX_IN
Address Offset0x0000 0558
Physical Address0x4844 A558InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp4_aclkx_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1591 Register Call Summary for Register CFG_MCASP4_ACLKX_IN
IODELAYCONFIG Module Register Manual
Table 20-1592 CFG_MCASP4_ACLKX_OEN
Address Offset0x0000 055C
Physical Address0x4844 A55CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp4_aclkx_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1593 Register Call Summary for Register CFG_MCASP4_ACLKX_OEN
IODELAYCONFIG Module Register Manual
Table 20-1594 CFG_MCASP4_ACLKX_OUT
Address Offset0x0000 0560
Physical Address0x4844 A560InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp4_aclkx_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1595 Register Call Summary for Register CFG_MCASP4_ACLKX_OUT
IODELAYCONFIG Module Register Manual
Table 20-1596 CFG_MCASP4_AXR0_IN
Address Offset0x0000 0564
Physical Address0x4844 A564InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp4_axr0_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1597 Register Call Summary for Register CFG_MCASP4_AXR0_IN
IODELAYCONFIG Module Register Manual
Table 20-1598 CFG_MCASP4_AXR0_OEN
Address Offset0x0000 0568
Physical Address0x4844 A568InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp4_axr0_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1599 Register Call Summary for Register CFG_MCASP4_AXR0_OEN
IODELAYCONFIG Module Register Manual
Table 20-1600 CFG_MCASP4_AXR0_OUT
Address Offset0x0000 056C
Physical Address0x4844 A56CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp4_axr0_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1601 Register Call Summary for Register CFG_MCASP4_AXR0_OUT
IODELAYCONFIG Module Register Manual
Table 20-1602 CFG_MCASP4_AXR1_IN
Address Offset0x0000 0570
Physical Address0x4844 A570InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp4_axr1_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1603 Register Call Summary for Register CFG_MCASP4_AXR1_IN
IODELAYCONFIG Module Register Manual
Table 20-1604 CFG_MCASP4_AXR1_OEN
Address Offset0x0000 0574
Physical Address0x4844 A574InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp4_axr1_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1605 Register Call Summary for Register CFG_MCASP4_AXR1_OEN
IODELAYCONFIG Module Register Manual
Table 20-1606 CFG_MCASP4_AXR1_OUT
Address Offset0x0000 0578
Physical Address0x4844 A578InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp4_axr1_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1607 Register Call Summary for Register CFG_MCASP4_AXR1_OUT
IODELAYCONFIG Module Register Manual
Table 20-1608 CFG_MCASP4_FSX_IN
Address Offset0x0000 057C
Physical Address0x4844 A57CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp4_fsx_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1609 Register Call Summary for Register CFG_MCASP4_FSX_IN
IODELAYCONFIG Module Register Manual
Table 20-1610 CFG_MCASP4_FSX_OEN
Address Offset0x0000 0580
Physical Address0x4844 A580InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp4_fsx_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1611 Register Call Summary for Register CFG_MCASP4_FSX_OEN
IODELAYCONFIG Module Register Manual
Table 20-1612 CFG_MCASP4_FSX_OUT
Address Offset0x0000 0584
Physical Address0x4844 A584InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp4_fsx_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1613 Register Call Summary for Register CFG_MCASP4_FSX_OUT
IODELAYCONFIG Module Register Manual
Table 20-1614 CFG_MCASP5_ACLKX_IN
Address Offset0x0000 0588
Physical Address0x4844 A588InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp5_aclkx_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1615 Register Call Summary for Register CFG_MCASP5_ACLKX_IN
IODELAYCONFIG Module Register Manual
Table 20-1616 CFG_MCASP5_ACLKX_OEN
Address Offset0x0000 058C
Physical Address0x4844 A58CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp5_aclkx_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1617 Register Call Summary for Register CFG_MCASP5_ACLKX_OEN
IODELAYCONFIG Module Register Manual
Table 20-1618 CFG_MCASP5_ACLKX_OUT
Address Offset0x0000 0590
Physical Address0x4844 A590InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp5_aclkx_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1619 Register Call Summary for Register CFG_MCASP5_ACLKX_OUT
IODELAYCONFIG Module Register Manual
Table 20-1620 CFG_MCASP5_AXR0_IN
Address Offset0x0000 0594
Physical Address0x4844 A594InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp5_axr0_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1621 Register Call Summary for Register CFG_MCASP5_AXR0_IN
IODELAYCONFIG Module Register Manual
Table 20-1622 CFG_MCASP5_AXR0_OEN
Address Offset0x0000 0598
Physical Address0x4844 A598InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp5_axr0_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1623 Register Call Summary for Register CFG_MCASP5_AXR0_OEN
IODELAYCONFIG Module Register Manual
Table 20-1624 CFG_MCASP5_AXR0_OUT
Address Offset0x0000 059C
Physical Address0x4844 A59CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp5_axr0_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1625 Register Call Summary for Register CFG_MCASP5_AXR0_OUT
IODELAYCONFIG Module Register Manual
Table 20-1626 CFG_MCASP5_AXR1_IN
Address Offset0x0000 05A0
Physical Address0x4844 A5A0InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp5_axr1_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1627 Register Call Summary for Register CFG_MCASP5_AXR1_IN
IODELAYCONFIG Module Register Manual
Table 20-1628 CFG_MCASP5_AXR1_OEN
Address Offset0x0000 05A4
Physical Address0x4844 A5A4InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp5_axr1_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1629 Register Call Summary for Register CFG_MCASP5_AXR1_OEN
IODELAYCONFIG Module Register Manual
Table 20-1630 CFG_MCASP5_AXR1_OUT
Address Offset0x0000 05A8
Physical Address0x4844 A5A8InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp5_axr1_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1631 Register Call Summary for Register CFG_MCASP5_AXR1_OUT
IODELAYCONFIG Module Register Manual
Table 20-1632 CFG_MCASP5_FSX_IN
Address Offset0x0000 05AC
Physical Address0x4844 A5ACInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp5_fsx_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1633 Register Call Summary for Register CFG_MCASP5_FSX_IN
IODELAYCONFIG Module Register Manual
Table 20-1634 CFG_MCASP5_FSX_OEN
Address Offset0x0000 05B0
Physical Address0x4844 A5B0InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp5_fsx_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1635 Register Call Summary for Register CFG_MCASP5_FSX_OEN
IODELAYCONFIG Module Register Manual
Table 20-1636 CFG_MCASP5_FSX_OUT
Address Offset0x0000 05B4
Physical Address0x4844 A5B4InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mcasp5_fsx_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1637 Register Call Summary for Register CFG_MCASP5_FSX_OUT
IODELAYCONFIG Module Register Manual
Table 20-1638 CFG_MDIO_D_IN
Address Offset0x0000 05B8
Physical Address0x4844 A5B8InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mdio_d_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1639 Register Call Summary for Register CFG_MDIO_D_IN
IODELAYCONFIG Module Register Manual
Table 20-1640 CFG_MDIO_D_OEN
Address Offset0x0000 05BC
Physical Address0x4844 A5BCInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mdio_d_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1641 Register Call Summary for Register CFG_MDIO_D_OEN
IODELAYCONFIG Module Register Manual
Table 20-1642 CFG_MDIO_D_OUT
Address Offset0x0000 05C0
Physical Address0x4844 A5C0InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mdio_d_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1643 Register Call Summary for Register CFG_MDIO_D_OUT
IODELAYCONFIG Module Register Manual
Table 20-1644 CFG_MDIO_MCLK_IN
Address Offset0x0000 05C4
Physical Address0x4844 A5C4InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mdio_mclk_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1645 Register Call Summary for Register CFG_MDIO_MCLK_IN
IODELAYCONFIG Module Register Manual
Table 20-1646 CFG_MDIO_MCLK_OEN
Address Offset0x0000 05C8
Physical Address0x4844 A5C8InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mdio_mclk_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1647 Register Call Summary for Register CFG_MDIO_MCLK_OEN
IODELAYCONFIG Module Register Manual
Table 20-1648 CFG_MDIO_MCLK_OUT
Address Offset0x0000 05CC
Physical Address0x4844 A5CCInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mdio_mclk_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1649 Register Call Summary for Register CFG_MDIO_MCLK_OUT
IODELAYCONFIG Module Register Manual
Table 20-1650 CFG_MLBP_CLK_N_IN
Address Offset0x0000 05D0
Physical Address0x4844 A5D0InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mlbp_clk_n_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1651 Register Call Summary for Register CFG_MLBP_CLK_N_IN
IODELAYCONFIG Module Register Manual
Table 20-1652 CFG_MLBP_CLK_N_OEN
Address Offset0x0000 05D4
Physical Address0x4844 A5D4InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mlbp_clk_n_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1653 Register Call Summary for Register CFG_MLBP_CLK_N_OEN
IODELAYCONFIG Module Register Manual
Table 20-1654 CFG_MLBP_CLK_N_OUT
Address Offset0x0000 05D8
Physical Address0x4844 A5D8InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mlbp_clk_n_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1655 Register Call Summary for Register CFG_MLBP_CLK_N_OUT
IODELAYCONFIG Module Register Manual
Table 20-1656 CFG_MLBP_CLK_P_IN
Address Offset0x0000 05DC
Physical Address0x4844 A5DCInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mlbp_clk_p_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1657 Register Call Summary for Register CFG_MLBP_CLK_P_IN
IODELAYCONFIG Module Register Manual
Table 20-1658 CFG_MLBP_CLK_P_OEN
Address Offset0x0000 05E0
Physical Address0x4844 A5E0InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mlbp_clk_p_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1659 Register Call Summary for Register CFG_MLBP_CLK_P_OEN
IODELAYCONFIG Module Register Manual
Table 20-1660 CFG_MLBP_CLK_P_OUT
Address Offset0x0000 05E4
Physical Address0x4844 A5E4InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mlbp_clk_p_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1661 Register Call Summary for Register CFG_MLBP_CLK_P_OUT
IODELAYCONFIG Module Register Manual
Table 20-1662 CFG_MLBP_DAT_N_IN
Address Offset0x0000 05E8
Physical Address0x4844 A5E8InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mlbp_dat_n_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1663 Register Call Summary for Register CFG_MLBP_DAT_N_IN
IODELAYCONFIG Module Register Manual
Table 20-1664 CFG_MLBP_DAT_N_OEN
Address Offset0x0000 05EC
Physical Address0x4844 A5ECInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mlbp_dat_n_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1665 Register Call Summary for Register CFG_MLBP_DAT_N_OEN
IODELAYCONFIG Module Register Manual
Table 20-1666 CFG_MLBP_DAT_N_OUT
Address Offset0x0000 05F0
Physical Address0x4844 A5F0InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mlbp_dat_n_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1667 Register Call Summary for Register CFG_MLBP_DAT_N_OUT
IODELAYCONFIG Module Register Manual
Table 20-1668 CFG_MLBP_DAT_P_IN
Address Offset0x0000 05F4
Physical Address0x4844 A5F4InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mlbp_dat_p_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1669 Register Call Summary for Register CFG_MLBP_DAT_P_IN
IODELAYCONFIG Module Register Manual
Table 20-1670 CFG_MLBP_DAT_P_OEN
Address Offset0x0000 05F8
Physical Address0x4844 A5F8InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mlbp_dat_p_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1671 Register Call Summary for Register CFG_MLBP_DAT_P_OEN
IODELAYCONFIG Module Register Manual
Table 20-1672 CFG_MLBP_DAT_P_OUT
Address Offset0x0000 05FC
Physical Address0x4844 A5FCInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mlbp_dat_p_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1673 Register Call Summary for Register CFG_MLBP_DAT_P_OUT
IODELAYCONFIG Module Register Manual
Table 20-1674 CFG_MLBP_SIG_N_IN
Address Offset0x0000 0600
Physical Address0x4844 A600InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mlbp_sig_n_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1675 Register Call Summary for Register CFG_MLBP_SIG_N_IN
IODELAYCONFIG Module Register Manual
Table 20-1676 CFG_MLBP_SIG_N_OEN
Address Offset0x0000 0604
Physical Address0x4844 A604InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mlbp_sig_n_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1677 Register Call Summary for Register CFG_MLBP_SIG_N_OEN
IODELAYCONFIG Module Register Manual
Table 20-1678 CFG_MLBP_SIG_N_OUT
Address Offset0x0000 0608
Physical Address0x4844 A608InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mlbp_sig_n_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1679 Register Call Summary for Register CFG_MLBP_SIG_N_OUT
IODELAYCONFIG Module Register Manual
Table 20-1680 CFG_MLBP_SIG_P_IN
Address Offset0x0000 060C
Physical Address0x4844 A60CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mlbp_sig_p_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1681 Register Call Summary for Register CFG_MLBP_SIG_P_IN
IODELAYCONFIG Module Register Manual
Table 20-1682 CFG_MLBP_SIG_P_OEN
Address Offset0x0000 0610
Physical Address0x4844 A610InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mlbp_sig_p_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1683 Register Call Summary for Register CFG_MLBP_SIG_P_OEN
IODELAYCONFIG Module Register Manual
Table 20-1684 CFG_MLBP_SIG_P_OUT
Address Offset0x0000 0614
Physical Address0x4844 A614InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mlbp_sig_p_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1685 Register Call Summary for Register CFG_MLBP_SIG_P_OUT
IODELAYCONFIG Module Register Manual
Table 20-1686 CFG_MMC1_CLK_IN
Address Offset0x0000 0618
Physical Address0x4844 A618InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mmc1_clk_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1687 Register Call Summary for Register CFG_MMC1_CLK_IN
IODELAYCONFIG Module Register Manual
Table 20-1688 CFG_MMC1_CLK_OEN
Address Offset0x0000 061C
Physical Address0x4844 A61CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mmc1_clk_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1689 Register Call Summary for Register CFG_MMC1_CLK_OEN
IODELAYCONFIG Module Register Manual
Table 20-1690 CFG_MMC1_CLK_OUT
Address Offset0x0000 0620
Physical Address0x4844 A620InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mmc1_clk_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1691 Register Call Summary for Register CFG_MMC1_CLK_OUT
IODELAYCONFIG Module Register Manual
Table 20-1692 CFG_MMC1_CMD_IN
Address Offset0x0000 0624
Physical Address0x4844 A624InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mmc1_cmd_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1693 Register Call Summary for Register CFG_MMC1_CMD_IN
IODELAYCONFIG Module Register Manual
Table 20-1694 CFG_MMC1_CMD_OEN
Address Offset0x0000 0628
Physical Address0x4844 A628InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mmc1_cmd_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1695 Register Call Summary for Register CFG_MMC1_CMD_OEN
IODELAYCONFIG Module Register Manual
Table 20-1696 CFG_MMC1_CMD_OUT
Address Offset0x0000 062C
Physical Address0x4844 A62CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mmc1_cmd_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1697 Register Call Summary for Register CFG_MMC1_CMD_OUT
IODELAYCONFIG Module Register Manual
Table 20-1698 CFG_MMC1_DAT0_IN
Address Offset0x0000 0630
Physical Address0x4844 A630InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mmc1_dat0_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1699 Register Call Summary for Register CFG_MMC1_DAT0_IN
IODELAYCONFIG Module Register Manual
Table 20-1700 CFG_MMC1_DAT0_OEN
Address Offset0x0000 0634
Physical Address0x4844 A634InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mmc1_dat0_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1701 Register Call Summary for Register CFG_MMC1_DAT0_OEN
IODELAYCONFIG Module Register Manual
Table 20-1702 CFG_MMC1_DAT0_OUT
Address Offset0x0000 0638
Physical Address0x4844 A638InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mmc1_dat0_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1703 Register Call Summary for Register CFG_MMC1_DAT0_OUT
IODELAYCONFIG Module Register Manual
Table 20-1704 CFG_MMC1_DAT1_IN
Address Offset0x0000 063C
Physical Address0x4844 A63CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mmc1_dat1_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1705 Register Call Summary for Register CFG_MMC1_DAT1_IN
IODELAYCONFIG Module Register Manual
Table 20-1706 CFG_MMC1_DAT1_OEN
Address Offset0x0000 0640
Physical Address0x4844 A640InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mmc1_dat1_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1707 Register Call Summary for Register CFG_MMC1_DAT1_OEN
IODELAYCONFIG Module Register Manual
Table 20-1708 CFG_MMC1_DAT1_OUT
Address Offset0x0000 0644
Physical Address0x4844 A644InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mmc1_dat1_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1709 Register Call Summary for Register CFG_MMC1_DAT1_OUT
IODELAYCONFIG Module Register Manual
Table 20-1710 CFG_MMC1_DAT2_IN
Address Offset0x0000 0648
Physical Address0x4844 A648InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mmc1_dat2_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1711 Register Call Summary for Register CFG_MMC1_DAT2_IN
IODELAYCONFIG Module Register Manual
Table 20-1712 CFG_MMC1_DAT2_OEN
Address Offset0x0000 064C
Physical Address0x4844 A64CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mmc1_dat2_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1713 Register Call Summary for Register CFG_MMC1_DAT2_OEN
IODELAYCONFIG Module Register Manual
Table 20-1714 CFG_MMC1_DAT2_OUT
Address Offset0x0000 0650
Physical Address0x4844 A650InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mmc1_dat2_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1715 Register Call Summary for Register CFG_MMC1_DAT2_OUT
IODELAYCONFIG Module Register Manual
Table 20-1716 CFG_MMC1_DAT3_IN
Address Offset0x0000 0654
Physical Address0x4844 A654InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mmc1_dat3_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1717 Register Call Summary for Register CFG_MMC1_DAT3_IN
IODELAYCONFIG Module Register Manual
Table 20-1718 CFG_MMC1_DAT3_OEN
Address Offset0x0000 0658
Physical Address0x4844 A658InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mmc1_dat3_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1719 Register Call Summary for Register CFG_MMC1_DAT3_OEN
IODELAYCONFIG Module Register Manual
Table 20-1720 CFG_MMC1_DAT3_OUT
Address Offset0x0000 065C
Physical Address0x4844 A65CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mmc1_dat3_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1721 Register Call Summary for Register CFG_MMC1_DAT3_OUT
IODELAYCONFIG Module Register Manual
Table 20-1722 CFG_MMC1_SDCD_IN
Address Offset0x0000 0660
Physical Address0x4844 A660InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mmc1_sdcd_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1723 Register Call Summary for Register CFG_MMC1_SDCD_IN
IODELAYCONFIG Module Register Manual
Table 20-1724 CFG_MMC1_SDCD_OEN
Address Offset0x0000 0664
Physical Address0x4844 A664InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mmc1_sdcd_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1725 Register Call Summary for Register CFG_MMC1_SDCD_OEN
IODELAYCONFIG Module Register Manual
Table 20-1726 CFG_MMC1_SDCD_OUT
Address Offset0x0000 0668
Physical Address0x4844 A668InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mmc1_sdcd_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1727 Register Call Summary for Register CFG_MMC1_SDCD_OUT
IODELAYCONFIG Module Register Manual
Table 20-1728 CFG_MMC1_SDWP_IN
Address Offset0x0000 066C
Physical Address0x4844 A66CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mmc1_sdwp_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1729 Register Call Summary for Register CFG_MMC1_SDWP_IN
IODELAYCONFIG Module Register Manual
Table 20-1730 CFG_MMC1_SDWP_OEN
Address Offset0x0000 0670
Physical Address0x4844 A670InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mmc1_sdwp_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1731 Register Call Summary for Register CFG_MMC1_SDWP_OEN
IODELAYCONFIG Module Register Manual
Table 20-1732 CFG_MMC1_SDWP_OUT
Address Offset0x0000 0674
Physical Address0x4844 A674InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mmc1_sdwp_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1733 Register Call Summary for Register CFG_MMC1_SDWP_OUT
IODELAYCONFIG Module Register Manual
Table 20-1734 CFG_MMC3_CLK_IN
Address Offset0x0000 0678
Physical Address0x4844 A678InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mmc3_clk_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1735 Register Call Summary for Register CFG_MMC3_CLK_IN
IODELAYCONFIG Module Register Manual
Table 20-1736 CFG_MMC3_CLK_OEN
Address Offset0x0000 067C
Physical Address0x4844 A67CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mmc3_clk_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1737 Register Call Summary for Register CFG_MMC3_CLK_OEN
IODELAYCONFIG Module Register Manual
Table 20-1738 CFG_MMC3_CLK_OUT
Address Offset0x0000 0680
Physical Address0x4844 A680InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mmc3_clk_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1739 Register Call Summary for Register CFG_MMC3_CLK_OUT
IODELAYCONFIG Module Register Manual
Table 20-1740 CFG_MMC3_CMD_IN
Address Offset0x0000 0684
Physical Address0x4844 A684InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mmc3_cmd_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1741 Register Call Summary for Register CFG_MMC3_CMD_IN
IODELAYCONFIG Module Register Manual
Table 20-1742 CFG_MMC3_CMD_OEN
Address Offset0x0000 0688
Physical Address0x4844 A688InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mmc3_cmd_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1743 Register Call Summary for Register CFG_MMC3_CMD_OEN
IODELAYCONFIG Module Register Manual
Table 20-1744 CFG_MMC3_CMD_OUT
Address Offset0x0000 068C
Physical Address0x4844 A68CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mmc3_cmd_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1745 Register Call Summary for Register CFG_MMC3_CMD_OUT
IODELAYCONFIG Module Register Manual
Table 20-1746 CFG_MMC3_DAT0_IN
Address Offset0x0000 0690
Physical Address0x4844 A690InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mmc3_dat0_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1747 Register Call Summary for Register CFG_MMC3_DAT0_IN
IODELAYCONFIG Module Register Manual
Table 20-1748 CFG_MMC3_DAT0_OEN
Address Offset0x0000 0694
Physical Address0x4844 A694InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mmc3_dat0_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1749 Register Call Summary for Register CFG_MMC3_DAT0_OEN
IODELAYCONFIG Module Register Manual
Table 20-1750 CFG_MMC3_DAT0_OUT
Address Offset0x0000 0698
Physical Address0x4844 A698InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mmc3_dat0_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1751 Register Call Summary for Register CFG_MMC3_DAT0_OUT
IODELAYCONFIG Module Register Manual
Table 20-1752 CFG_MMC3_DAT1_IN
Address Offset0x0000 069C
Physical Address0x4844 A69CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mmc3_dat1_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1753 Register Call Summary for Register CFG_MMC3_DAT1_IN
IODELAYCONFIG Module Register Manual
Table 20-1754 CFG_MMC3_DAT1_OEN
Address Offset0x0000 06A0
Physical Address0x4844 A6A0InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mmc3_dat1_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1755 Register Call Summary for Register CFG_MMC3_DAT1_OEN
IODELAYCONFIG Module Register Manual
Table 20-1756 CFG_MMC3_DAT1_OUT
Address Offset0x0000 06A4
Physical Address0x4844 A6A4InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mmc3_dat1_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1757 Register Call Summary for Register CFG_MMC3_DAT1_OUT
IODELAYCONFIG Module Register Manual
Table 20-1758 CFG_MMC3_DAT2_IN
Address Offset0x0000 06A8
Physical Address0x4844 A6A8InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mmc3_dat2_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1759 Register Call Summary for Register CFG_MMC3_DAT2_IN
IODELAYCONFIG Module Register Manual
Table 20-1760 CFG_MMC3_DAT2_OEN
Address Offset0x0000 06AC
Physical Address0x4844 A6ACInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mmc3_dat2_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1761 Register Call Summary for Register CFG_MMC3_DAT2_OEN
IODELAYCONFIG Module Register Manual
Table 20-1762 CFG_MMC3_DAT2_OUT
Address Offset0x0000 06B0
Physical Address0x4844 A6B0InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mmc3_dat2_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1763 Register Call Summary for Register CFG_MMC3_DAT2_OUT
IODELAYCONFIG Module Register Manual
Table 20-1764 CFG_MMC3_DAT3_IN
Address Offset0x0000 06B4
Physical Address0x4844 A6B4InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mmc3_dat3_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1765 Register Call Summary for Register CFG_MMC3_DAT3_IN
IODELAYCONFIG Module Register Manual
Table 20-1766 CFG_MMC3_DAT3_OEN
Address Offset0x0000 06B8
Physical Address0x4844 A6B8InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mmc3_dat3_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1767 Register Call Summary for Register CFG_MMC3_DAT3_OEN
IODELAYCONFIG Module Register Manual
Table 20-1768 CFG_MMC3_DAT3_OUT
Address Offset0x0000 06BC
Physical Address0x4844 A6BCInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mmc3_dat3_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1769 Register Call Summary for Register CFG_MMC3_DAT3_OUT
IODELAYCONFIG Module Register Manual
Table 20-1770 CFG_MMC3_DAT4_IN
Address Offset0x0000 06C0
Physical Address0x4844 A6C0InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mmc3_dat4_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1771 Register Call Summary for Register CFG_MMC3_DAT4_IN
IODELAYCONFIG Module Register Manual
Table 20-1772 CFG_MMC3_DAT4_OEN
Address Offset0x0000 06C4
Physical Address0x4844 A6C4InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mmc3_dat4_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1773 Register Call Summary for Register CFG_MMC3_DAT4_OEN
IODELAYCONFIG Module Register Manual
Table 20-1774 CFG_MMC3_DAT4_OUT
Address Offset0x0000 06C8
Physical Address0x4844 A6C8InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mmc3_dat4_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1775 Register Call Summary for Register CFG_MMC3_DAT4_OUT
IODELAYCONFIG Module Register Manual
Table 20-1776 CFG_MMC3_DAT5_IN
Address Offset0x0000 06CC
Physical Address0x4844 A6CCInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mmc3_dat5_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1777 Register Call Summary for Register CFG_MMC3_DAT5_IN
IODELAYCONFIG Module Register Manual
Table 20-1778 CFG_MMC3_DAT5_OEN
Address Offset0x0000 06D0
Physical Address0x4844 A6D0InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mmc3_dat5_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1779 Register Call Summary for Register CFG_MMC3_DAT5_OEN
IODELAYCONFIG Module Register Manual
Table 20-1780 CFG_MMC3_DAT5_OUT
Address Offset0x0000 06D4
Physical Address0x4844 A6D4InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mmc3_dat5_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1781 Register Call Summary for Register CFG_MMC3_DAT5_OUT
IODELAYCONFIG Module Register Manual
Table 20-1782 CFG_MMC3_DAT6_IN
Address Offset0x0000 06D8
Physical Address0x4844 A6D8InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mmc3_dat6_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1783 Register Call Summary for Register CFG_MMC3_DAT6_IN
IODELAYCONFIG Module Register Manual
Table 20-1784 CFG_MMC3_DAT6_OEN
Address Offset0x0000 06DC
Physical Address0x4844 A6DCInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mmc3_dat6_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1785 Register Call Summary for Register CFG_MMC3_DAT6_OEN
IODELAYCONFIG Module Register Manual
Table 20-1786 CFG_MMC3_DAT6_OUT
Address Offset0x0000 06E0
Physical Address0x4844 A6E0InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mmc3_dat6_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1787 Register Call Summary for Register CFG_MMC3_DAT6_OUT
IODELAYCONFIG Module Register Manual
Table 20-1788 CFG_MMC3_DAT7_IN
Address Offset0x0000 06E4
Physical Address0x4844 A6E4InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mmc3_dat7_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1789 Register Call Summary for Register CFG_MMC3_DAT7_IN
IODELAYCONFIG Module Register Manual
Table 20-1790 CFG_MMC3_DAT7_OEN
Address Offset0x0000 06E8
Physical Address0x4844 A6E8InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mmc3_dat7_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1791 Register Call Summary for Register CFG_MMC3_DAT7_OEN
IODELAYCONFIG Module Register Manual
Table 20-1792 CFG_MMC3_DAT7_OUT
Address Offset0x0000 06EC
Physical Address0x4844 A6ECInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_mmc3_dat7_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1793 Register Call Summary for Register CFG_MMC3_DAT7_OUT
IODELAYCONFIG Module Register Manual
Table 20-1794 CFG_RGMII0_RXC_IN
Address Offset0x0000 06F0
Physical Address0x4844 A6F0InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_rgmii0_rxc_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1795 Register Call Summary for Register CFG_RGMII0_RXC_IN
IODELAYCONFIG Module Register Manual
Table 20-1796 CFG_RGMII0_RXC_OEN
Address Offset0x0000 06F4
Physical Address0x4844 A6F4InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_rgmii0_rxc_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1797 Register Call Summary for Register CFG_RGMII0_RXC_OEN
IODELAYCONFIG Module Register Manual
Table 20-1798 CFG_RGMII0_RXC_OUT
Address Offset0x0000 06F8
Physical Address0x4844 A6F8InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_rgmii0_rxc_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1799 Register Call Summary for Register CFG_RGMII0_RXC_OUT
IODELAYCONFIG Module Register Manual
Table 20-1800 CFG_RGMII0_RXCTL_IN
Address Offset0x0000 06FC
Physical Address0x4844 A6FCInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_rgmii0_rxctl_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1801 Register Call Summary for Register CFG_RGMII0_RXCTL_IN
IODELAYCONFIG Module Register Manual
Table 20-1802 CFG_RGMII0_RXCTL_OEN
Address Offset0x0000 0700
Physical Address0x4844 A700InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_rgmii0_rxctl_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1803 Register Call Summary for Register CFG_RGMII0_RXCTL_OEN
IODELAYCONFIG Module Register Manual
Table 20-1804 CFG_RGMII0_RXCTL_OUT
Address Offset0x0000 0704
Physical Address0x4844 A704InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_rgmii0_rxctl_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1805 Register Call Summary for Register CFG_RGMII0_RXCTL_OUT
IODELAYCONFIG Module Register Manual
Table 20-1806 CFG_RGMII0_RXD0_IN
Address Offset0x0000 0708
Physical Address0x4844 A708InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_rgmii0_rxd0_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1807 Register Call Summary for Register CFG_RGMII0_RXD0_IN
IODELAYCONFIG Module Register Manual
Table 20-1808 CFG_RGMII0_RXD0_OEN
Address Offset0x0000 070C
Physical Address0x4844 A70CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_rgmii0_rxd0_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1809 Register Call Summary for Register CFG_RGMII0_RXD0_OEN
IODELAYCONFIG Module Register Manual
Table 20-1810 CFG_RGMII0_RXD0_OUT
Address Offset0x0000 0710
Physical Address0x4844 A710InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_rgmii0_rxd0_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1811 Register Call Summary for Register CFG_RGMII0_RXD0_OUT
IODELAYCONFIG Module Register Manual
Table 20-1812 CFG_RGMII0_RXD1_IN
Address Offset0x0000 0714
Physical Address0x4844 A714InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_rgmii0_rxd1_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1813 Register Call Summary for Register CFG_RGMII0_RXD1_IN
IODELAYCONFIG Module Register Manual
Table 20-1814 CFG_RGMII0_RXD1_OEN
Address Offset0x0000 0718
Physical Address0x4844 A718InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_rgmii0_rxd1_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1815 Register Call Summary for Register CFG_RGMII0_RXD1_OEN
IODELAYCONFIG Module Register Manual
Table 20-1816 CFG_RGMII0_RXD1_OUT
Address Offset0x0000 071C
Physical Address0x4844 A71CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_rgmii0_rxd1_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1817 Register Call Summary for Register CFG_RGMII0_RXD1_OUT
IODELAYCONFIG Module Register Manual
Table 20-1818 CFG_RGMII0_RXD2_IN
Address Offset0x0000 0720
Physical Address0x4844 A720InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_rgmii0_rxd2_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1819 Register Call Summary for Register CFG_RGMII0_RXD2_IN
IODELAYCONFIG Module Register Manual
Table 20-1820 CFG_RGMII0_RXD2_OEN
Address Offset0x0000 0724
Physical Address0x4844 A724InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_rgmii0_rxd2_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1821 Register Call Summary for Register CFG_RGMII0_RXD2_OEN
IODELAYCONFIG Module Register Manual
Table 20-1822 CFG_RGMII0_RXD2_OUT
Address Offset0x0000 0728
Physical Address0x4844 A728InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_rgmii0_rxd2_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1823 Register Call Summary for Register CFG_RGMII0_RXD2_OUT
IODELAYCONFIG Module Register Manual
Table 20-1824 CFG_RGMII0_RXD3_IN
Address Offset0x0000 072C
Physical Address0x4844 A72CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_rgmii0_rxd3_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1825 Register Call Summary for Register CFG_RGMII0_RXD3_IN
IODELAYCONFIG Module Register Manual
Table 20-1826 CFG_RGMII0_RXD3_OEN
Address Offset0x0000 0730
Physical Address0x4844 A730InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_rgmii0_rxd3_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1827 Register Call Summary for Register CFG_RGMII0_RXD3_OEN
IODELAYCONFIG Module Register Manual
Table 20-1828 CFG_RGMII0_RXD3_OUT
Address Offset0x0000 0734
Physical Address0x4844 A734InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_rgmii0_rxd3_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1829 Register Call Summary for Register CFG_RGMII0_RXD3_OUT
IODELAYCONFIG Module Register Manual
Table 20-1830 CFG_RGMII0_TXC_IN
Address Offset0x0000 0738
Physical Address0x4844 A738InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_rgmii0_txc_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1831 Register Call Summary for Register CFG_RGMII0_TXC_IN
IODELAYCONFIG Module Register Manual
Table 20-1832 CFG_RGMII0_TXC_OEN
Address Offset0x0000 073C
Physical Address0x4844 A73CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_rgmii0_txc_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1833 Register Call Summary for Register CFG_RGMII0_TXC_OEN
IODELAYCONFIG Module Register Manual
Table 20-1834 CFG_RGMII0_TXC_OUT
Address Offset0x0000 0740
Physical Address0x4844 A740InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_rgmii0_txc_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1835 Register Call Summary for Register CFG_RGMII0_TXC_OUT
IODELAYCONFIG Module Register Manual
Table 20-1836 CFG_RGMII0_TXCTL_IN
Address Offset0x0000 0744
Physical Address0x4844 A744InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_rgmii0_txctl_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1837 Register Call Summary for Register CFG_RGMII0_TXCTL_IN
IODELAYCONFIG Module Register Manual
Table 20-1838 CFG_RGMII0_TXCTL_OEN
Address Offset0x0000 0748
Physical Address0x4844 A748InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_rgmii0_txctl_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1839 Register Call Summary for Register CFG_RGMII0_TXCTL_OEN
IODELAYCONFIG Module Register Manual
Table 20-1840 CFG_RGMII0_TXCTL_OUT
Address Offset0x0000 074C
Physical Address0x4844 A74CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_rgmii0_txctl_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1841 Register Call Summary for Register CFG_RGMII0_TXCTL_OUT
IODELAYCONFIG Module Register Manual
Table 20-1842 CFG_RGMII0_TXD0_IN
Address Offset0x0000 0750
Physical Address0x4844 A750InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_rgmii0_txd0_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1843 Register Call Summary for Register CFG_RGMII0_TXD0_IN
IODELAYCONFIG Module Register Manual
Table 20-1844 CFG_RGMII0_TXD0_OEN
Address Offset0x0000 0754
Physical Address0x4844 A754InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_rgmii0_txd0_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1845 Register Call Summary for Register CFG_RGMII0_TXD0_OEN
IODELAYCONFIG Module Register Manual
Table 20-1846 CFG_RGMII0_TXD0_OUT
Address Offset0x0000 0758
Physical Address0x4844 A758InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_rgmii0_txd0_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1847 Register Call Summary for Register CFG_RGMII0_TXD0_OUT
IODELAYCONFIG Module Register Manual
Table 20-1848 CFG_RGMII0_TXD1_IN
Address Offset0x0000 075C
Physical Address0x4844 A75CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_rgmii0_txd1_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1849 Register Call Summary for Register CFG_RGMII0_TXD1_IN
IODELAYCONFIG Module Register Manual
Table 20-1850 CFG_RGMII0_TXD1_OEN
Address Offset0x0000 0760
Physical Address0x4844 A760InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_rgmii0_txd1_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1851 Register Call Summary for Register CFG_RGMII0_TXD1_OEN
IODELAYCONFIG Module Register Manual
Table 20-1852 CFG_RGMII0_TXD1_OUT
Address Offset0x0000 0764
Physical Address0x4844 A764InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_rgmii0_txd1_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1853 Register Call Summary for Register CFG_RGMII0_TXD1_OUT
IODELAYCONFIG Module Register Manual
Table 20-1854 CFG_RGMII0_TXD2_IN
Address Offset0x0000 0768
Physical Address0x4844 A768InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_rgmii0_txd2_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1855 Register Call Summary for Register CFG_RGMII0_TXD2_IN
IODELAYCONFIG Module Register Manual
Table 20-1856 CFG_RGMII0_TXD2_OEN
Address Offset0x0000 076C
Physical Address0x4844 A76CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_rgmii0_txd2_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1857 Register Call Summary for Register CFG_RGMII0_TXD2_OEN
IODELAYCONFIG Module Register Manual
Table 20-1858 CFG_RGMII0_TXD2_OUT
Address Offset0x0000 0770
Physical Address0x4844 A770InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_rgmii0_txd2_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1859 Register Call Summary for Register CFG_RGMII0_TXD2_OUT
IODELAYCONFIG Module Register Manual
Table 20-1860 CFG_RGMII0_TXD3_IN
Address Offset0x0000 0774
Physical Address0x4844 A774InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_rgmii0_txd3_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1861 Register Call Summary for Register CFG_RGMII0_TXD3_IN
IODELAYCONFIG Module Register Manual
Table 20-1862 CFG_RGMII0_TXD3_OEN
Address Offset0x0000 0778
Physical Address0x4844 A778InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_rgmii0_txd3_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1863 Register Call Summary for Register CFG_RGMII0_TXD3_OEN
IODELAYCONFIG Module Register Manual
Table 20-1864 CFG_RGMII0_TXD3_OUT
Address Offset0x0000 077C
Physical Address0x4844 A77CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_rgmii0_txd3_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1865 Register Call Summary for Register CFG_RGMII0_TXD3_OUT
IODELAYCONFIG Module Register Manual
Table 20-1866 CFG_RTCK_IN
Address Offset0x0000 0780
Physical Address0x4844 A780InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_rtck_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1867 Register Call Summary for Register CFG_RTCK_IN
IODELAYCONFIG Module Register Manual
Table 20-1868 CFG_RTCK_OEN
Address Offset0x0000 0784
Physical Address0x4844 A784InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_rtck_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1869 Register Call Summary for Register CFG_RTCK_OEN
IODELAYCONFIG Module Register Manual
Table 20-1870 CFG_RTCK_OUT
Address Offset0x0000 0788
Physical Address0x4844 A788InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_rtck_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1871 Register Call Summary for Register CFG_RTCK_OUT
IODELAYCONFIG Module Register Manual
Table 20-1872 CFG_SPI1_CS0_IN
Address Offset0x0000 078C
Physical Address0x4844 A78CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_spi1_cs0_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1873 Register Call Summary for Register CFG_SPI1_CS0_IN
IODELAYCONFIG Module Register Manual
Table 20-1874 CFG_SPI1_CS0_OEN
Address Offset0x0000 0790
Physical Address0x4844 A790InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_spi1_cs0_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1875 Register Call Summary for Register CFG_SPI1_CS0_OEN
IODELAYCONFIG Module Register Manual
Table 20-1876 CFG_SPI1_CS0_OUT
Address Offset0x0000 0794
Physical Address0x4844 A794InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_spi1_cs0_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1877 Register Call Summary for Register CFG_SPI1_CS0_OUT
IODELAYCONFIG Module Register Manual
Table 20-1878 CFG_SPI1_CS1_IN
Address Offset0x0000 0798
Physical Address0x4844 A798InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_spi1_cs1_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1879 Register Call Summary for Register CFG_SPI1_CS1_IN
IODELAYCONFIG Module Register Manual
Table 20-1880 CFG_SPI1_CS1_OEN
Address Offset0x0000 079C
Physical Address0x4844 A79CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_spi1_cs1_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1881 Register Call Summary for Register CFG_SPI1_CS1_OEN
IODELAYCONFIG Module Register Manual
Table 20-1882 CFG_SPI1_CS1_OUT
Address Offset0x0000 07A0
Physical Address0x4844 A7A0InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_spi1_cs1_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1883 Register Call Summary for Register CFG_SPI1_CS1_OUT
IODELAYCONFIG Module Register Manual
Table 20-1884 CFG_SPI1_CS2_IN
Address Offset0x0000 07A4
Physical Address0x4844 A7A4InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_spi1_cs2_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1885 Register Call Summary for Register CFG_SPI1_CS2_IN
IODELAYCONFIG Module Register Manual
Table 20-1886 CFG_SPI1_CS2_OEN
Address Offset0x0000 07A8
Physical Address0x4844 A7A8InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_spi1_cs2_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1887 Register Call Summary for Register CFG_SPI1_CS2_OEN
IODELAYCONFIG Module Register Manual
Table 20-1888 CFG_SPI1_CS2_OUT
Address Offset0x0000 07AC
Physical Address0x4844 A7ACInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_spi1_cs2_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1889 Register Call Summary for Register CFG_SPI1_CS2_OUT
IODELAYCONFIG Module Register Manual
Table 20-1890 CFG_SPI1_CS3_IN
Address Offset0x0000 07B0
Physical Address0x4844 A7B0InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_spi1_cs3_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1891 Register Call Summary for Register CFG_SPI1_CS3_IN
IODELAYCONFIG Module Register Manual
Table 20-1892 CFG_SPI1_CS3_OEN
Address Offset0x0000 07B4
Physical Address0x4844 A7B4InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_spi1_cs3_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1893 Register Call Summary for Register CFG_SPI1_CS3_OEN
IODELAYCONFIG Module Register Manual
Table 20-1894 CFG_SPI1_CS3_OUT
Address Offset0x0000 07B8
Physical Address0x4844 A7B8InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_spi1_cs3_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1895 Register Call Summary for Register CFG_SPI1_CS3_OUT
IODELAYCONFIG Module Register Manual
Table 20-1896 CFG_SPI1_D0_IN
Address Offset0x0000 07BC
Physical Address0x4844 A7BCInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_spi1_d0_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1897 Register Call Summary for Register CFG_SPI1_D0_IN
IODELAYCONFIG Module Register Manual
Table 20-1898 CFG_SPI1_D0_OEN
Address Offset0x0000 07C0
Physical Address0x4844 A7C0InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_spi1_d0_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1899 Register Call Summary for Register CFG_SPI1_D0_OEN
IODELAYCONFIG Module Register Manual
Table 20-1900 CFG_SPI1_D0_OUT
Address Offset0x0000 07C4
Physical Address0x4844 A7C4InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_spi1_d0_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1901 Register Call Summary for Register CFG_SPI1_D0_OUT
IODELAYCONFIG Module Register Manual
Table 20-1902 CFG_SPI1_D1_IN
Address Offset0x0000 07C8
Physical Address0x4844 A7C8InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_spi1_d1_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1903 Register Call Summary for Register CFG_SPI1_D1_IN
IODELAYCONFIG Module Register Manual
Table 20-1904 CFG_SPI1_D1_OEN
Address Offset0x0000 07CC
Physical Address0x4844 A7CCInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_spi1_d1_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1905 Register Call Summary for Register CFG_SPI1_D1_OEN
IODELAYCONFIG Module Register Manual
Table 20-1906 CFG_SPI1_D1_OUT
Address Offset0x0000 07D0
Physical Address0x4844 A7D0InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_spi1_d1_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1907 Register Call Summary for Register CFG_SPI1_D1_OUT
IODELAYCONFIG Module Register Manual
Table 20-1908 CFG_SPI1_SCLK_IN
Address Offset0x0000 07D4
Physical Address0x4844 A7D4InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_spi1_sclk_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1909 Register Call Summary for Register CFG_SPI1_SCLK_IN
IODELAYCONFIG Module Register Manual
Table 20-1910 CFG_SPI1_SCLK_OEN
Address Offset0x0000 07D8
Physical Address0x4844 A7D8InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_spi1_sclk_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1911 Register Call Summary for Register CFG_SPI1_SCLK_OEN
IODELAYCONFIG Module Register Manual
Table 20-1912 CFG_SPI1_SCLK_OUT
Address Offset0x0000 07DC
Physical Address0x4844 A7DCInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_spi1_sclk_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1913 Register Call Summary for Register CFG_SPI1_SCLK_OUT
IODELAYCONFIG Module Register Manual
Table 20-1914 CFG_SPI2_CS0_IN
Address Offset0x0000 07E0
Physical Address0x4844 A7E0InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_spi2_cs0_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1915 Register Call Summary for Register CFG_SPI2_CS0_IN
IODELAYCONFIG Module Register Manual
Table 20-1916 CFG_SPI2_CS0_OEN
Address Offset0x0000 07E4
Physical Address0x4844 A7E4InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_spi2_cs0_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1917 Register Call Summary for Register CFG_SPI2_CS0_OEN
IODELAYCONFIG Module Register Manual
Table 20-1918 CFG_SPI2_CS0_OUT
Address Offset0x0000 07E8
Physical Address0x4844 A7E8InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_spi2_cs0_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1919 Register Call Summary for Register CFG_SPI2_CS0_OUT
IODELAYCONFIG Module Register Manual
Table 20-1920 CFG_SPI2_D0_IN
Address Offset0x0000 07EC
Physical Address0x4844 A7ECInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_spi2_d0_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1921 Register Call Summary for Register CFG_SPI2_D0_IN
IODELAYCONFIG Module Register Manual
Table 20-1922 CFG_SPI2_D0_OEN
Address Offset0x0000 07F0
Physical Address0x4844 A7F0InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_spi2_d0_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1923 Register Call Summary for Register CFG_SPI2_D0_OEN
IODELAYCONFIG Module Register Manual
Table 20-1924 CFG_SPI2_D0_OUT
Address Offset0x0000 07F4
Physical Address0x4844 A7F4InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_spi2_d0_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1925 Register Call Summary for Register CFG_SPI2_D0_OUT
IODELAYCONFIG Module Register Manual
Table 20-1926 CFG_SPI2_D1_IN
Address Offset0x0000 07F8
Physical Address0x4844 A7F8InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_spi2_d1_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1927 Register Call Summary for Register CFG_SPI2_D1_IN
IODELAYCONFIG Module Register Manual
Table 20-1928 CFG_SPI2_D1_OEN
Address Offset0x0000 07FC
Physical Address0x4844 A7FCInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_spi2_d1_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1929 Register Call Summary for Register CFG_SPI2_D1_OEN
IODELAYCONFIG Module Register Manual
Table 20-1930 CFG_SPI2_D1_OUT
Address Offset0x0000 0800
Physical Address0x4844 A800InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_spi2_d1_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1931 Register Call Summary for Register CFG_SPI2_D1_OUT
IODELAYCONFIG Module Register Manual
Table 20-1932 CFG_SPI2_SCLK_IN
Address Offset0x0000 0804
Physical Address0x4844 A804InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_spi2_sclk_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1933 Register Call Summary for Register CFG_SPI2_SCLK_IN
IODELAYCONFIG Module Register Manual
Table 20-1934 CFG_SPI2_SCLK_OEN
Address Offset0x0000 0808
Physical Address0x4844 A808InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_spi2_sclk_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1935 Register Call Summary for Register CFG_SPI2_SCLK_OEN
IODELAYCONFIG Module Register Manual
Table 20-1936 CFG_SPI2_SCLK_OUT
Address Offset0x0000 080C
Physical Address0x4844 A80CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_spi2_sclk_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1937 Register Call Summary for Register CFG_SPI2_SCLK_OUT
IODELAYCONFIG Module Register Manual
Table 20-1938 CFG_TDI_IN
Address Offset0x0000 0810
Physical Address0x4844 A810InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_tdi_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1939 Register Call Summary for Register CFG_TDI_IN
IODELAYCONFIG Module Register Manual
Table 20-1940 CFG_TDI_OEN
Address Offset0x0000 0814
Physical Address0x4844 A814InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_tdi_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1941 Register Call Summary for Register CFG_TDI_OEN
IODELAYCONFIG Module Register Manual
Table 20-1942 CFG_TDI_OUT
Address Offset0x0000 0818
Physical Address0x4844 A818InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_tdi_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1943 Register Call Summary for Register CFG_TDI_OUT
IODELAYCONFIG Module Register Manual
Table 20-1944 CFG_TDO_IN
Address Offset0x0000 081C
Physical Address0x4844 A81CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_tdo_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1945 Register Call Summary for Register CFG_TDO_IN
IODELAYCONFIG Module Register Manual
Table 20-1946 CFG_TDO_OEN
Address Offset0x0000 0820
Physical Address0x4844 A820InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_tdo_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1947 Register Call Summary for Register CFG_TDO_OEN
IODELAYCONFIG Module Register Manual
Table 20-1948 CFG_TDO_OUT
Address Offset0x0000 0824
Physical Address0x4844 A824InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_tdo_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1949 Register Call Summary for Register CFG_TDO_OUT
IODELAYCONFIG Module Register Manual
Table 20-1950 CFG_TMS_IN
Address Offset0x0000 0828
Physical Address0x4844 A828InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_tms_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1951 Register Call Summary for Register CFG_TMS_IN
IODELAYCONFIG Module Register Manual
Table 20-1952 CFG_TMS_OEN
Address Offset0x0000 082C
Physical Address0x4844 A82CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_tms_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1953 Register Call Summary for Register CFG_TMS_OEN
IODELAYCONFIG Module Register Manual
Table 20-1954 CFG_TMS_OUT
Address Offset0x0000 0830
Physical Address0x4844 A830InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_tms_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1955 Register Call Summary for Register CFG_TMS_OUT
IODELAYCONFIG Module Register Manual
Table 20-1956 CFG_TRSTN_IN
Address Offset0x0000 0834
Physical Address0x4844 A834InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_trstn_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1957 Register Call Summary for Register CFG_TRSTN_IN
IODELAYCONFIG Module Register Manual
Table 20-1958 CFG_TRSTN_OEN
Address Offset0x0000 0838
Physical Address0x4844 A838InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_trstn_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1959 Register Call Summary for Register CFG_TRSTN_OEN
IODELAYCONFIG Module Register Manual
Table 20-1960 CFG_TRSTN_OUT
Address Offset0x0000 083C
Physical Address0x4844 A83CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_trstn_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1961 Register Call Summary for Register CFG_TRSTN_OUT
IODELAYCONFIG Module Register Manual
Table 20-1962 CFG_UART1_CTSN_IN
Address Offset0x0000 0840
Physical Address0x4844 A840InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_uart1_ctsn_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1963 Register Call Summary for Register CFG_UART1_CTSN_IN
IODELAYCONFIG Module Register Manual
Table 20-1964 CFG_UART1_CTSN_OEN
Address Offset0x0000 0844
Physical Address0x4844 A844InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_uart1_ctsn_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1965 Register Call Summary for Register CFG_UART1_CTSN_OEN
IODELAYCONFIG Module Register Manual
Table 20-1966 CFG_UART1_CTSN_OUT
Address Offset0x0000 0848
Physical Address0x4844 A848InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_uart1_ctsn_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1967 Register Call Summary for Register CFG_UART1_CTSN_OUT
IODELAYCONFIG Module Register Manual
Table 20-1968 CFG_UART1_RTSN_IN
Address Offset0x0000 084C
Physical Address0x4844 A84CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_uart1_rtsn_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1969 Register Call Summary for Register CFG_UART1_RTSN_IN
IODELAYCONFIG Module Register Manual
Table 20-1970 CFG_UART1_RTSN_OEN
Address Offset0x0000 0850
Physical Address0x4844 A850InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_uart1_rtsn_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1971 Register Call Summary for Register CFG_UART1_RTSN_OEN
IODELAYCONFIG Module Register Manual
Table 20-1972 CFG_UART1_RTSN_OUT
Address Offset0x0000 0854
Physical Address0x4844 A854InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_uart1_rtsn_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1973 Register Call Summary for Register CFG_UART1_RTSN_OUT
IODELAYCONFIG Module Register Manual
Table 20-1974 CFG_UART1_RXD_IN
Address Offset0x0000 0858
Physical Address0x4844 A858InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_uart1_rxd_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1975 Register Call Summary for Register CFG_UART1_RXD_IN
IODELAYCONFIG Module Register Manual
Table 20-1976 CFG_UART1_RXD_OEN
Address Offset0x0000 085C
Physical Address0x4844 A85CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_uart1_rxd_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1977 Register Call Summary for Register CFG_UART1_RXD_OEN
IODELAYCONFIG Module Register Manual
Table 20-1978 CFG_UART1_RXD_OUT
Address Offset0x0000 0860
Physical Address0x4844 A860InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_uart1_rxd_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1979 Register Call Summary for Register CFG_UART1_RXD_OUT
IODELAYCONFIG Module Register Manual
Table 20-1980 CFG_UART1_TXD_IN
Address Offset0x0000 0864
Physical Address0x4844 A864InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_uart1_txd_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1981 Register Call Summary for Register CFG_UART1_TXD_IN
IODELAYCONFIG Module Register Manual
Table 20-1982 CFG_UART1_TXD_OEN
Address Offset0x0000 0868
Physical Address0x4844 A868InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_uart1_txd_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1983 Register Call Summary for Register CFG_UART1_TXD_OEN
IODELAYCONFIG Module Register Manual
Table 20-1984 CFG_UART1_TXD_OUT
Address Offset0x0000 086C
Physical Address0x4844 A86CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_uart1_txd_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1985 Register Call Summary for Register CFG_UART1_TXD_OUT
IODELAYCONFIG Module Register Manual
Table 20-1986 CFG_UART2_CTSN_IN
Address Offset0x0000 0870
Physical Address0x4844 A870InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_uart2_ctsn_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1987 Register Call Summary for Register CFG_UART2_CTSN_IN
IODELAYCONFIG Module Register Manual
Table 20-1988 CFG_UART2_CTSN_OEN
Address Offset0x0000 0874
Physical Address0x4844 A874InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_uart2_ctsn_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1989 Register Call Summary for Register CFG_UART2_CTSN_OEN
IODELAYCONFIG Module Register Manual
Table 20-1990 CFG_UART2_CTSN_OUT
Address Offset0x0000 0878
Physical Address0x4844 A878InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_uart2_ctsn_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1991 Register Call Summary for Register CFG_UART2_CTSN_OUT
IODELAYCONFIG Module Register Manual
Table 20-1992 CFG_UART2_RTSN_IN
Address Offset0x0000 087C
Physical Address0x4844 A87CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_uart2_rtsn_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1993 Register Call Summary for Register CFG_UART2_RTSN_IN
IODELAYCONFIG Module Register Manual
Table 20-1994 CFG_UART2_RTSN_OEN
Address Offset0x0000 0880
Physical Address0x4844 A880InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_uart2_rtsn_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1995 Register Call Summary for Register CFG_UART2_RTSN_OEN
IODELAYCONFIG Module Register Manual
Table 20-1996 CFG_UART2_RTSN_OUT
Address Offset0x0000 0884
Physical Address0x4844 A884InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_uart2_rtsn_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1997 Register Call Summary for Register CFG_UART2_RTSN_OUT
IODELAYCONFIG Module Register Manual
Table 20-1998 CFG_UART2_RXD_IN
Address Offset0x0000 0888
Physical Address0x4844 A888InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_uart2_rxd_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-1999 Register Call Summary for Register CFG_UART2_RXD_IN
IODELAYCONFIG Module Register Manual
Table 20-2000 CFG_UART2_RXD_OEN
Address Offset0x0000 088C
Physical Address0x4844 A88CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_uart2_rxd_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2001 Register Call Summary for Register CFG_UART2_RXD_OEN
IODELAYCONFIG Module Register Manual
Table 20-2002 CFG_UART2_RXD_OUT
Address Offset0x0000 0890
Physical Address0x4844 A890InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_uart2_rxd_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2003 Register Call Summary for Register CFG_UART2_RXD_OUT
IODELAYCONFIG Module Register Manual
Table 20-2004 CFG_UART2_TXD_IN
Address Offset0x0000 0894
Physical Address0x4844 A894InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_uart2_txd_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2005 Register Call Summary for Register CFG_UART2_TXD_IN
IODELAYCONFIG Module Register Manual
Table 20-2006 CFG_UART2_TXD_OEN
Address Offset0x0000 0898
Physical Address0x4844 A898InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_uart2_txd_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2007 Register Call Summary for Register CFG_UART2_TXD_OEN
IODELAYCONFIG Module Register Manual
Table 20-2008 CFG_UART2_TXD_OUT
Address Offset0x0000 089C
Physical Address0x4844 A89CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_uart2_txd_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2009 Register Call Summary for Register CFG_UART2_TXD_OUT
IODELAYCONFIG Module Register Manual
Table 20-2010 CFG_UART3_RXD_IN
Address Offset0x0000 08A0
Physical Address0x4844 A8A0InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_uart3_rxd_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2011 Register Call Summary for Register CFG_UART3_RXD_IN
IODELAYCONFIG Module Register Manual
Table 20-2012 CFG_UART3_RXD_OEN
Address Offset0x0000 08A4
Physical Address0x4844 A8A4InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_uart3_rxd_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2013 Register Call Summary for Register CFG_UART3_RXD_OEN
IODELAYCONFIG Module Register Manual
Table 20-2014 CFG_UART3_RXD_OUT
Address Offset0x0000 08A8
Physical Address0x4844 A8A8InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_uart3_rxd_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2015 Register Call Summary for Register CFG_UART3_RXD_OUT
IODELAYCONFIG Module Register Manual
Table 20-2016 CFG_UART3_TXD_IN
Address Offset0x0000 08AC
Physical Address0x4844 A8ACInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_uart3_txd_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2017 Register Call Summary for Register CFG_UART3_TXD_IN
IODELAYCONFIG Module Register Manual
Table 20-2018 CFG_UART3_TXD_OEN
Address Offset0x0000 08B0
Physical Address0x4844 A8B0InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_uart3_txd_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2019 Register Call Summary for Register CFG_UART3_TXD_OEN
IODELAYCONFIG Module Register Manual
Table 20-2020 CFG_UART3_TXD_OUT
Address Offset0x0000 08B4
Physical Address0x4844 A8B4InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_uart3_txd_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2021 Register Call Summary for Register CFG_UART3_TXD_OUT
IODELAYCONFIG Module Register Manual
Table 20-2022 CFG_USB1_DRVVBUS_IN
Address Offset0x0000 08B8
Physical Address0x4844 A8B8InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_usb1_drvvbus_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2023 Register Call Summary for Register CFG_USB1_DRVVBUS_IN
IODELAYCONFIG Module Register Manual
Table 20-2024 CFG_USB1_DRVVBUS_OEN
Address Offset0x0000 08BC
Physical Address0x4844 A8BCInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_usb1_drvvbus_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2025 Register Call Summary for Register CFG_USB1_DRVVBUS_OEN
IODELAYCONFIG Module Register Manual
Table 20-2026 CFG_USB1_DRVVBUS_OUT
Address Offset0x0000 08C0
Physical Address0x4844 A8C0InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_usb1_drvvbus_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2027 Register Call Summary for Register CFG_USB1_DRVVBUS_OUT
IODELAYCONFIG Module Register Manual
Table 20-2028 CFG_USB2_DRVVBUS_IN
Address Offset0x0000 08C4
Physical Address0x4844 A8C4InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_usb2_drvvbus_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2029 Register Call Summary for Register CFG_USB2_DRVVBUS_IN
IODELAYCONFIG Module Register Manual
Table 20-2030 CFG_USB2_DRVVBUS_OEN
Address Offset0x0000 08C8
Physical Address0x4844 A8C8InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_usb2_drvvbus_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2031 Register Call Summary for Register CFG_USB2_DRVVBUS_OEN
IODELAYCONFIG Module Register Manual
Table 20-2032 CFG_USB2_DRVVBUS_OUT
Address Offset0x0000 08CC
Physical Address0x4844 A8CCInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_usb2_drvvbus_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2033 Register Call Summary for Register CFG_USB2_DRVVBUS_OUT
IODELAYCONFIG Module Register Manual
Table 20-2034 CFG_VIN1A_CLK0_IN
Address Offset0x0000 08D0
Physical Address0x4844 A8D0InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_clk0_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2035 Register Call Summary for Register CFG_VIN1A_CLK0_IN
IODELAYCONFIG Module Register Manual
Table 20-2036 CFG_VIN1A_CLK0_OEN
Address Offset0x0000 08D4
Physical Address0x4844 A8D4InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_clk0_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2037 Register Call Summary for Register CFG_VIN1A_CLK0_OEN
IODELAYCONFIG Module Register Manual
Table 20-2038 CFG_VIN1A_CLK0_OUT
Address Offset0x0000 08D8
Physical Address0x4844 A8D8InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_clk0_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2039 Register Call Summary for Register CFG_VIN1A_CLK0_OUT
IODELAYCONFIG Module Register Manual
Table 20-2040 CFG_VIN1A_D0_IN
Address Offset0x0000 08DC
Physical Address0x4844 A8DCInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_d0_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2041 Register Call Summary for Register CFG_VIN1A_D0_IN
IODELAYCONFIG Module Register Manual
Table 20-2042 CFG_VIN1A_D0_OEN
Address Offset0x0000 08E0
Physical Address0x4844 A8E0InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_d0_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2043 Register Call Summary for Register CFG_VIN1A_D0_OEN
IODELAYCONFIG Module Register Manual
Table 20-2044 CFG_VIN1A_D0_OUT
Address Offset0x0000 08E4
Physical Address0x4844 A8E4InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_d0_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2045 Register Call Summary for Register CFG_VIN1A_D0_OUT
IODELAYCONFIG Module Register Manual
Table 20-2046 CFG_VIN1A_D10_IN
Address Offset0x0000 08E8
Physical Address0x4844 A8E8InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_d10_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2047 Register Call Summary for Register CFG_VIN1A_D10_IN
IODELAYCONFIG Module Register Manual
Table 20-2048 CFG_VIN1A_D10_OEN
Address Offset0x0000 08EC
Physical Address0x4844 A8ECInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_d10_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2049 Register Call Summary for Register CFG_VIN1A_D10_OEN
IODELAYCONFIG Module Register Manual
Table 20-2050 CFG_VIN1A_D10_OUT
Address Offset0x0000 08F0
Physical Address0x4844 A8F0InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_d10_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2051 Register Call Summary for Register CFG_VIN1A_D10_OUT
IODELAYCONFIG Module Register Manual
Table 20-2052 CFG_VIN1A_D11_IN
Address Offset0x0000 08F4
Physical Address0x4844 A8F4InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_d11_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2053 Register Call Summary for Register CFG_VIN1A_D11_IN
IODELAYCONFIG Module Register Manual
Table 20-2054 CFG_VIN1A_D11_OEN
Address Offset0x0000 08F8
Physical Address0x4844 A8F8InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_d11_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2055 Register Call Summary for Register CFG_VIN1A_D11_OEN
IODELAYCONFIG Module Register Manual
Table 20-2056 CFG_VIN1A_D11_OUT
Address Offset0x0000 08FC
Physical Address0x4844 A8FCInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_d11_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2057 Register Call Summary for Register CFG_VIN1A_D11_OUT
IODELAYCONFIG Module Register Manual
Table 20-2058 CFG_VIN1A_D12_IN
Address Offset0x0000 0900
Physical Address0x4844 A900InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_d12_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2059 Register Call Summary for Register CFG_VIN1A_D12_IN
IODELAYCONFIG Module Register Manual
Table 20-2060 CFG_VIN1A_D12_OEN
Address Offset0x0000 0904
Physical Address0x4844 A904InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_d12_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2061 Register Call Summary for Register CFG_VIN1A_D12_OEN
IODELAYCONFIG Module Register Manual
Table 20-2062 CFG_VIN1A_D12_OUT
Address Offset0x0000 0908
Physical Address0x4844 A908InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_d12_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2063 Register Call Summary for Register CFG_VIN1A_D12_OUT
IODELAYCONFIG Module Register Manual
Table 20-2064 CFG_VIN1A_D13_IN
Address Offset0x0000 090C
Physical Address0x4844 A90CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_d13_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2065 Register Call Summary for Register CFG_VIN1A_D13_IN
IODELAYCONFIG Module Register Manual
Table 20-2066 CFG_VIN1A_D13_OEN
Address Offset0x0000 0910
Physical Address0x4844 A910InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_d13_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2067 Register Call Summary for Register CFG_VIN1A_D13_OEN
IODELAYCONFIG Module Register Manual
Table 20-2068 CFG_VIN1A_D13_OUT
Address Offset0x0000 0914
Physical Address0x4844 A914InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_d13_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2069 Register Call Summary for Register CFG_VIN1A_D13_OUT
IODELAYCONFIG Module Register Manual
Table 20-2070 CFG_VIN1A_D14_IN
Address Offset0x0000 0918
Physical Address0x4844 A918InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_d14_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2071 Register Call Summary for Register CFG_VIN1A_D14_IN
IODELAYCONFIG Module Register Manual
Table 20-2072 CFG_VIN1A_D14_OEN
Address Offset0x0000 091C
Physical Address0x4844 A91CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_d14_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2073 Register Call Summary for Register CFG_VIN1A_D14_OEN
IODELAYCONFIG Module Register Manual
Table 20-2074 CFG_VIN1A_D14_OUT
Address Offset0x0000 0920
Physical Address0x4844 A920InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_d14_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2075 Register Call Summary for Register CFG_VIN1A_D14_OUT
IODELAYCONFIG Module Register Manual
Table 20-2076 CFG_VIN1A_D15_IN
Address Offset0x0000 0924
Physical Address0x4844 A924InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_d15_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2077 Register Call Summary for Register CFG_VIN1A_D15_IN
IODELAYCONFIG Module Register Manual
Table 20-2078 CFG_VIN1A_D15_OEN
Address Offset0x0000 0928
Physical Address0x4844 A928InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_d15_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2079 Register Call Summary for Register CFG_VIN1A_D15_OEN
IODELAYCONFIG Module Register Manual
Table 20-2080 CFG_VIN1A_D15_OUT
Address Offset0x0000 092C
Physical Address0x4844 A92CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_d15_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2081 Register Call Summary for Register CFG_VIN1A_D15_OUT
IODELAYCONFIG Module Register Manual
Table 20-2082 CFG_VIN1A_D16_IN
Address Offset0x0000 0930
Physical Address0x4844 A930InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_d16_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2083 Register Call Summary for Register CFG_VIN1A_D16_IN
IODELAYCONFIG Module Register Manual
Table 20-2084 CFG_VIN1A_D16_OEN
Address Offset0x0000 0934
Physical Address0x4844 A934InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_d16_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2085 Register Call Summary for Register CFG_VIN1A_D16_OEN
IODELAYCONFIG Module Register Manual
Table 20-2086 CFG_VIN1A_D16_OUT
Address Offset0x0000 0938
Physical Address0x4844 A938InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_d16_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2087 Register Call Summary for Register CFG_VIN1A_D16_OUT
IODELAYCONFIG Module Register Manual
Table 20-2088 CFG_VIN1A_D17_IN
Address Offset0x0000 093C
Physical Address0x4844 A93CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_d17_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2089 Register Call Summary for Register CFG_VIN1A_D17_IN
IODELAYCONFIG Module Register Manual
Table 20-2090 CFG_VIN1A_D17_OEN
Address Offset0x0000 0940
Physical Address0x4844 A940InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_d17_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2091 Register Call Summary for Register CFG_VIN1A_D17_OEN
IODELAYCONFIG Module Register Manual
Table 20-2092 CFG_VIN1A_D17_OUT
Address Offset0x0000 0944
Physical Address0x4844 A944InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_d17_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2093 Register Call Summary for Register CFG_VIN1A_D17_OUT
IODELAYCONFIG Module Register Manual
Table 20-2094 CFG_VIN1A_D18_IN
Address Offset0x0000 0948
Physical Address0x4844 A948InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_d18_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2095 Register Call Summary for Register CFG_VIN1A_D18_IN
IODELAYCONFIG Module Register Manual
Table 20-2096 CFG_VIN1A_D18_OEN
Address Offset0x0000 094C
Physical Address0x4844 A94CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_d18_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2097 Register Call Summary for Register CFG_VIN1A_D18_OEN
IODELAYCONFIG Module Register Manual
Table 20-2098 CFG_VIN1A_D18_OUT
Address Offset0x0000 0950
Physical Address0x4844 A950InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_d18_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2099 Register Call Summary for Register CFG_VIN1A_D18_OUT
IODELAYCONFIG Module Register Manual
Table 20-2100 CFG_VIN1A_D19_IN
Address Offset0x0000 0954
Physical Address0x4844 A954InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_d19_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2101 Register Call Summary for Register CFG_VIN1A_D19_IN
IODELAYCONFIG Module Register Manual
Table 20-2102 CFG_VIN1A_D19_OEN
Address Offset0x0000 0958
Physical Address0x4844 A958InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_d19_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2103 Register Call Summary for Register CFG_VIN1A_D19_OEN
IODELAYCONFIG Module Register Manual
Table 20-2104 CFG_VIN1A_D19_OUT
Address Offset0x0000 095C
Physical Address0x4844 A95CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_d19_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2105 Register Call Summary for Register CFG_VIN1A_D19_OUT
IODELAYCONFIG Module Register Manual
Table 20-2106 CFG_VIN1A_D1_IN
Address Offset0x0000 0960
Physical Address0x4844 A960InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_d1_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2107 Register Call Summary for Register CFG_VIN1A_D1_IN
IODELAYCONFIG Module Register Manual
Table 20-2108 CFG_VIN1A_D1_OEN
Address Offset0x0000 0964
Physical Address0x4844 A964InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_d1_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2109 Register Call Summary for Register CFG_VIN1A_D1_OEN
IODELAYCONFIG Module Register Manual
Table 20-2110 CFG_VIN1A_D1_OUT
Address Offset0x0000 0968
Physical Address0x4844 A968InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_d1_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2111 Register Call Summary for Register CFG_VIN1A_D1_OUT
IODELAYCONFIG Module Register Manual
Table 20-2112 CFG_VIN1A_D20_IN
Address Offset0x0000 096C
Physical Address0x4844 A96CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_d20_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2113 Register Call Summary for Register CFG_VIN1A_D20_IN
IODELAYCONFIG Module Register Manual
Table 20-2114 CFG_VIN1A_D20_OEN
Address Offset0x0000 0970
Physical Address0x4844 A970InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_d20_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2115 Register Call Summary for Register CFG_VIN1A_D20_OEN
IODELAYCONFIG Module Register Manual
Table 20-2116 CFG_VIN1A_D20_OUT
Address Offset0x0000 0974
Physical Address0x4844 A974InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_d20_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2117 Register Call Summary for Register CFG_VIN1A_D20_OUT
IODELAYCONFIG Module Register Manual
Table 20-2118 CFG_VIN1A_D21_IN
Address Offset0x0000 0978
Physical Address0x4844 A978InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_d21_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2119 Register Call Summary for Register CFG_VIN1A_D21_IN
IODELAYCONFIG Module Register Manual
Table 20-2120 CFG_VIN1A_D21_OEN
Address Offset0x0000 097C
Physical Address0x4844 A97CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_d21_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2121 Register Call Summary for Register CFG_VIN1A_D21_OEN
IODELAYCONFIG Module Register Manual
Table 20-2122 CFG_VIN1A_D21_OUT
Address Offset0x0000 0980
Physical Address0x4844 A980InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_d21_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2123 Register Call Summary for Register CFG_VIN1A_D21_OUT
IODELAYCONFIG Module Register Manual
Table 20-2124 CFG_VIN1A_D22_IN
Address Offset0x0000 0984
Physical Address0x4844 A984InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_d22_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2125 Register Call Summary for Register CFG_VIN1A_D22_IN
IODELAYCONFIG Module Register Manual
Table 20-2126 CFG_VIN1A_D22_OEN
Address Offset0x0000 0988
Physical Address0x4844 A988InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_d22_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2127 Register Call Summary for Register CFG_VIN1A_D22_OEN
IODELAYCONFIG Module Register Manual
Table 20-2128 CFG_VIN1A_D22_OUT
Address Offset0x0000 098C
Physical Address0x4844 A98CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_d22_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2129 Register Call Summary for Register CFG_VIN1A_D22_OUT
IODELAYCONFIG Module Register Manual
Table 20-2130 CFG_VIN1A_D23_IN
Address Offset0x0000 0990
Physical Address0x4844 A990InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_d23_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2131 Register Call Summary for Register CFG_VIN1A_D23_IN
IODELAYCONFIG Module Register Manual
Table 20-2132 CFG_VIN1A_D23_OEN
Address Offset0x0000 0994
Physical Address0x4844 A994InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_d23_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2133 Register Call Summary for Register CFG_VIN1A_D23_OEN
IODELAYCONFIG Module Register Manual
Table 20-2134 CFG_VIN1A_D23_OUT
Address Offset0x0000 0998
Physical Address0x4844 A998InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_d23_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2135 Register Call Summary for Register CFG_VIN1A_D23_OUT
IODELAYCONFIG Module Register Manual
Table 20-2136 CFG_VIN1A_D2_IN
Address Offset0x0000 099C
Physical Address0x4844 A99CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_d2_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2137 Register Call Summary for Register CFG_VIN1A_D2_IN
IODELAYCONFIG Module Register Manual
Table 20-2138 CFG_VIN1A_D2_OEN
Address Offset0x0000 09A0
Physical Address0x4844 A9A0InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_d2_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2139 Register Call Summary for Register CFG_VIN1A_D2_OEN
IODELAYCONFIG Module Register Manual
Table 20-2140 CFG_VIN1A_D2_OUT
Address Offset0x0000 09A4
Physical Address0x4844 A9A4InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_d2_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2141 Register Call Summary for Register CFG_VIN1A_D2_OUT
IODELAYCONFIG Module Register Manual
Table 20-2142 CFG_VIN1A_D3_IN
Address Offset0x0000 09A8
Physical Address0x4844 A9A8InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_d3_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2143 Register Call Summary for Register CFG_VIN1A_D3_IN
IODELAYCONFIG Module Register Manual
Table 20-2144 CFG_VIN1A_D3_OEN
Address Offset0x0000 09AC
Physical Address0x4844 A9ACInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_d3_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2145 Register Call Summary for Register CFG_VIN1A_D3_OEN
IODELAYCONFIG Module Register Manual
Table 20-2146 CFG_VIN1A_D3_OUT
Address Offset0x0000 09B0
Physical Address0x4844 A9B0InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_d3_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2147 Register Call Summary for Register CFG_VIN1A_D3_OUT
IODELAYCONFIG Module Register Manual
Table 20-2148 CFG_VIN1A_D4_IN
Address Offset0x0000 09B4
Physical Address0x4844 A9B4InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_d4_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2149 Register Call Summary for Register CFG_VIN1A_D4_IN
IODELAYCONFIG Module Register Manual
Table 20-2150 CFG_VIN1A_D4_OEN
Address Offset0x0000 09B8
Physical Address0x4844 A9B8InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_d4_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2151 Register Call Summary for Register CFG_VIN1A_D4_OEN
IODELAYCONFIG Module Register Manual
Table 20-2152 CFG_VIN1A_D4_OUT
Address Offset0x0000 09BC
Physical Address0x4844 A9BCInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_d4_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2153 Register Call Summary for Register CFG_VIN1A_D4_OUT
IODELAYCONFIG Module Register Manual
Table 20-2154 CFG_VIN1A_D5_IN
Address Offset0x0000 09C0
Physical Address0x4844 A9C0InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_d5_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2155 Register Call Summary for Register CFG_VIN1A_D5_IN
IODELAYCONFIG Module Register Manual
Table 20-2156 CFG_VIN1A_D5_OEN
Address Offset0x0000 09C4
Physical Address0x4844 A9C4InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_d5_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2157 Register Call Summary for Register CFG_VIN1A_D5_OEN
IODELAYCONFIG Module Register Manual
Table 20-2158 CFG_VIN1A_D5_OUT
Address Offset0x0000 09C8
Physical Address0x4844 A9C8InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_d5_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2159 Register Call Summary for Register CFG_VIN1A_D5_OUT
IODELAYCONFIG Module Register Manual
Table 20-2160 CFG_VIN1A_D6_IN
Address Offset0x0000 09CC
Physical Address0x4844 A9CCInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_d6_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2161 Register Call Summary for Register CFG_VIN1A_D6_IN
IODELAYCONFIG Module Register Manual
Table 20-2162 CFG_VIN1A_D6_OEN
Address Offset0x0000 09D0
Physical Address0x4844 A9D0InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_d6_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2163 Register Call Summary for Register CFG_VIN1A_D6_OEN
IODELAYCONFIG Module Register Manual
Table 20-2164 CFG_VIN1A_D6_OUT
Address Offset0x0000 09D4
Physical Address0x4844 A9D4InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_d6_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2165 Register Call Summary for Register CFG_VIN1A_D6_OUT
IODELAYCONFIG Module Register Manual
Table 20-2166 CFG_VIN1A_D7_IN
Address Offset0x0000 09D8
Physical Address0x4844 A9D8InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_d7_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2167 Register Call Summary for Register CFG_VIN1A_D7_IN
IODELAYCONFIG Module Register Manual
Table 20-2168 CFG_VIN1A_D7_OEN
Address Offset0x0000 09DC
Physical Address0x4844 A9DCInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_d7_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2169 Register Call Summary for Register CFG_VIN1A_D7_OEN
IODELAYCONFIG Module Register Manual
Table 20-2170 CFG_VIN1A_D7_OUT
Address Offset0x0000 09E0
Physical Address0x4844 A9E0InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_d7_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2171 Register Call Summary for Register CFG_VIN1A_D7_OUT
IODELAYCONFIG Module Register Manual
Table 20-2172 CFG_VIN1A_D8_IN
Address Offset0x0000 09E4
Physical Address0x4844 A9E4InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_d8_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2173 Register Call Summary for Register CFG_VIN1A_D8_IN
IODELAYCONFIG Module Register Manual
Table 20-2174 CFG_VIN1A_D8_OEN
Address Offset0x0000 09E8
Physical Address0x4844 A9E8InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_d8_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2175 Register Call Summary for Register CFG_VIN1A_D8_OEN
IODELAYCONFIG Module Register Manual
Table 20-2176 CFG_VIN1A_D8_OUT
Address Offset0x0000 09EC
Physical Address0x4844 A9ECInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_d8_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2177 Register Call Summary for Register CFG_VIN1A_D8_OUT
IODELAYCONFIG Module Register Manual
Table 20-2178 CFG_VIN1A_D9_IN
Address Offset0x0000 09F0
Physical Address0x4844 A9F0InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_d9_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2179 Register Call Summary for Register CFG_VIN1A_D9_IN
IODELAYCONFIG Module Register Manual
Table 20-2180 CFG_VIN1A_D9_OEN
Address Offset0x0000 09F4
Physical Address0x4844 A9F4InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_d9_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2181 Register Call Summary for Register CFG_VIN1A_D9_OEN
IODELAYCONFIG Module Register Manual
Table 20-2182 CFG_VIN1A_D9_OUT
Address Offset0x0000 09F8
Physical Address0x4844 A9F8InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_d9_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2183 Register Call Summary for Register CFG_VIN1A_D9_OUT
IODELAYCONFIG Module Register Manual
Table 20-2184 CFG_VIN1A_DE0_IN
Address Offset0x0000 09FC
Physical Address0x4844 A9FCInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_de0_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2185 Register Call Summary for Register CFG_VIN1A_DE0_IN
IODELAYCONFIG Module Register Manual
Table 20-2186 CFG_VIN1A_DE0_OEN
Address Offset0x0000 0A00
Physical Address0x4844 AA00InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_de0_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2187 Register Call Summary for Register CFG_VIN1A_DE0_OEN
IODELAYCONFIG Module Register Manual
Table 20-2188 CFG_VIN1A_DE0_OUT
Address Offset0x0000 0A04
Physical Address0x4844 AA04InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_de0_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2189 Register Call Summary for Register CFG_VIN1A_DE0_OUT
IODELAYCONFIG Module Register Manual
Table 20-2190 CFG_VIN1A_FLD0_IN
Address Offset0x0000 0A08
Physical Address0x4844 AA08InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_fld0_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2191 Register Call Summary for Register CFG_VIN1A_FLD0_IN
IODELAYCONFIG Module Register Manual
Table 20-2192 CFG_VIN1A_FLD0_OEN
Address Offset0x0000 0A0C
Physical Address0x4844 AA0CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_fld0_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2193 Register Call Summary for Register CFG_VIN1A_FLD0_OEN
IODELAYCONFIG Module Register Manual
Table 20-2194 CFG_VIN1A_FLD0_OUT
Address Offset0x0000 0A10
Physical Address0x4844 AA10InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_fld0_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2195 Register Call Summary for Register CFG_VIN1A_FLD0_OUT
IODELAYCONFIG Module Register Manual
Table 20-2196 CFG_VIN1A_HSYNC0_IN
Address Offset0x0000 0A14
Physical Address0x4844 AA14InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_hsync0_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2197 Register Call Summary for Register CFG_VIN1A_HSYNC0_IN
IODELAYCONFIG Module Register Manual
Table 20-2198 CFG_VIN1A_HSYNC0_OEN
Address Offset0x0000 0A18
Physical Address0x4844 AA18InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_hsync0_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2199 Register Call Summary for Register CFG_VIN1A_HSYNC0_OEN
IODELAYCONFIG Module Register Manual
Table 20-2200 CFG_VIN1A_HSYNC0_OUT
Address Offset0x0000 0A1C
Physical Address0x4844 AA1CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_hsync0_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2201 Register Call Summary for Register CFG_VIN1A_HSYNC0_OUT
IODELAYCONFIG Module Register Manual
Table 20-2202 CFG_VIN1A_VSYNC0_IN
Address Offset0x0000 0A20
Physical Address0x4844 AA20InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_vsync0_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2203 Register Call Summary for Register CFG_VIN1A_VSYNC0_IN
IODELAYCONFIG Module Register Manual
Table 20-2204 CFG_VIN1A_VSYNC0_OEN
Address Offset0x0000 0A24
Physical Address0x4844 AA24InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_vsync0_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2205 Register Call Summary for Register CFG_VIN1A_VSYNC0_OEN
IODELAYCONFIG Module Register Manual
Table 20-2206 CFG_VIN1A_VSYNC0_OUT
Address Offset0x0000 0A28
Physical Address0x4844 AA28InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1a_vsync0_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2207 Register Call Summary for Register CFG_VIN1A_VSYNC0_OUT
IODELAYCONFIG Module Register Manual
Table 20-2208 CFG_VIN1B_CLK1_IN
Address Offset0x0000 0A2C
Physical Address0x4844 AA2CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1b_clk1_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2209 Register Call Summary for Register CFG_VIN1B_CLK1_IN
IODELAYCONFIG Module Register Manual
Table 20-2210 CFG_VIN1B_CLK1_OEN
Address Offset0x0000 0A30
Physical Address0x4844 AA30InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1b_clk1_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2211 Register Call Summary for Register CFG_VIN1B_CLK1_OEN
IODELAYCONFIG Module Register Manual
Table 20-2212 CFG_VIN1B_CLK1_OUT
Address Offset0x0000 0A34
Physical Address0x4844 AA34InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin1b_clk1_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2213 Register Call Summary for Register CFG_VIN1B_CLK1_OUT
IODELAYCONFIG Module Register Manual
Table 20-2214 CFG_VIN2A_CLK0_IN
Address Offset0x0000 0A38
Physical Address0x4844 AA38InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_clk0_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2215 Register Call Summary for Register CFG_VIN2A_CLK0_IN
IODELAYCONFIG Module Register Manual
Table 20-2216 CFG_VIN2A_CLK0_OEN
Address Offset0x0000 0A3C
Physical Address0x4844 AA3CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_clk0_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2217 Register Call Summary for Register CFG_VIN2A_CLK0_OEN
IODELAYCONFIG Module Register Manual
Table 20-2218 CFG_VIN2A_CLK0_OUT
Address Offset0x0000 0A40
Physical Address0x4844 AA40InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_clk0_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2219 Register Call Summary for Register CFG_VIN2A_CLK0_OUT
IODELAYCONFIG Module Register Manual
Table 20-2220 CFG_VIN2A_D0_IN
Address Offset0x0000 0A44
Physical Address0x4844 AA44InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_d0_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2221 Register Call Summary for Register CFG_VIN2A_D0_IN
IODELAYCONFIG Module Register Manual
Table 20-2222 CFG_VIN2A_D0_OEN
Address Offset0x0000 0A48
Physical Address0x4844 AA48InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_d0_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2223 Register Call Summary for Register CFG_VIN2A_D0_OEN
IODELAYCONFIG Module Register Manual
Table 20-2224 CFG_VIN2A_D0_OUT
Address Offset0x0000 0A4C
Physical Address0x4844 AA4CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_d0_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2225 Register Call Summary for Register CFG_VIN2A_D0_OUT
IODELAYCONFIG Module Register Manual
Table 20-2226 CFG_VIN2A_D10_IN
Address Offset0x0000 0A50
Physical Address0x4844 AA50InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_d10_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2227 Register Call Summary for Register CFG_VIN2A_D10_IN
IODELAYCONFIG Module Register Manual
Table 20-2228 CFG_VIN2A_D10_OEN
Address Offset0x0000 0A54
Physical Address0x4844 AA54InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_d10_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2229 Register Call Summary for Register CFG_VIN2A_D10_OEN
IODELAYCONFIG Module Register Manual
Table 20-2230 CFG_VIN2A_D10_OUT
Address Offset0x0000 0A58
Physical Address0x4844 AA58InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_d10_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2231 Register Call Summary for Register CFG_VIN2A_D10_OUT
IODELAYCONFIG Module Register Manual
Table 20-2232 CFG_VIN2A_D11_IN
Address Offset0x0000 0A5C
Physical Address0x4844 AA5CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_d11_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2233 Register Call Summary for Register CFG_VIN2A_D11_IN
IODELAYCONFIG Module Register Manual
Table 20-2234 CFG_VIN2A_D11_OEN
Address Offset0x0000 0A60
Physical Address0x4844 AA60InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_d11_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2235 Register Call Summary for Register CFG_VIN2A_D11_OEN
IODELAYCONFIG Module Register Manual
Table 20-2236 CFG_VIN2A_D11_OUT
Address Offset0x0000 0A64
Physical Address0x4844 AA64InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_d11_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2237 Register Call Summary for Register CFG_VIN2A_D11_OUT
IODELAYCONFIG Module Register Manual
Table 20-2238 CFG_VIN2A_D12_IN
Address Offset0x0000 0A68
Physical Address0x4844 AA68InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_d12_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2239 Register Call Summary for Register CFG_VIN2A_D12_IN
IODELAYCONFIG Module Register Manual
Table 20-2240 CFG_VIN2A_D12_OEN
Address Offset0x0000 0A6C
Physical Address0x4844 AA6CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_d12_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2241 Register Call Summary for Register CFG_VIN2A_D12_OEN
IODELAYCONFIG Module Register Manual
Table 20-2242 CFG_VIN2A_D12_OUT
Address Offset0x0000 0A70
Physical Address0x4844 AA70InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_d12_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2243 Register Call Summary for Register CFG_VIN2A_D12_OUT
IODELAYCONFIG Module Register Manual
Table 20-2244 CFG_VIN2A_D13_IN
Address Offset0x0000 0A74
Physical Address0x4844 AA74InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_d13_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2245 Register Call Summary for Register CFG_VIN2A_D13_IN
IODELAYCONFIG Module Register Manual
Table 20-2246 CFG_VIN2A_D13_OEN
Address Offset0x0000 0A78
Physical Address0x4844 AA78InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_d13_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2247 Register Call Summary for Register CFG_VIN2A_D13_OEN
IODELAYCONFIG Module Register Manual
Table 20-2248 CFG_VIN2A_D13_OUT
Address Offset0x0000 0A7C
Physical Address0x4844 AA7CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_d13_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2249 Register Call Summary for Register CFG_VIN2A_D13_OUT
IODELAYCONFIG Module Register Manual
Table 20-2250 CFG_VIN2A_D14_IN
Address Offset0x0000 0A80
Physical Address0x4844 AA80InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_d14_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2251 Register Call Summary for Register CFG_VIN2A_D14_IN
IODELAYCONFIG Module Register Manual
Table 20-2252 CFG_VIN2A_D14_OEN
Address Offset0x0000 0A84
Physical Address0x4844 AA84InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_d14_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2253 Register Call Summary for Register CFG_VIN2A_D14_OEN
IODELAYCONFIG Module Register Manual
Table 20-2254 CFG_VIN2A_D14_OUT
Address Offset0x0000 0A88
Physical Address0x4844 AA88InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_d14_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2255 Register Call Summary for Register CFG_VIN2A_D14_OUT
IODELAYCONFIG Module Register Manual
Table 20-2256 CFG_VIN2A_D15_IN
Address Offset0x0000 0A8C
Physical Address0x4844 AA8CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_d15_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2257 Register Call Summary for Register CFG_VIN2A_D15_IN
IODELAYCONFIG Module Register Manual
Table 20-2258 CFG_VIN2A_D15_OEN
Address Offset0x0000 0A90
Physical Address0x4844 AA90InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_d15_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2259 Register Call Summary for Register CFG_VIN2A_D15_OEN
IODELAYCONFIG Module Register Manual
Table 20-2260 CFG_VIN2A_D15_OUT
Address Offset0x0000 0A94
Physical Address0x4844 AA94InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_d15_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2261 Register Call Summary for Register CFG_VIN2A_D15_OUT
IODELAYCONFIG Module Register Manual
Table 20-2262 CFG_VIN2A_D16_IN
Address Offset0x0000 0A98
Physical Address0x4844 AA98InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_d16_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2263 Register Call Summary for Register CFG_VIN2A_D16_IN
IODELAYCONFIG Module Register Manual
Table 20-2264 CFG_VIN2A_D16_OEN
Address Offset0x0000 0A9C
Physical Address0x4844 AA9CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_d16_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2265 Register Call Summary for Register CFG_VIN2A_D16_OEN
IODELAYCONFIG Module Register Manual
Table 20-2266 CFG_VIN2A_D16_OUT
Address Offset0x0000 0AA0
Physical Address0x4844 AAA0InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_d16_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2267 Register Call Summary for Register CFG_VIN2A_D16_OUT
IODELAYCONFIG Module Register Manual
Table 20-2268 CFG_VIN2A_D17_IN
Address Offset0x0000 0AA4
Physical Address0x4844 AAA4InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_d17_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2269 Register Call Summary for Register CFG_VIN2A_D17_IN
IODELAYCONFIG Module Register Manual
Table 20-2270 CFG_VIN2A_D17_OEN
Address Offset0x0000 0AA8
Physical Address0x4844 AAA8InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_d17_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2271 Register Call Summary for Register CFG_VIN2A_D17_OEN
IODELAYCONFIG Module Register Manual
Table 20-2272 CFG_VIN2A_D17_OUT
Address Offset0x0000 0AAC
Physical Address0x4844 AAACInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_d17_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2273 Register Call Summary for Register CFG_VIN2A_D17_OUT
IODELAYCONFIG Module Register Manual
Table 20-2274 CFG_VIN2A_D18_IN
Address Offset0x0000 0AB0
Physical Address0x4844 AAB0InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_d18_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2275 Register Call Summary for Register CFG_VIN2A_D18_IN
IODELAYCONFIG Module Register Manual
Table 20-2276 CFG_VIN2A_D18_OEN
Address Offset0x0000 0AB4
Physical Address0x4844 AAB4InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_d18_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2277 Register Call Summary for Register CFG_VIN2A_D18_OEN
IODELAYCONFIG Module Register Manual
Table 20-2278 CFG_VIN2A_D18_OUT
Address Offset0x0000 0AB8
Physical Address0x4844 AAB8InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_d18_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2279 Register Call Summary for Register CFG_VIN2A_D18_OUT
IODELAYCONFIG Module Register Manual
Table 20-2280 CFG_VIN2A_D19_IN
Address Offset0x0000 0ABC
Physical Address0x4844 AABCInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_d19_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2281 Register Call Summary for Register CFG_VIN2A_D19_IN
IODELAYCONFIG Module Register Manual
Table 20-2282 CFG_VIN2A_D19_OEN
Address Offset0x0000 0AC0
Physical Address0x4844 AAC0InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_d19_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2283 Register Call Summary for Register CFG_VIN2A_D19_OEN
IODELAYCONFIG Module Register Manual
Table 20-2284 CFG_VIN2A_D19_OUT
Address Offset0x0000 0AC4
Physical Address0x4844 AAC4InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_d19_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2285 Register Call Summary for Register CFG_VIN2A_D19_OUT
IODELAYCONFIG Module Register Manual
Table 20-2286 CFG_VIN2A_D1_IN
Address Offset0x0000 0AC8
Physical Address0x4844 AAC8InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_d1_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2287 Register Call Summary for Register CFG_VIN2A_D1_IN
IODELAYCONFIG Module Register Manual
Table 20-2288 CFG_VIN2A_D1_OEN
Address Offset0x0000 0ACC
Physical Address0x4844 AACCInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_d1_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2289 Register Call Summary for Register CFG_VIN2A_D1_OEN
IODELAYCONFIG Module Register Manual
Table 20-2290 CFG_VIN2A_D1_OUT
Address Offset0x0000 0AD0
Physical Address0x4844 AAD0InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_d1_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2291 Register Call Summary for Register CFG_VIN2A_D1_OUT
IODELAYCONFIG Module Register Manual
Table 20-2292 CFG_VIN2A_D20_IN
Address Offset0x0000 0AD4
Physical Address0x4844 AAD4InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_d20_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2293 Register Call Summary for Register CFG_VIN2A_D20_IN
IODELAYCONFIG Module Register Manual
Table 20-2294 CFG_VIN2A_D20_OEN
Address Offset0x0000 0AD8
Physical Address0x4844 AAD8InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_d20_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2295 Register Call Summary for Register CFG_VIN2A_D20_OEN
IODELAYCONFIG Module Register Manual
Table 20-2296 CFG_VIN2A_D20_OUT
Address Offset0x0000 0ADC
Physical Address0x4844 AADCInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_d20_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2297 Register Call Summary for Register CFG_VIN2A_D20_OUT
IODELAYCONFIG Module Register Manual
Table 20-2298 CFG_VIN2A_D21_IN
Address Offset0x0000 0AE0
Physical Address0x4844 AAE0InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_d21_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2299 Register Call Summary for Register CFG_VIN2A_D21_IN
IODELAYCONFIG Module Register Manual
Table 20-2300 CFG_VIN2A_D21_OEN
Address Offset0x0000 0AE4
Physical Address0x4844 AAE4InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_d21_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2301 Register Call Summary for Register CFG_VIN2A_D21_OEN
IODELAYCONFIG Module Register Manual
Table 20-2302 CFG_VIN2A_D21_OUT
Address Offset0x0000 0AE8
Physical Address0x4844 AAE8InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_d21_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2303 Register Call Summary for Register CFG_VIN2A_D21_OUT
IODELAYCONFIG Module Register Manual
Table 20-2304 CFG_VIN2A_D22_IN
Address Offset0x0000 0AEC
Physical Address0x4844 AAECInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_d22_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2305 Register Call Summary for Register CFG_VIN2A_D22_IN
IODELAYCONFIG Module Register Manual
Table 20-2306 CFG_VIN2A_D22_OEN
Address Offset0x0000 0AF0
Physical Address0x4844 AAF0InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_d22_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2307 Register Call Summary for Register CFG_VIN2A_D22_OEN
IODELAYCONFIG Module Register Manual
Table 20-2308 CFG_VIN2A_D22_OUT
Address Offset0x0000 0AF4
Physical Address0x4844 AAF4InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_d22_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2309 Register Call Summary for Register CFG_VIN2A_D22_OUT
IODELAYCONFIG Module Register Manual
Table 20-2310 CFG_VIN2A_D23_IN
Address Offset0x0000 0AF8
Physical Address0x4844 AAF8InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_d23_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2311 Register Call Summary for Register CFG_VIN2A_D23_IN
IODELAYCONFIG Module Register Manual
Table 20-2312 CFG_VIN2A_D23_OEN
Address Offset0x0000 0AFC
Physical Address0x4844 AAFCInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_d23_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2313 Register Call Summary for Register CFG_VIN2A_D23_OEN
IODELAYCONFIG Module Register Manual
Table 20-2314 CFG_VIN2A_D23_OUT
Address Offset0x0000 0B00
Physical Address0x4844 AB00InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_d23_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2315 Register Call Summary for Register CFG_VIN2A_D23_OUT
IODELAYCONFIG Module Register Manual
Table 20-2316 CFG_VIN2A_D2_IN
Address Offset0x0000 0B04
Physical Address0x4844 AB04InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_d2_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2317 Register Call Summary for Register CFG_VIN2A_D2_IN
IODELAYCONFIG Module Register Manual
Table 20-2318 CFG_VIN2A_D2_OEN
Address Offset0x0000 0B08
Physical Address0x4844 AB08InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_d2_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2319 Register Call Summary for Register CFG_VIN2A_D2_OEN
IODELAYCONFIG Module Register Manual
Table 20-2320 CFG_VIN2A_D2_OUT
Address Offset0x0000 0B0C
Physical Address0x4844 AB0CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_d2_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2321 Register Call Summary for Register CFG_VIN2A_D2_OUT
IODELAYCONFIG Module Register Manual
Table 20-2322 CFG_VIN2A_D3_IN
Address Offset0x0000 0B10
Physical Address0x4844 AB10InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_d3_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2323 Register Call Summary for Register CFG_VIN2A_D3_IN
IODELAYCONFIG Module Register Manual
Table 20-2324 CFG_VIN2A_D3_OEN
Address Offset0x0000 0B14
Physical Address0x4844 AB14InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_d3_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2325 Register Call Summary for Register CFG_VIN2A_D3_OEN
IODELAYCONFIG Module Register Manual
Table 20-2326 CFG_VIN2A_D3_OUT
Address Offset0x0000 0B18
Physical Address0x4844 AB18InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_d3_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2327 Register Call Summary for Register CFG_VIN2A_D3_OUT
IODELAYCONFIG Module Register Manual
Table 20-2328 CFG_VIN2A_D4_IN
Address Offset0x0000 0B1C
Physical Address0x4844 AB1CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_d4_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2329 Register Call Summary for Register CFG_VIN2A_D4_IN
IODELAYCONFIG Module Register Manual
Table 20-2330 CFG_VIN2A_D4_OEN
Address Offset0x0000 0B20
Physical Address0x4844 AB20InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_d4_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2331 Register Call Summary for Register CFG_VIN2A_D4_OEN
IODELAYCONFIG Module Register Manual
Table 20-2332 CFG_VIN2A_D4_OUT
Address Offset0x0000 0B24
Physical Address0x4844 AB24InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_d4_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2333 Register Call Summary for Register CFG_VIN2A_D4_OUT
IODELAYCONFIG Module Register Manual
Table 20-2334 CFG_VIN2A_D5_IN
Address Offset0x0000 0B28
Physical Address0x4844 AB28InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_d5_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2335 Register Call Summary for Register CFG_VIN2A_D5_IN
IODELAYCONFIG Module Register Manual
Table 20-2336 CFG_VIN2A_D5_OEN
Address Offset0x0000 0B2C
Physical Address0x4844 AB2CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_d5_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2337 Register Call Summary for Register CFG_VIN2A_D5_OEN
IODELAYCONFIG Module Register Manual
Table 20-2338 CFG_VIN2A_D5_OUT
Address Offset0x0000 0B30
Physical Address0x4844 AB30InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_d5_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2339 Register Call Summary for Register CFG_VIN2A_D5_OUT
IODELAYCONFIG Module Register Manual
Table 20-2340 CFG_VIN2A_D6_IN
Address Offset0x0000 0B34
Physical Address0x4844 AB34InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_d6_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2341 Register Call Summary for Register CFG_VIN2A_D6_IN
IODELAYCONFIG Module Register Manual
Table 20-2342 CFG_VIN2A_D6_OEN
Address Offset0x0000 0B38
Physical Address0x4844 AB38InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_d6_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2343 Register Call Summary for Register CFG_VIN2A_D6_OEN
IODELAYCONFIG Module Register Manual
Table 20-2344 CFG_VIN2A_D6_OUT
Address Offset0x0000 0B3C
Physical Address0x4844 AB3CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_d6_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2345 Register Call Summary for Register CFG_VIN2A_D6_OUT
IODELAYCONFIG Module Register Manual
Table 20-2346 CFG_VIN2A_D7_IN
Address Offset0x0000 0B40
Physical Address0x4844 AB40InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_d7_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2347 Register Call Summary for Register CFG_VIN2A_D7_IN
IODELAYCONFIG Module Register Manual
Table 20-2348 CFG_VIN2A_D7_OEN
Address Offset0x0000 0B44
Physical Address0x4844 AB44InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_d7_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2349 Register Call Summary for Register CFG_VIN2A_D7_OEN
IODELAYCONFIG Module Register Manual
Table 20-2350 CFG_VIN2A_D7_OUT
Address Offset0x0000 0B48
Physical Address0x4844 AB48InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_d7_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2351 Register Call Summary for Register CFG_VIN2A_D7_OUT
IODELAYCONFIG Module Register Manual
Table 20-2352 CFG_VIN2A_D8_IN
Address Offset0x0000 0B4C
Physical Address0x4844 AB4CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_d8_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2353 Register Call Summary for Register CFG_VIN2A_D8_IN
IODELAYCONFIG Module Register Manual
Table 20-2354 CFG_VIN2A_D8_OEN
Address Offset0x0000 0B50
Physical Address0x4844 AB50InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_d8_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2355 Register Call Summary for Register CFG_VIN2A_D8_OEN
IODELAYCONFIG Module Register Manual
Table 20-2356 CFG_VIN2A_D8_OUT
Address Offset0x0000 0B54
Physical Address0x4844 AB54InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_d8_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2357 Register Call Summary for Register CFG_VIN2A_D8_OUT
IODELAYCONFIG Module Register Manual
Table 20-2358 CFG_VIN2A_D9_IN
Address Offset0x0000 0B58
Physical Address0x4844 AB58InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_d9_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2359 Register Call Summary for Register CFG_VIN2A_D9_IN
IODELAYCONFIG Module Register Manual
Table 20-2360 CFG_VIN2A_D9_OEN
Address Offset0x0000 0B5C
Physical Address0x4844 AB5CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_d9_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2361 Register Call Summary for Register CFG_VIN2A_D9_OEN
IODELAYCONFIG Module Register Manual
Table 20-2362 CFG_VIN2A_D9_OUT
Address Offset0x0000 0B60
Physical Address0x4844 AB60InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_d9_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2363 Register Call Summary for Register CFG_VIN2A_D9_OUT
IODELAYCONFIG Module Register Manual
Table 20-2364 CFG_VIN2A_DE0_IN
Address Offset0x0000 0B64
Physical Address0x4844 AB64InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_de0_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2365 Register Call Summary for Register CFG_VIN2A_DE0_IN
IODELAYCONFIG Module Register Manual
Table 20-2366 CFG_VIN2A_DE0_OEN
Address Offset0x0000 0B68
Physical Address0x4844 AB68InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_de0_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2367 Register Call Summary for Register CFG_VIN2A_DE0_OEN
IODELAYCONFIG Module Register Manual
Table 20-2368 CFG_VIN2A_DE0_OUT
Address Offset0x0000 0B6C
Physical Address0x4844 AB6CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_de0_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2369 Register Call Summary for Register CFG_VIN2A_DE0_OUT
IODELAYCONFIG Module Register Manual
Table 20-2370 CFG_VIN2A_FLD0_IN
Address Offset0x0000 0B70
Physical Address0x4844 AB70InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_fld0_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2371 Register Call Summary for Register CFG_VIN2A_FLD0_IN
IODELAYCONFIG Module Register Manual
Table 20-2372 CFG_VIN2A_FLD0_OEN
Address Offset0x0000 0B74
Physical Address0x4844 AB74InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_fld0_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2373 Register Call Summary for Register CFG_VIN2A_FLD0_OEN
IODELAYCONFIG Module Register Manual
Table 20-2374 CFG_VIN2A_FLD0_OUT
Address Offset0x0000 0B78
Physical Address0x4844 AB78InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_fld0_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2375 Register Call Summary for Register CFG_VIN2A_FLD0_OUT
IODELAYCONFIG Module Register Manual
Table 20-2376 CFG_VIN2A_HSYNC0_IN
Address Offset0x0000 0B7C
Physical Address0x4844 AB7CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_hsync0_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2377 Register Call Summary for Register CFG_VIN2A_HSYNC0_IN
IODELAYCONFIG Module Register Manual
Table 20-2378 CFG_VIN2A_HSYNC0_OEN
Address Offset0x0000 0B80
Physical Address0x4844 AB80InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_hsync0_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2379 Register Call Summary for Register CFG_VIN2A_HSYNC0_OEN
IODELAYCONFIG Module Register Manual
Table 20-2380 CFG_VIN2A_HSYNC0_OUT
Address Offset0x0000 0B84
Physical Address0x4844 AB84InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_hsync0_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2381 Register Call Summary for Register CFG_VIN2A_HSYNC0_OUT
IODELAYCONFIG Module Register Manual
Table 20-2382 CFG_VIN2A_VSYNC0_IN
Address Offset0x0000 0B88
Physical Address0x4844 AB88InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_vsync0_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2383 Register Call Summary for Register CFG_VIN2A_VSYNC0_IN
IODELAYCONFIG Module Register Manual
Table 20-2384 CFG_VIN2A_VSYNC0_OEN
Address Offset0x0000 0B8C
Physical Address0x4844 AB8CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_vsync0_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2385 Register Call Summary for Register CFG_VIN2A_VSYNC0_OEN
IODELAYCONFIG Module Register Manual
Table 20-2386 CFG_VIN2A_VSYNC0_OUT
Address Offset0x0000 0B90
Physical Address0x4844 AB90InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vin2a_vsync0_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2387 Register Call Summary for Register CFG_VIN2A_VSYNC0_OUT
IODELAYCONFIG Module Register Manual
Table 20-2388 CFG_VOUT1_CLK_IN
Address Offset0x0000 0B94
Physical Address0x4844 AB94InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_clk_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2389 Register Call Summary for Register CFG_VOUT1_CLK_IN
IODELAYCONFIG Module Register Manual
Table 20-2390 CFG_VOUT1_CLK_OEN
Address Offset0x0000 0B98
Physical Address0x4844 AB98InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_clk_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2391 Register Call Summary for Register CFG_VOUT1_CLK_OEN
IODELAYCONFIG Module Register Manual
Table 20-2392 CFG_VOUT1_CLK_OUT
Address Offset0x0000 0B9C
Physical Address0x4844 AB9CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_clk_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2393 Register Call Summary for Register CFG_VOUT1_CLK_OUT
IODELAYCONFIG Module Register Manual
Table 20-2394 CFG_VOUT1_D0_IN
Address Offset0x0000 0BA0
Physical Address0x4844 ABA0InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_d0_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2395 Register Call Summary for Register CFG_VOUT1_D0_IN
IODELAYCONFIG Module Register Manual
Table 20-2396 CFG_VOUT1_D0_OEN
Address Offset0x0000 0BA4
Physical Address0x4844 ABA4InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_d0_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2397 Register Call Summary for Register CFG_VOUT1_D0_OEN
IODELAYCONFIG Module Register Manual
Table 20-2398 CFG_VOUT1_D0_OUT
Address Offset0x0000 0BA8
Physical Address0x4844 ABA8InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_d0_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2399 Register Call Summary for Register CFG_VOUT1_D0_OUT
IODELAYCONFIG Module Register Manual
Table 20-2400 CFG_VOUT1_D10_IN
Address Offset0x0000 0BAC
Physical Address0x4844 ABACInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_d10_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2401 Register Call Summary for Register CFG_VOUT1_D10_IN
IODELAYCONFIG Module Register Manual
Table 20-2402 CFG_VOUT1_D10_OEN
Address Offset0x0000 0BB0
Physical Address0x4844 ABB0InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_d10_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2403 Register Call Summary for Register CFG_VOUT1_D10_OEN
IODELAYCONFIG Module Register Manual
Table 20-2404 CFG_VOUT1_D10_OUT
Address Offset0x0000 0BB4
Physical Address0x4844 ABB4InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_d10_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2405 Register Call Summary for Register CFG_VOUT1_D10_OUT
IODELAYCONFIG Module Register Manual
Table 20-2406 CFG_VOUT1_D11_IN
Address Offset0x0000 0BB8
Physical Address0x4844 ABB8InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_d11_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2407 Register Call Summary for Register CFG_VOUT1_D11_IN
IODELAYCONFIG Module Register Manual
Table 20-2408 CFG_VOUT1_D11_OEN
Address Offset0x0000 0BBC
Physical Address0x4844 ABBCInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_d11_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2409 Register Call Summary for Register CFG_VOUT1_D11_OEN
IODELAYCONFIG Module Register Manual
Table 20-2410 CFG_VOUT1_D11_OUT
Address Offset0x0000 0BC0
Physical Address0x4844 ABC0InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_d11_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2411 Register Call Summary for Register CFG_VOUT1_D11_OUT
IODELAYCONFIG Module Register Manual
Table 20-2412 CFG_VOUT1_D12_IN
Address Offset0x0000 0BC4
Physical Address0x4844 ABC4InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_d12_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2413 Register Call Summary for Register CFG_VOUT1_D12_IN
IODELAYCONFIG Module Register Manual
Table 20-2414 CFG_VOUT1_D12_OEN
Address Offset0x0000 0BC8
Physical Address0x4844 ABC8InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_d12_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2415 Register Call Summary for Register CFG_VOUT1_D12_OEN
IODELAYCONFIG Module Register Manual
Table 20-2416 CFG_VOUT1_D12_OUT
Address Offset0x0000 0BCC
Physical Address0x4844 ABCCInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_d12_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2417 Register Call Summary for Register CFG_VOUT1_D12_OUT
IODELAYCONFIG Module Register Manual
Table 20-2418 CFG_VOUT1_D13_IN
Address Offset0x0000 0BD0
Physical Address0x4844 ABD0InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_d13_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2419 Register Call Summary for Register CFG_VOUT1_D13_IN
IODELAYCONFIG Module Register Manual
Table 20-2420 CFG_VOUT1_D13_OEN
Address Offset0x0000 0BD4
Physical Address0x4844 ABD4InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_d13_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2421 Register Call Summary for Register CFG_VOUT1_D13_OEN
IODELAYCONFIG Module Register Manual
Table 20-2422 CFG_VOUT1_D13_OUT
Address Offset0x0000 0BD8
Physical Address0x4844 ABD8InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_d13_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2423 Register Call Summary for Register CFG_VOUT1_D13_OUT
IODELAYCONFIG Module Register Manual
Table 20-2424 CFG_VOUT1_D14_IN
Address Offset0x0000 0BDC
Physical Address0x4844 ABDCInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_d14_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2425 Register Call Summary for Register CFG_VOUT1_D14_IN
IODELAYCONFIG Module Register Manual
Table 20-2426 CFG_VOUT1_D14_OEN
Address Offset0x0000 0BE0
Physical Address0x4844 ABE0InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_d14_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2427 Register Call Summary for Register CFG_VOUT1_D14_OEN
IODELAYCONFIG Module Register Manual
Table 20-2428 CFG_VOUT1_D14_OUT
Address Offset0x0000 0BE4
Physical Address0x4844 ABE4InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_d14_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2429 Register Call Summary for Register CFG_VOUT1_D14_OUT
IODELAYCONFIG Module Register Manual
Table 20-2430 CFG_VOUT1_D15_IN
Address Offset0x0000 0BE8
Physical Address0x4844 ABE8InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_d15_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2431 Register Call Summary for Register CFG_VOUT1_D15_IN
IODELAYCONFIG Module Register Manual
Table 20-2432 CFG_VOUT1_D15_OEN
Address Offset0x0000 0BEC
Physical Address0x4844 ABECInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_d15_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2433 Register Call Summary for Register CFG_VOUT1_D15_OEN
IODELAYCONFIG Module Register Manual
Table 20-2434 CFG_VOUT1_D15_OUT
Address Offset0x0000 0BF0
Physical Address0x4844 ABF0InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_d15_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2435 Register Call Summary for Register CFG_VOUT1_D15_OUT
IODELAYCONFIG Module Register Manual
Table 20-2436 CFG_VOUT1_D16_IN
Address Offset0x0000 0BF4
Physical Address0x4844 ABF4InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_d16_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2437 Register Call Summary for Register CFG_VOUT1_D16_IN
IODELAYCONFIG Module Register Manual
Table 20-2438 CFG_VOUT1_D16_OEN
Address Offset0x0000 0BF8
Physical Address0x4844 ABF8InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_d16_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2439 Register Call Summary for Register CFG_VOUT1_D16_OEN
IODELAYCONFIG Module Register Manual
Table 20-2440 CFG_VOUT1_D16_OUT
Address Offset0x0000 0BFC
Physical Address0x4844 ABFCInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_d16_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2441 Register Call Summary for Register CFG_VOUT1_D16_OUT
IODELAYCONFIG Module Register Manual
Table 20-2442 CFG_VOUT1_D17_IN
Address Offset0x0000 0C00
Physical Address0x4844 AC00InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_d17_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2443 Register Call Summary for Register CFG_VOUT1_D17_IN
IODELAYCONFIG Module Register Manual
Table 20-2444 CFG_VOUT1_D17_OEN
Address Offset0x0000 0C04
Physical Address0x4844 AC04InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_d17_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2445 Register Call Summary for Register CFG_VOUT1_D17_OEN
IODELAYCONFIG Module Register Manual
Table 20-2446 CFG_VOUT1_D17_OUT
Address Offset0x0000 0C08
Physical Address0x4844 AC08InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_d17_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2447 Register Call Summary for Register CFG_VOUT1_D17_OUT
IODELAYCONFIG Module Register Manual
Table 20-2448 CFG_VOUT1_D18_IN
Address Offset0x0000 0C0C
Physical Address0x4844 AC0CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_d18_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2449 Register Call Summary for Register CFG_VOUT1_D18_IN
IODELAYCONFIG Module Register Manual
Table 20-2450 CFG_VOUT1_D18_OEN
Address Offset0x0000 0C10
Physical Address0x4844 AC10InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_d18_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2451 Register Call Summary for Register CFG_VOUT1_D18_OEN
IODELAYCONFIG Module Register Manual
Table 20-2452 CFG_VOUT1_D18_OUT
Address Offset0x0000 0C14
Physical Address0x4844 AC14InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_d18_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2453 Register Call Summary for Register CFG_VOUT1_D18_OUT
IODELAYCONFIG Module Register Manual
Table 20-2454 CFG_VOUT1_D19_IN
Address Offset0x0000 0C18
Physical Address0x4844 AC18InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_d19_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2455 Register Call Summary for Register CFG_VOUT1_D19_IN
IODELAYCONFIG Module Register Manual
Table 20-2456 CFG_VOUT1_D19_OEN
Address Offset0x0000 0C1C
Physical Address0x4844 AC1CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_d19_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2457 Register Call Summary for Register CFG_VOUT1_D19_OEN
IODELAYCONFIG Module Register Manual
Table 20-2458 CFG_VOUT1_D19_OUT
Address Offset0x0000 0C20
Physical Address0x4844 AC20InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_d19_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2459 Register Call Summary for Register CFG_VOUT1_D19_OUT
IODELAYCONFIG Module Register Manual
Table 20-2460 CFG_VOUT1_D1_IN
Address Offset0x0000 0C24
Physical Address0x4844 AC24InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_d1_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2461 Register Call Summary for Register CFG_VOUT1_D1_IN
IODELAYCONFIG Module Register Manual
Table 20-2462 CFG_VOUT1_D1_OEN
Address Offset0x0000 0C28
Physical Address0x4844 AC28InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_d1_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2463 Register Call Summary for Register CFG_VOUT1_D1_OEN
IODELAYCONFIG Module Register Manual
Table 20-2464 CFG_VOUT1_D1_OUT
Address Offset0x0000 0C2C
Physical Address0x4844 AC2CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_d1_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2465 Register Call Summary for Register CFG_VOUT1_D1_OUT
IODELAYCONFIG Module Register Manual
Table 20-2466 CFG_VOUT1_D20_IN
Address Offset0x0000 0C30
Physical Address0x4844 AC30InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_d20_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2467 Register Call Summary for Register CFG_VOUT1_D20_IN
IODELAYCONFIG Module Register Manual
Table 20-2468 CFG_VOUT1_D20_OEN
Address Offset0x0000 0C34
Physical Address0x4844 AC34InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_d20_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2469 Register Call Summary for Register CFG_VOUT1_D20_OEN
IODELAYCONFIG Module Register Manual
Table 20-2470 CFG_VOUT1_D20_OUT
Address Offset0x0000 0C38
Physical Address0x4844 AC38InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_d20_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2471 Register Call Summary for Register CFG_VOUT1_D20_OUT
IODELAYCONFIG Module Register Manual
Table 20-2472 CFG_VOUT1_D21_IN
Address Offset0x0000 0C3C
Physical Address0x4844 AC3CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_d21_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2473 Register Call Summary for Register CFG_VOUT1_D21_IN
IODELAYCONFIG Module Register Manual
Table 20-2474 CFG_VOUT1_D21_OEN
Address Offset0x0000 0C40
Physical Address0x4844 AC40InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_d21_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2475 Register Call Summary for Register CFG_VOUT1_D21_OEN
IODELAYCONFIG Module Register Manual
Table 20-2476 CFG_VOUT1_D21_OUT
Address Offset0x0000 0C44
Physical Address0x4844 AC44InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_d21_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2477 Register Call Summary for Register CFG_VOUT1_D21_OUT
IODELAYCONFIG Module Register Manual
Table 20-2478 CFG_VOUT1_D22_IN
Address Offset0x0000 0C48
Physical Address0x4844 AC48InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_d22_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2479 Register Call Summary for Register CFG_VOUT1_D22_IN
IODELAYCONFIG Module Register Manual
Table 20-2480 CFG_VOUT1_D22_OEN
Address Offset0x0000 0C4C
Physical Address0x4844 AC4CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_d22_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2481 Register Call Summary for Register CFG_VOUT1_D22_OEN
IODELAYCONFIG Module Register Manual
Table 20-2482 CFG_VOUT1_D22_OUT
Address Offset0x0000 0C50
Physical Address0x4844 AC50InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_d22_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2483 Register Call Summary for Register CFG_VOUT1_D22_OUT
IODELAYCONFIG Module Register Manual
Table 20-2484 CFG_VOUT1_D23_IN
Address Offset0x0000 0C54
Physical Address0x4844 AC54InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_d23_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2485 Register Call Summary for Register CFG_VOUT1_D23_IN
IODELAYCONFIG Module Register Manual
Table 20-2486 CFG_VOUT1_D23_OEN
Address Offset0x0000 0C58
Physical Address0x4844 AC58InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_d23_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2487 Register Call Summary for Register CFG_VOUT1_D23_OEN
IODELAYCONFIG Module Register Manual
Table 20-2488 CFG_VOUT1_D23_OUT
Address Offset0x0000 0C5C
Physical Address0x4844 AC5CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_d23_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2489 Register Call Summary for Register CFG_VOUT1_D23_OUT
IODELAYCONFIG Module Register Manual
Table 20-2490 CFG_VOUT1_D2_IN
Address Offset0x0000 0C60
Physical Address0x4844 AC60InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_d2_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2491 Register Call Summary for Register CFG_VOUT1_D2_IN
IODELAYCONFIG Module Register Manual
Table 20-2492 CFG_VOUT1_D2_OEN
Address Offset0x0000 0C64
Physical Address0x4844 AC64InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_d2_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2493 Register Call Summary for Register CFG_VOUT1_D2_OEN
IODELAYCONFIG Module Register Manual
Table 20-2494 CFG_VOUT1_D2_OUT
Address Offset0x0000 0C68
Physical Address0x4844 AC68InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_d2_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2495 Register Call Summary for Register CFG_VOUT1_D2_OUT
IODELAYCONFIG Module Register Manual
Table 20-2496 CFG_VOUT1_D3_IN
Address Offset0x0000 0C6C
Physical Address0x4844 AC6CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_d3_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2497 Register Call Summary for Register CFG_VOUT1_D3_IN
IODELAYCONFIG Module Register Manual
Table 20-2498 CFG_VOUT1_D3_OEN
Address Offset0x0000 0C70
Physical Address0x4844 AC70InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_d3_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2499 Register Call Summary for Register CFG_VOUT1_D3_OEN
IODELAYCONFIG Module Register Manual
Table 20-2500 CFG_VOUT1_D3_OUT
Address Offset0x0000 0C74
Physical Address0x4844 AC74InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_d3_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2501 Register Call Summary for Register CFG_VOUT1_D3_OUT
IODELAYCONFIG Module Register Manual
Table 20-2502 CFG_VOUT1_D4_IN
Address Offset0x0000 0C78
Physical Address0x4844 AC78InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_d4_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2503 Register Call Summary for Register CFG_VOUT1_D4_IN
IODELAYCONFIG Module Register Manual
Table 20-2504 CFG_VOUT1_D4_OEN
Address Offset0x0000 0C7C
Physical Address0x4844 AC7CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_d4_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2505 Register Call Summary for Register CFG_VOUT1_D4_OEN
IODELAYCONFIG Module Register Manual
Table 20-2506 CFG_VOUT1_D4_OUT
Address Offset0x0000 0C80
Physical Address0x4844 AC80InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_d4_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2507 Register Call Summary for Register CFG_VOUT1_D4_OUT
IODELAYCONFIG Module Register Manual
Table 20-2508 CFG_VOUT1_D5_IN
Address Offset0x0000 0C84
Physical Address0x4844 AC84InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_d5_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2509 Register Call Summary for Register CFG_VOUT1_D5_IN
IODELAYCONFIG Module Register Manual
Table 20-2510 CFG_VOUT1_D5_OEN
Address Offset0x0000 0C88
Physical Address0x4844 AC88InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_d5_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2511 Register Call Summary for Register CFG_VOUT1_D5_OEN
IODELAYCONFIG Module Register Manual
Table 20-2512 CFG_VOUT1_D5_OUT
Address Offset0x0000 0C8C
Physical Address0x4844 AC8CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_d5_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2513 Register Call Summary for Register CFG_VOUT1_D5_OUT
IODELAYCONFIG Module Register Manual
Table 20-2514 CFG_VOUT1_D6_IN
Address Offset0x0000 0C90
Physical Address0x4844 AC90InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_d6_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2515 Register Call Summary for Register CFG_VOUT1_D6_IN
IODELAYCONFIG Module Register Manual
Table 20-2516 CFG_VOUT1_D6_OEN
Address Offset0x0000 0C94
Physical Address0x4844 AC94InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_d6_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2517 Register Call Summary for Register CFG_VOUT1_D6_OEN
IODELAYCONFIG Module Register Manual
Table 20-2518 CFG_VOUT1_D6_OUT
Address Offset0x0000 0C98
Physical Address0x4844 AC98InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_d6_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2519 Register Call Summary for Register CFG_VOUT1_D6_OUT
IODELAYCONFIG Module Register Manual
Table 20-2520 CFG_VOUT1_D7_IN
Address Offset0x0000 0C9C
Physical Address0x4844 AC9CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_d7_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2521 Register Call Summary for Register CFG_VOUT1_D7_IN
IODELAYCONFIG Module Register Manual
Table 20-2522 CFG_VOUT1_D7_OEN
Address Offset0x0000 0CA0
Physical Address0x4844 ACA0InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_d7_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2523 Register Call Summary for Register CFG_VOUT1_D7_OEN
IODELAYCONFIG Module Register Manual
Table 20-2524 CFG_VOUT1_D7_OUT
Address Offset0x0000 0CA4
Physical Address0x4844 ACA4InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_d7_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2525 Register Call Summary for Register CFG_VOUT1_D7_OUT
IODELAYCONFIG Module Register Manual
Table 20-2526 CFG_VOUT1_D8_IN
Address Offset0x0000 0CA8
Physical Address0x4844 ACA8InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_d8_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2527 Register Call Summary for Register CFG_VOUT1_D8_IN
IODELAYCONFIG Module Register Manual
Table 20-2528 CFG_VOUT1_D8_OEN
Address Offset0x0000 0CAC
Physical Address0x4844 ACACInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_d8_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2529 Register Call Summary for Register CFG_VOUT1_D8_OEN
IODELAYCONFIG Module Register Manual
Table 20-2530 CFG_VOUT1_D8_OUT
Address Offset0x0000 0CB0
Physical Address0x4844 ACB0InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_d8_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2531 Register Call Summary for Register CFG_VOUT1_D8_OUT
IODELAYCONFIG Module Register Manual
Table 20-2532 CFG_VOUT1_D9_IN
Address Offset0x0000 0CB4
Physical Address0x4844 ACB4InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_d9_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2533 Register Call Summary for Register CFG_VOUT1_D9_IN
IODELAYCONFIG Module Register Manual
Table 20-2534 CFG_VOUT1_D9_OEN
Address Offset0x0000 0CB8
Physical Address0x4844 ACB8InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_d9_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2535 Register Call Summary for Register CFG_VOUT1_D9_OEN
IODELAYCONFIG Module Register Manual
Table 20-2536 CFG_VOUT1_D9_OUT
Address Offset0x0000 0CBC
Physical Address0x4844 ACBCInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_d9_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2537 Register Call Summary for Register CFG_VOUT1_D9_OUT
IODELAYCONFIG Module Register Manual
Table 20-2538 CFG_VOUT1_DE_IN
Address Offset0x0000 0CC0
Physical Address0x4844 ACC0InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_de_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2539 Register Call Summary for Register CFG_VOUT1_DE_IN
IODELAYCONFIG Module Register Manual
Table 20-2540 CFG_VOUT1_DE_OEN
Address Offset0x0000 0CC4
Physical Address0x4844 ACC4InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_de_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2541 Register Call Summary for Register CFG_VOUT1_DE_OEN
IODELAYCONFIG Module Register Manual
Table 20-2542 CFG_VOUT1_DE_OUT
Address Offset0x0000 0CC8
Physical Address0x4844 ACC8InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_de_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2543 Register Call Summary for Register CFG_VOUT1_DE_OUT
IODELAYCONFIG Module Register Manual
Table 20-2544 CFG_VOUT1_FLD_IN
Address Offset0x0000 0CCC
Physical Address0x4844 ACCCInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_fld_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2545 Register Call Summary for Register CFG_VOUT1_FLD_IN
IODELAYCONFIG Module Register Manual
Table 20-2546 CFG_VOUT1_FLD_OEN
Address Offset0x0000 0CD0
Physical Address0x4844 ACD0InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_fld_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2547 Register Call Summary for Register CFG_VOUT1_FLD_OEN
IODELAYCONFIG Module Register Manual
Table 20-2548 CFG_VOUT1_FLD_OUT
Address Offset0x0000 0CD4
Physical Address0x4844 ACD4InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_fld_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2549 Register Call Summary for Register CFG_VOUT1_FLD_OUT
IODELAYCONFIG Module Register Manual
Table 20-2550 CFG_VOUT1_HSYNC_IN
Address Offset0x0000 0CD8
Physical Address0x4844 ACD8InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_hsync_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2551 Register Call Summary for Register CFG_VOUT1_HSYNC_IN
IODELAYCONFIG Module Register Manual
Table 20-2552 CFG_VOUT1_HSYNC_OEN
Address Offset0x0000 0CDC
Physical Address0x4844 ACDCInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_hsync_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2553 Register Call Summary for Register CFG_VOUT1_HSYNC_OEN
IODELAYCONFIG Module Register Manual
Table 20-2554 CFG_VOUT1_HSYNC_OUT
Address Offset0x0000 0CE0
Physical Address0x4844 ACE0InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_hsync_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2555 Register Call Summary for Register CFG_VOUT1_HSYNC_OUT
IODELAYCONFIG Module Register Manual
Table 20-2556 CFG_VOUT1_VSYNC_IN
Address Offset0x0000 0CE4
Physical Address0x4844 ACE4InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_vsync_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2557 Register Call Summary for Register CFG_VOUT1_VSYNC_IN
IODELAYCONFIG Module Register Manual
Table 20-2558 CFG_VOUT1_VSYNC_OEN
Address Offset0x0000 0CE8
Physical Address0x4844 ACE8InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_vsync_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2559 Register Call Summary for Register CFG_VOUT1_VSYNC_OEN
IODELAYCONFIG Module Register Manual
Table 20-2560 CFG_VOUT1_VSYNC_OUT
Address Offset0x0000 0CEC
Physical Address0x4844 ACECInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_vout1_vsync_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2561 Register Call Summary for Register CFG_VOUT1_VSYNC_OUT
IODELAYCONFIG Module Register Manual
Table 20-2562 CFG_XREF_CLK0_IN
Address Offset0x0000 0CF0
Physical Address0x4844 ACF0InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_xref_clk0_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2563 Register Call Summary for Register CFG_XREF_CLK0_IN
IODELAYCONFIG Module Register Manual
Table 20-2564 CFG_XREF_CLK0_OEN
Address Offset0x0000 0CF4
Physical Address0x4844 ACF4InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_xref_clk0_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2565 Register Call Summary for Register CFG_XREF_CLK0_OEN
IODELAYCONFIG Module Register Manual
Table 20-2566 CFG_XREF_CLK0_OUT
Address Offset0x0000 0CF8
Physical Address0x4844 ACF8InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_xref_clk0_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2567 Register Call Summary for Register CFG_XREF_CLK0_OUT
IODELAYCONFIG Module Register Manual
Table 20-2568 CFG_XREF_CLK1_IN
Address Offset0x0000 0CFC
Physical Address0x4844 ACFCInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_xref_clk1_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2569 Register Call Summary for Register CFG_XREF_CLK1_IN
IODELAYCONFIG Module Register Manual
Table 20-2570 CFG_XREF_CLK1_OEN
Address Offset0x0000 0D00
Physical Address0x4844 AD00InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_xref_clk1_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2571 Register Call Summary for Register CFG_XREF_CLK1_OEN
IODELAYCONFIG Module Register Manual
Table 20-2572 CFG_XREF_CLK1_OUT
Address Offset0x0000 0D04
Physical Address0x4844 AD04InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_xref_clk1_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2573 Register Call Summary for Register CFG_XREF_CLK1_OUT
IODELAYCONFIG Module Register Manual
Table 20-2574 CFG_XREF_CLK2_IN
Address Offset0x0000 0D08
Physical Address0x4844 AD08InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_xref_clk2_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2575 Register Call Summary for Register CFG_XREF_CLK2_IN
IODELAYCONFIG Module Register Manual
Table 20-2576 CFG_XREF_CLK2_OEN
Address Offset0x0000 0D0C
Physical Address0x4844 AD0CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_xref_clk2_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2577 Register Call Summary for Register CFG_XREF_CLK2_OEN
IODELAYCONFIG Module Register Manual
Table 20-2578 CFG_XREF_CLK2_OUT
Address Offset0x0000 0D10
Physical Address0x4844 AD10InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_xref_clk2_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2579 Register Call Summary for Register CFG_XREF_CLK2_OUT
IODELAYCONFIG Module Register Manual
Table 20-2580 CFG_XREF_CLK3_IN
Address Offset0x0000 0D14
Physical Address0x4844 AD14InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_xref_clk3_in interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2581 Register Call Summary for Register CFG_XREF_CLK3_IN
IODELAYCONFIG Module Register Manual
Table 20-2582 CFG_XREF_CLK3_OEN
Address Offset0x0000 0D18
Physical Address0x4844 AD18InstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_xref_clk3_oen interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2583 Register Call Summary for Register CFG_XREF_CLK3_OEN
IODELAYCONFIG Module Register Manual
Table 20-2584 CFG_XREF_CLK3_OUT
Address Offset0x0000 0D1C
Physical Address0x4844 AD1CInstanceIODELAYCONFIG
DescriptionDelay Select Value in binary coded form for cfg_xref_clk3_out interface
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIGNATURERESERVEDLOCK_BITBINARY_DELAY
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:12SIGNATUREWrite to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)RW0x0
11RESERVEDR0x0
10LOCK_BITWhen '1', prevents HW update to this MMR. When '0', allows HW update of this MMR.RW0x0
9:0BINARY_DELAYDelay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad.RW0x0
Table 20-2585 Register Call Summary for Register CFG_XREF_CLK3_OUT
IODELAYCONFIG Module Register Manual