6 ECC Generation for Bootloader Code

The Cortex-R4/R5 CPU may generate speculative fetches to any location within the ATCM memory space. A speculative fetch to a location with invalid ECC, which is subsequently not used, will not create an abort, but will set the ESM flags for a correctable or uncorrectable error. An uncorrectable error will unconditionally cause the nERROR pin to toggle low. Therefore, care must be taken to generate the correct ECC for the entire ATCM space including the holes between sections and any unused or blank flash areas.

The easiest way to achieve this is to use the Linker to generate ECC data rather than the loader. Couple changes should be made:

• Add a ‘vfill = 0xFFFFFFFF' directive to the end of each line that maps to Flash in the Memory{} section of the command file. The 'vfill’ affects only the ECC generation. It instructs the ECC generator to treat the flash as if it were filled with the value 0xFFFFFFFF. It's a virtual fill, because the loader doesn't need to download 4Mbytes.
• Add memory regions corresponding to the ECC area of the flash bank to the Memory{} section.
• Add an ECC {} directive describing the algorithm that matches the device.

Once you make changes to linker command file so that the linker generates ECC for the project, it is necessary to change the loader settings so that the loader doesn't also try to generate ECC. On CCS “Flash Settings”, “Auto ECC Generation” should be unchecked, and “Flash Verification Settings” should be 'None'.

The following is a modified memory map of the linker command file used in the Cortex-R5 CAN bootloader project that you can use to replace the one generated by HALCoGen.

The ECC algorithm directive for Flash ECC devices should be added to generate ECC data.

/* Linker Settings */ --retain="*(.intvecs)" /* Memory Map */ MEMORY { /* Add a vfill directive to the end of each line that maps to Flash */ VECTORS (X) : origin=0x00000000 length=0x00000020 vfill = 0xffffffff FLASH0 (RX) : origin=0x00000020 length=0x001FFFE0 vfill = 0xffffffff FLASH1 (RX) : origin=0x00200000 length=0x00200000 vfill = 0xffffffff SRAM (RWX) : origin=0x08002000 length=0x0002D000 STACK (RW) : origin=0x08000000 length=0x00002000 /* USER CODE BEGIN (3) */ #if 1 /* Add memory regions corresponding to the ECC area of the flash bank */ ECC_VEC (R) : origin=(0xf0400000 + (start(VECTORS) >> 3)) length=(size(VECTORS) >> 3) ECC={algorithm=algoL2R5F021, input_range=VECTORS} ECC_FLA0 (R) : origin=(0xf0400000 + (start(FLASH0) >> 3)) length=(size(FLASH0) >> 3) ECC={algorithm=algoL2R5F021, input_range=FLASH0 } ECC_FLA1 (R) : origin=(0xf0400000 + (start(FLASH1) >> 3)) length=(size(FLASH1) >> 3) ECC={algorithm=algoL2R5F021, input_range=FLASH1 } #endif /* USER CODE END */ } /* USER CODE BEGIN (4) */ /* Add an ECC {} directive describing the algorithm that matches the device */ ECC { algoL2R5F021 : address_mask = 0xfffffff8 /*Address Bits 31:3 */ hamming_mask = R4 /*Use R4/R5 build in Mask */ parity_mask = 0x0c /*Set which ECC bits are Even & Odd parity */ mirroring = F021 /*RM57Lx and TMS570LCx are build in F021*/ } /* USER CODE END */