SNLU254A November   2020  – July 2022 DS160PT801

 

  1.   Abstract
  2.   Trademarks
  3. 1EVM Control and Configuration Information
    1. 1.1 Retimer Pin Controls
    2. 1.2 USB-to-SMBus Interface
    3. 1.3 PCIe PRSNT# Signal Control and Configuration
    4. 1.4 PCIe Reference Clock Control and Configuration
  4. 2EVM Power
    1. 2.1 EVM Current Sensing
  5. 3SigCon Architect GUI
    1. 3.1 Setup and Installation
    2. 3.2 Configuration Page
    3. 3.3 Low-Level Page
    4. 3.4 EEPROM Page
    5. 3.5 Control Panel
    6. 3.6 High-Level Page
    7. 3.7 Diagnostic Page
    8. 3.8 Eye Monitor Page
  6. 4PCB Material Information
    1. 4.1 DS160PT801 PCB Design
    2. 4.2 DS160PT801 PCB Stackup
    3. 4.3 DS160PT801 PCB Power Distribution
    4. 4.4 DS160PT801 Local Decoupling
  7. 5DS160PT801X16EVM Schematic
  8. 6Hardware BOM
  9. 7Revision History

4.3 DS160PT801 PCB Power Distribution

The riser card power distribution network was designed for observation and performance. Four power layers were dedicated to retimer supply voltages. This improves isolation between sensitive analog circuits and reduces losses where high dynamic currents are present.

Layer 3 and Layer 4 in the stackup are dedicated to the high-speed analog and digital supply rails. Both of these rails are nominally 1.1-V voltage levels. Using two layers as close to the mounted DS160PT801 as possible improves decoupling performance and aligns with internal package power supply design. Note that previous designs with a single PWR2_HSD supply are completely compatible with the Revision C pre-production silicon used on this EVM.


GUID-20201025-CA0I-XPFM-MNRH-LLJG9N4FZTPL-low.png

Figure 4-2 Layer 3 High-Speed Analog Analog Power Rails


GUID-20201025-CA0I-LLJB-P1K8-1SQCGGB2MVNM-low.png

Figure 4-3 Layer 4 Digital Power Rails

Layer 9 and Layer 10 are used to supply the analog voltages. These retimer supplies are lower current and have relatively constant demand so placements lower in the PCB stackup match their requirements. In addition to retimer supply needs, these layers are also used to provide 3-V and 12-V levels to the attached endpoint and regulator inputs.

As with any Serdes, hardware design power distribution is important to the overall device performance. To ensure optimal voltage levels at the retimer devices, the main 1.1-V regulator uses a remote sense line directly to the U2 retimer. This helps to compensate for any losses on the PCB between the regulator and the device load.


GUID-20201025-CA0I-K2PD-VW1P-NHSVPZVLHFGX-low.png

Figure 4-4 Layer 9 and 10 Power Distribution