SNIU028D February 2016 – September 2020 UCD3138 , UCD3138064 , UCD3138064A , UCD3138128 , UCD3138A , UCD3138A64
Address 00050030 – DPWM 3 Cycle Adjust B Register
Address 00070030 – DPWM 2 Cycle Adjust B Register
Address 000A0030 – DPWM 1 Cycle Adjust B Register
Address 000D0030 – DPWM 0 Cycle Adjust B Register
15 | 0 |
CYCLE_ADJUST_B |
R/W-0000 0000 0000 0000 |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | CYCLE_ADJUST_B | R/W | 0000 0000 0000 0000 | Adjusts the PWM B output signal. 16-bit signed number allows output signal to be delayed or sped up. |