SNIU028D February 2016 – September 2020 UCD3138 , UCD3138064 , UCD3138064A , UCD3138128 , UCD3138A , UCD3138A64
Address 0x0008_0034 – Front End Control 2 SAR Timing Register
Address 0x000B_0034– Front End Control 1 SAR Timing Register
Address 0x000E_0034 – Front End Control 0 SAR Timing Register
10 | 8 |
SAR_TIMING_UPPER |
R/W-100 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved | SAR_TIMING_MID | Reserved | SAR_TIMING_LOWER |
R-0 | R/W-011 | R-0 | R/W-010 |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
10-8 | SAR_TIMING _UPPER | R/W | 100 | Configures timing for Bits 9:8 of DAC setpoint for SAR Algorithm |
7 | Reserved | R | 0 | |
6-4 | SAR_TIMING_MID | R/W | 011 | Configures timing for Bits 7:6 of DAC setpoint for SAR Algorithm |
3 | Reserved | R | 0 | |
2-0 | SAR_TIMING _LOWER | R/W | 010 | Configures timing for Bits 5:0 of DAC setpoint for SAR Algorithm |