SNAU260A October 2020 – February 2021 LMK5C33216
ADVANCE INFORMATION
The APLL pages can be used to see detailed information on APLL behavior including the output dividers. It is possible to select between APLL frequency and DPLL frequency from this page to cascade to the output frequency boxes. By leaving APLL frequency (as shown in blue circle) selected, it is possible to type a VCO frequency into the PLL1 VCO frequency box (as shown in red circle) to have the fractional N value re-calculated.
When the DPLL is not used, the APLLs support an APLL only mode with a programmable 24-bit denominator. Support for this mode is currently not implemented in the TICS Pro software.
Figure 6-14 below shows the post dividers for PLL2 which includes PLL2 P2 for high speed open collector CML output, and below right shows the post dividers for PLL3 which includes PLL3 P1 with a CML MUX for bypassing BAW frequency directly to CML outputs or to be used with the PLL3 P1 divider for other outputs.