This Technical Reference Manual (TRM) can be used as a reference for the default register bits after the NVM download. The end user is responsible for validating the NVM settings for proper system use including any safety impact. This TRM does not provide information about the electrical characteristics, external components, package, or the functionality of the device. For this information and the full register map, refer to the device data sheet available on the at ti.com.
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The TPS65219/TPS65220 PMIC is a cost and space optimized solution that has flexible mapping to support the power requirements from different processors and SoCs. This PMIC contains seven regulators; 3 Buck regulators and 4 Low Drop-out Regulators (LDOs). Additionally, it has I2C, GPIOs and configurable multi-function pins. TPS65219 is characterized for -40°C to +105°C ambient temperature and TPS65220 is characterized for -40°C to +125°C ambient temperature. For safety sensitive applications, TPS65220 is functional safety capable. Therefore the TPS65220 development process is a TI-quality managed process, also functional safety FIT rate calculation and Failure mode distribution (FMD) is available for TPS65220. Whenever entering the INITIALIZE state, the PMIC reads its memory and loads the registers with the content from the EEPROM. The EEPROM loading takes approximately 2.3ms. The power-up sequence can only be executed after the EEPROM-load and all rails are discharged below the SCG threshold. This document describes the default configuration programmed on TPS6521907.
The following sections describe the default configuration on the EEPROM-backed registers. During the power-down-sequence, non-EEPROM-backed bits are reset, with the exception of unmasked interrupt bits and DISCHARGE_EN bits.
This section lists all the register settings that identify the supported temperature and the NVM ID with the corresponding revision that represents a list of default register settings.
Register Address | Field Name | Value | Description |
---|---|---|---|
0x00 | TI_DEVICE_ID (Bits: 7-5) |
0x00 | Device specific ID code to identify supported ambient and junction temperature. |
0x01 | TI_NVM_ID (Bits: 7-0) |
0x07 | Identification code for the NVM ID |
0x41 | NVM_REVISION (Bits: 7-5) |
0x2 | Identification code for the NVM revision |
0x26 | I2C_ADDRESS (Bits: 6-0) |
0x30 | I2C address |
This section describes the PMIC rails that are enabled in Active and Standby state. Any rail that is disabled by default has the option to be enabled through I2C once the device is in Active state and I2C communication is available. The transition between Active and Standby state can be triggered by hardware (when MODE/STBY pin is configured as STBY) or by software (register field: STBY_I2C_CTRL).
PMIC Rail | Register Address | Field Name | Value | Description |
---|---|---|---|---|
BUCK1 | 0x02 | BUCK1_EN | 0x1 | Enabled |
BUCK2 | 0x02 | BUCK2_EN | 0x1 | Enabled |
BUCK3 | 0x02 | BUCK3_EN | 0x1 | Enabled |
LDO1 | 0x02 | LDO1_EN | 0x1 | Enabled |
LDO2 | 0x02 | LDO2_EN | 0x1 | Enabled |
LDO3 | 0x02 | LDO3_EN | 0x1 | Enabled |
LDO4 | 0x02 | LDO4_EN | 0x1 | Enabled |
GPO1 | 0x1E | GPO1_EN | 0x1 | GPO1 enabled. The output state is Hi-Z. |
GPO2 | 0x1E | GPO2_EN | 0x0 | GPO2 disabled. The output state is low. |
GPIO | 0x1E | GPIO_EN | 0x0 | GPIO disabled. The output state is low. |
PMIC Rail | Register Address | Field Name | Value | Description |
---|---|---|---|---|
BUCK1 | 0x21 | BUCK1_STBY_EN | 0x1 | Enabled in STBY Mode |
BUCK2 | 0x21 | BUCK2_STBY_EN | 0x1 | Enabled in STBY Mode |
BUCK3 | 0x21 | BUCK3_STBY_EN | 0x1 | Enabled in STBY Mode |
LDO1 | 0x21 | LDO1_STBY_EN | 0x1 | Enabled in STBY Mode |
LDO2 | 0x21 | LDO2_STBY_EN | 0x1 | Enabled in STBY Mode |
LDO3 | 0x21 | LDO3_STBY_EN | 0x1 | Enabled in STBY Mode |
LDO4 | 0x21 | LDO4_STBY_EN | 0x1 | Enabled in STBY Mode |
GPO1 | 0x22 | GPO1_STBY_EN | 0x1 | Enabled in STBY Mode |
GPO2 | 0x22 | GPO2_STBY_EN | 0x0 | Disabled in STBY Mode |
GPIO | 0x22 | GPIO_STBY_EN | 0x0 | Disabled in STBY Mode |
This section describes how each of the PMIC power resources are configured.
PMIC Rail | Register Address | Field Name | Value | Description |
---|---|---|---|---|
Bucks Switching Mode (Global for all buck regulators) |
0x03 | BUCK_FF_ENABLE (Switching Mode) |
0x0 | Quasi-fixed frequency mode |
0x03 | BUCK_SS_ENABLE (Spread-Spectrum) |
0x0 | Spread spectrum disabled (only applicable if BUCK_FF_ENABLE=0x1) |
|
BUCK1 | 0x0A | BUCK1_VSET (Output Voltage) |
0xA | 0.850V |
0x0A | BUCK1_UV_THR_SEL (UV threshold) |
0x0 | -5% UV detection | |
0x0A | BUCK1_BW_SEL (Bandwidth) |
0x1 | high bandwidth | |
BUCK2 | 0x09 | BUCK2_VSET (Output Voltage) |
0x33 | 3.300V |
0x09 | BUCK2_UV_THR_SEL (UV threshold) |
0x0 | -5% UV detection | |
0x09 | BUCK2_BW_SEL (Bandwidth) |
0x1 | high bandwidth | |
0x03 | BUCK2_PHASE_CONFIG | 0x3 | 270 degrees (only applicable if BUCK_FF_ENABLE=0x1) |
|
BUCK3 | 0x08 | BUCK3_VSET (Output Voltage) |
0x18 | 1.200V |
0x08 | BUCK3_UV_THR_SEL (UV threshold) |
0x0 | -5% UV detection | |
0x08 | BUCK3_BW_SEL (Bandwidth) |
0x1 | high bandwidth | |
0x03 | BUCK3_PHASE_CONFIG | 0x2 | 180 degrees (only applicable if BUCK_FF_ENABLE=0x1) |
PMIC Rail | Setting | Register Address | Field Name | Value | Description |
---|---|---|---|---|---|
LDO1 | output voltage | 0x07 | LDO1_VSET | 0x36 | 3.300V |
Rail configuration | 0x07 | LDO1_LSW_CONFIG | 0x0 | Not Applicable (LDO1 not configured as load-switch) | |
0x07 | LDO1_BYP_CONFIG | 0x1 | LDO1 configured as Bypass (only applicable if LDO1_LSW_CONFIG=0x0) |
||
UV threshold | 0x1E | LDO1_UV_THR | 0x0 | -5% UV detection | |
LDO2 | output voltage | 0x06 | LDO2_VSET | 0x18 | 1.800V |
Rail configuration | 0x06 | LDO2_LSW_CONFIG | 0x0 | Not Applicable (LDO2 not configured as load-switch) | |
0x06 | LDO2_BYP_CONFIG | 0x0 | LDO2 configured as LDO (only applicable if LDO2_LSW_CONFIG=0x0) |
||
UV threshold | 0x1E | LDO2_UV_THR | 0x0 | -5% UV detection | |
LDO3 | output voltage | 0x05 | LDO3_VSET | 0x18 | 1.800V |
Rail configuration | 0x05 | LDO3_LSW_CONFIG | 0x0 | LDO Mode | |
ramp configuration | 0x05 | LDO3_SLOW_PU_RAMP | 0x1 | Slow ramp for power-up (~3ms) | |
UV threshold | 0x1E | LDO3_UV_THR | 0x0 | -5% UV detection | |
LDO4 | output voltage | 0x04 | LDO4_VSET | 0x26 | 2.500V |
Rail configuration | 0x04 | LDO4_LSW_CONFIG | 0x0 | LDO Mode | |
ramp configuration | 0x04 | LDO4_SLOW_PU_RAMP | 0x1 | Slow ramp for power-up (~3ms) | |
UV threshold | 0x1E | LDO4_UV_THR | 0x0 | -5% UV detection |
This section breaks down the power sequence settings for the device including the power-up/power-down slot assignment and duration. There may be slots in which no rail or GPIO is assigned to ramp. These "empty" slots can be used to add additional time and increase a slot duration.
PMIC Rail | Register Address | Field Name | Value | Description |
---|---|---|---|---|
BUCK1 | 0x11 | BUCK1_SEQUENCE_ON_SLOT | 0x5 | slot 5 |
BUCK2 | 0x10 | BUCK2_SEQUENCE_ON_SLOT | 0x0 | slot 0 |
BUCK3 | 0x0F | BUCK3_SEQUENCE_ON_SLOT | 0x4 | slot 4 |
LDO1 | 0x0E | LDO1_SEQUENCE_ON_SLOT | 0x2 | slot 2 |
LDO2 | 0x0D | LDO2_SEQUENCE_ON_SLOT | 0x2 | slot 2 |
LDO3 | 0x0C | LDO3_SEQUENCE_ON_SLOT | 0x2 | slot 2 |
LDO4 | 0x0B | LDO4_SEQUENCE_ON_SLOT | 0x2 | slot 2 |
GPO1 | 0x15 | GPO1_SEQUENCE_ON_SLOT | 0x2 | slot 2 |
GPO2 | 0x14 | GPO2_SEQUENCE_ON_SLOT | 0x0 | slot 0 |
GPIO | 0x13 | GPIO_SEQUENCE_ON_SLOT | 0x0 | slot 0 |
nRSTOUT | 0x12 | nRST_SEQUENCE_ON_SLOT | 0x9 | slot 9 |
Register Address | Field Name | Value | Description | |
---|---|---|---|---|
SLOT0 | 0x16 | POWER_UP_SLOT_0_DURATION | 0x1 | 1.5ms |
SLOT1 | 0x16 | POWER_UP_SLOT_1_DURATION | 0x0 | 0ms |
SLOT2 | 0x16 | POWER_UP_SLOT_2_DURATION | 0x2 | 3ms |
SLOT3 | 0x16 | POWER_UP_SLOT_3_DURATION | 0x1 | 1.5ms |
SLOT4 | 0x17 | POWER_UP_SLOT_4_DURATION | 0x1 | 1.5ms |
SLOT5 | 0x17 | POWER_UP_SLOT_5_DURATION | 0x1 | 1.5ms |
SLOT6 | 0x17 | POWER_UP_SLOT_6_DURATION | 0x0 | 0ms |
SLOT7 | 0x17 | POWER_UP_SLOT_7_DURATION | 0x3 | 10ms |
SLOT8 | 0x18 | POWER_UP_SLOT_8_DURATION | 0x1 | 1.5ms |
SLOT9 | 0x18 | POWER_UP_SLOT_9_DURATION | 0x3 | 10ms |
SLOT10 | 0x18 | POWER_UP_SLOT_10_DURATION | 0x0 | 0ms |
SLOT11 | 0x18 | POWER_UP_SLOT_11_DURATION | 0x0 | 0ms |
SLOT12 | 0x19 | POWER_UP_SLOT_12_DURATION | 0x0 | 0ms |
SLOT13 | 0x19 | POWER_UP_SLOT_13_DURATION | 0x0 | 0ms |
SLOT14 | 0x19 | POWER_UP_SLOT_14_DURATION | 0x0 | 0ms |
SLOT15 | 0x19 | POWER_UP_SLOT_15_DURATION | 0x0 | 0ms |
Register Address | Field Name | Value | Description | |
---|---|---|---|---|
BUCK1 | 0x11 | BUCK1_SEQUENCE_OFF_SLOT | 0x2 | slot 2 |
BUCK2 | 0x10 | BUCK2_SEQUENCE_OFF_SLOT | 0x4 | slot 4 |
BUCK3 | 0x0F | BUCK3_SEQUENCE_OFF_SLOT | 0x0 | slot 0 |
LDO1 | 0x0E | LDO1_SEQUENCE_OFF_SLOT | 0x2 | slot 2 |
LDO2 | 0x0D | LDO2_SEQUENCE_OFF_SLOT | 0x2 | slot 2 |
LDO3 | 0x0C | LDO3_SEQUENCE_OFF_SLOT | 0x2 | slot 2 |
LDO4 | 0x0B | LDO4_SEQUENCE_OFF_SLOT | 0x4 | slot 4 |
GPO1 | 0x15 | GPO1_SEQUENCE_OFF_SLOT | 0x2 | slot 2 |
GPO2 | 0x14 | GPO2_SEQUENCE_OFF_SLOT | 0x0 | slot 0 |
GPIO | 0x13 | GPIO_SEQUENCE_OFF_SLOT | 0x0 | slot 0 |
nRSTOUT | 0x12 | nRST_SEQUENCE_OFF_SLOT | 0x0 | slot 0 |
Register Address | Field Name | Value | Description | |
---|---|---|---|---|
SLOT0 | 0x16 | POWER_DOWN_SLOT_0_DURATION | 0x3 | 10ms |
SLOT1 | 0x16 | POWER_DOWN_SLOT_1_DURATION | 0x0 | 0ms |
SLOT2 | 0x16 | POWER_DOWN_SLOT_2_DURATION | 0x3 | 10ms |
SLOT3 | 0x16 | POWER_DOWN_SLOT_3_DURATION | 0x0 | 0ms |
SLOT4 | 0x17 | POWER_DOWN_SLOT_4_DURATION | 0x3 | 10ms |
SLOT5 | 0x17 | POWER_DOWN_SLOT_5_DURATION | 0x0 | 0ms |
SLOT6 | 0x17 | POWER_DOWN_SLOT_6_DURATION | 0x0 | 0ms |
SLOT7 | 0x17 | POWER_DOWN_SLOT_7_DURATION | 0x0 | 0ms |
SLOT8 | 0x18 | POWER_DOWN_SLOT_8_DURATION | 0x0 | 0ms |
SLOT9 | 0x18 | POWER_DOWN_SLOT_9_DURATION | 0x0 | 0ms |
SLOT10 | 0x18 | POWER_DOWN_SLOT_10_DURATION | 0x0 | 0ms |
SLOT11 | 0x18 | POWER_DOWN_SLOT_11_DURATION | 0x0 | 0ms |
SLOT12 | 0x19 | POWER_DOWN_SLOT_12_DURATION | 0x0 | 0ms |
SLOT13 | 0x19 | POWER_DOWN_SLOT_13_DURATION | 0x0 | 0ms |
SLOT14 | 0x19 | POWER_DOWN_SLOT_14_DURATION | 0x0 | 0ms |
SLOT15 | 0x19 | POWER_DOWN_SLOT_15_DURATION | 0x0 | 0ms |
The EN/PB/VSENSE pin is used to enable or disable the PMIC. This pin can be configured in one of three ways: EN, PB or VSENSE. The table below shows the default configuration for this pin. Please note, if the FSD (First supply detection) feature is enabled, the device goes from "No Power" to "Active" state, executing the power-up sequence as soon as the voltage on VSYS is above the POR threshold. In this scenario, the EN/PB/VSENSE pin is ignored ONLY during the first power-up.
Register Address | Field Name | Value | Description | |
---|---|---|---|---|
Pin Config | 0x20 | EN_PB_VSENSE_CONFIG | 0x00 | Device Enable Configuration |
ON Deglitch | 0x20 | EN_PB_VSENSE_DEGL | 0x0 | short (typ: 120us for EN/VSENSE and 200ms for PB) |
First Supply Detection | 0x20 | PU_ON_FSD | 0x1 | First Supply Detection (FSD) Enabled. |