SLUUCG8A June   2022  – August 2022 TPS51383

 

  1.   TPS51383 TPS51384 Evaluation Module User's Guide
  2.   Trademarks
  3. 1Introduction
  4. 2Performance Specification Summary
  5. 3External Components
  6. 4Test Setup and Results
    1. 4.1 Input and Output Connections
    2. 4.2 Start-Up Procedure
    3. 4.3 Start-Up
    4. 4.4 Shutdown
    5. 4.5 Output voltage ripple
  7. 5Board Layout
    1. 5.1 Layout
  8. 6Board Profile, Schematic, List of Materials, and Reference
    1. 6.1 Board Profile
    2. 6.2 Schematic
    3. 6.3 List of Materials
    4. 6.4 Reference
  9. 7Revision History

5.1 Layout

The following images show the board layout for the TPS51383EVM and TPS51384EVM. The TPS51383EVM and TPS51384EVM have four layers. The top layer contains the main power traces for VIN, VOUT, and GND. Also on the top layer are connections for the pins of the TPS51383EVM and TPS51384EVM and a large area filled with ground. Most of the signal traces are also located on the top side. The input decoupling capacitors, C3, C4, C5, and C6 are located as close to VIN pins and PGND pins of the IC as possible. The input and output connectors, test points, and all of the components are located on the top side. The bottom layer is a ground plane along with signal ground copper fill and the feedback trace from the point of regulation to the top of the resistor divider network. Two inner layers are ground plane.

Figure 5-1 TPS51383 and TPS51384 EVM Top Assembly
Figure 5-2 TPS51383 and TPS51384 EVM Top Layer
Figure 5-3 TPS51383 and TPS51384 EVM Inner1 Layer
Figure 5-4 TPS51383 and TPS51384 EVM Inner2 Layer
Figure 5-5 TPS51383 and TPS51384 EVM Bottom Layer