UCC28019A 8-Pin Continuous Conduction Mode (CCM) PFC Controller

7.3.2.1 VCC Undervoltage Lockout (UVLO)

During startup, Under-Voltage Lockout (UVLO) keeps the device in the off state until VCC rises above the 10.5-V enable threshold, VCC_ON. With a typical 1 V of hysteresis on UVLO to increase noise immunity, the device turns off when VCC drops to the 9.5-V disable threshold, VCC_OFF.

Figure 19. UVLO

If, during a brief ac-line dropout, the VCC voltage falls below the level necessary to bias the internal FAULT circuitry, the UVLO condition enables a special rapid discharge circuit which continues to discharge the VCOMP capacitors through a low impedance despite a complete lack of VCC. This helps to avoid an excessive current surge should the ac-line return while there is still substantial voltage stored on the VCOMP capacitors. Typically, these capacitors can be discharged to less than 1.2 V within 150 ms of loss of VCC.

7.3.2.2 Input Brown-Out Protection (IBOP)

The sensed line-voltage input, VINS, provides a means for the designer to set the desired mains RMS voltage level at which the PFC pre-regulator should start-up, V_ACturnon, as well as the desired mains RMS level at which it should shut down, V_ACturnoff. This prevents unwanted sustained system operation at or below a brown-out voltage, where excessive line current could overheat components. In addition, because VCC bias is not derived directly from the line voltage, IBOP protects the circuit from low line conditions that may not trigger the VCC UVLO turn-off.

Figure 20. Input Brown-Out Protection

Input line voltage is sensed directly from the rectified ac mains voltage through a resistor-divider filter network providing a scaled and filtered value at the VINS input. IBOP will put the device into standby mode when VINS falls (high to low) below 0.8 V, VINS_{BROWNOUT_th}. The device comes out of standby when VINS rises (low to high) above 1.5 V, VINS_{ENABLE_th}. Bias current sourced from VINS, I_{VINS_0V}, is less than 0.1 μA. With a bias current this low, there is little concern for any set-point error caused by this current flowing through the sensing network. The highest praticable value resistance for this network should be chosen to minimize power dissipation, especially in applications requiring low standby power. Be aware that higher resistance values are more susceptible to noise pickup, but low-noise PCB layout techniques can help mitigate this. Also, depending on the resistor type used and its voltage rating, R_VINS1 should be implemented with multiple resistors in series to reduce voltage stresses.

First, select R_VINS1 based on choosing the highest reasonable resistance value available for typical applications.

Then select R_VINS2 based on this value:

Equation 1.

Power dissipated in the resistor network is:

Equation 2.

The filter capacitor, C_VINS, has two functions. First, to attenuate the voltage ripple to levels between the enable and brown-out threshold to prevent ripple on VINS from falsely triggering IBOP when the converter is operating at low line. Second, C_VINS delays the brown-out protection operation for a desired number of line-half-cycle periods while still having a good response to an actual brown-out event.

The capacitor is chosen so that it will discharge to the VINS_{BROWNOUT_th} level after a delay of N number of line ½-cycles to accommodate ac-line dropout ride-through requirements.

Equation 3.

Where,

Equation 4.

and V_ACmin is the lowest normal operating rms input voltage.

7.3.2.3 Output Overvoltage Protection (OVP)

V_OUT(OVP) is the output voltage exceeding 5% of the rated value, causing VSENSE to exceed a 5.25-V threshold (5-V reference voltage + 5%), V_OVP. The normal control loop is bypassed and the GATE output is disabled until VSENSE falls below 5.25 V. V_OUT(OVP) is 420 V in a system with a 400-V rated output, for example.

7.3.2.4 Open Loop Protection/Standby (OLP/Standby)

If the output voltage feedback components were to fail and disconnect (open loop) the signal from the VSENSE input, then it is likely that the voltage error amp would increase the GATE output to maximum duty cycle. To prevent this, an internal pull-down forces VSENSE low. If the output voltage falls below 16% of its rated voltage, causing VSENSE to fall below 0.8 V, the device is put in standby, a state where the PWM switching is halted and the device is still on but draws standby current below 2.9 mA. This shutdown feature also gives the designer the option of pulling VSENSE low with an external switch.

7.3.2.5 ISENSE Open-Pin Protection (ISOP)

If the current feedback components were to fail and disconnect (open loop) the signal to the ISENSE input, then it is likely that the PWM stage would increase the GATE output to maximum duty cycle. To prevent this, an internal pull-up source drives ISENSE above 0.1 V so that a detector forces a state where the PWM switching is halted and the device is still on but draws standby current below 2.9 mA. This shutdown feature avoids continual operation in OVP and severely distorted input current.

7.3.2.6 Output Undervoltage Detection (UVD) and Enhanced Dynamic Response (EDR)

During normal operation, small perturbations on the PFC output voltage rarely exceed 5% deviation and the normal voltage control loop gain drives the output back into regulation. For large changes in line or load, if the output voltage drop exceeds -5%, an output under-voltage is detected (UVD) and Enhanced Dynamic Response (EDR) acts to speed up the slow response of the low-bandwidth voltage loop. During EDR, the transconductance of the voltage error amplifier is increased approximately 16 times to speed charging of the voltage-loop compensation capacitors to the level required for regulation. EDR is removed when VSENSE > 4.75 V. The EDR feature is not activated until soft start is completed.

Figure 21. OVP, UVD, OLP/ Standby, Soft Start Complete

Figure 22. Soft Start and Protection States

7.3.2.7 Over-Current Protection

Inductor current is sensed by R_ISENSE, a low value resistor in the return path of input rectifier. The other side of the resistor is tied to the system ground. The voltage is sensed on the rectifier side of the sense resistor and is always negative. The voltage at ISENSE is buffered by a fixed gain of -1.0 to provide a positive internal signal to the current functions. There are two over-current protection features; Soft Over-Current (SOC) protects against an overload on the output and Peak Current Limit (PCL) protects against inductor saturation.

Figure 23. Soft Over Current/ Peak Current Limit

7.3.2.8 Soft Over Current (SOC)

Soft Over-Current (SOC) limits the input current. SOC is activated when the current sense voltage on ISENSE reaches -0.73 V, affecting the internal VCOMP level, and the control loop is adjusted to reduce the PWM duty cycle.

7.3.2.9 Peak Current Limit (PCL)

Peak Current Limit (PCL) operates on a cycle-by-cycle basis. When the current sense voltage on ISENSE reaches -1.08 V, PCL is activated, immediately terminating the active switch cycle. PCL is leading-edge blanked to improve noise immunity against false triggering.

7.3.2.10 Current Sense Resistor, R_ISENSE

The current sense resistor, R_ISENSE, is sized using the minimum threshold value of Soft Over Current (SOC), V_SOC(min) = 0.66 V. To avoid triggering this threshold during normal operation, resulting in a decreased duty-cycle, the resistor is sized for an overload current of 10% more than the peak inductor current,

Equation 5.

Since R_ISENSE sees the average input current, worst-case power dissipation occurs at input low-line when input current is at its maximum. Power dissipated by the sense resistor is given by:

Equation 6.

Peak Current Limit (PCL) protection turns off the output driver when the voltage across the sense resistor reaches the PCL threshold, V_PCL. The absolute maximum peak current, I_PCL, is given by:

Equation 7.

Table 1. Design Goal Parameters

8.2.2.1 Current Calculations

First, determine the maximum average output current, I_OUT(max):

Equation 8.

Equation 9.

The maximum input RMS line current, I_{IN_RMS(max)}, is calculated using the parameters from Table 1 and the efficiency and power factor initial assumptions:

Equation 10.

Equation 11.

Based upon the calculated RMS value, the maximum peak input current, I_{IN_PEAK(max)}, and the maximum average input current, I_{IN_AVG(max)}, assuming the waveform is sinusoidal, can be determined.

Equation 12.

Equation 13.

Equation 14.

Equation 15.

8.2.2.2 Bridge Rectifier

Assuming a forward voltage drop, V_{F_BRIDGE}, of 0.95 V across the rectifier diodes, BR1, the power loss in the input bridge, P_BRIDGE, can be calculated:

Equation 16.

Equation 17.

8.2.2.3 Input Capacitor

Note that the UCC28019A is a continuous conduction mode controller and as such the inductor ripple current should be sized accordingly. High inductor ripple current has an impact on the CCM/DCM boundary and results in higher light-load THD, and also affects the choices for R_SENSE and C_ICOMP values. Allowing an inductor ripple current, I_RIPPLE, of 20% and a high frequency ripple voltage factor, ΔV_{RIPPLE_IN}, of 6%, the minimum input capacitor value, C_IN, is calculated by first determining the input ripple current, I_RIPPLE, and the input ripple voltage, V_{IN_RIPPLE(max)}:

Equation 18.

Equation 19.

Equation 20.

Equation 21.

Equation 22.

Equation 23.

Equation 24.

Equation 25.

The value for the input x-capacitor can now be calculated:

Equation 26.

Equation 27.

A 0.33 μF, 275 VAC ex-2 film capacitor was selected for C_IN.

8.2.2.4 Boost Inductor

The boost inductor, L_BST, is selected after determining the maximum inductor peak current, I_{L_PEAK(max)}:

Equation 28.

Equation 29.

The minimum value of the boost inductor is calculated based upon a worst case duty cycle of 0.5:

Equation 30.

Equation 31.

The actual value of the boost inductor that will be used is 1.25 mH.

The maximum duty cycle, DUTY_(max), can be calculated and will occur at the minimum input voltage:

Equation 32.

Equation 33.

Equation 34.

8.2.2.5 Boost Diode

The diode losses are estimated based upon the forward voltage drop, V_F, at 125°C and the reverse recovery charge, Q_RR, of the diode. This design uses a silicon-carbide diode. Although somewhat more expensive, it essentially eliminates the reverse recovery losses because Q_RR is equal to 0nC.

Equation 35.

Equation 36.

Equation 37.

Equation 38.

8.2.2.6 Switching Element

The conduction losses of the switch are estimated using the R_DS(on) of the FET at 125°C , found in the FET data sheet, and the calculated drain to source RMS current, I_{DS_RMS}:

Equation 39.

Equation 40.

Equation 41.

Equation 42.

Equation 43.

The switching losses are estimated using the rise time, (t_r), and fall time, (t_f), of the gate, and the output capacitance losses.

For the selected device:

Equation 44.

Equation 45.

Equation 46.

Equation 47.

Total FET losses:

Equation 48.

8.2.2.7 Sense Resistor

To accommodate the gain of the internal non-linear power limit, R_SENSE is sized such that it will trigger the soft over-current at 25% higher than the maximum peak inductor current using the minimum SOC threshold, V_SOC, of ISENSE.

Equation 49.

Equation 50.

Using a parallel combination of available standard value resistors, the sense resistor is chosen.

Equation 51.

The power dissipated across the sense resistor, P_Rsense, must be calculated:

Equation 52.

Equation 53.

The peak current limit, PCL, protection feature will be triggered when current through the sense resistor results in the voltage across R_SENSE to be equal to the V_PCL threshold. For a worst case analysis, the maximum V_PCL threshold is used:

Equation 54.

Equation 55.

To protect the device from inrush current, a standard 220-Ω resistor, R_ISENSE, is placed in series with the ISENSE pin. A 1000-pF capacitor, C_ISENSE, is placed close to the device to improve noise immunity on the ISENSE pin.

8.2.2.8 Output Capacitor

The output capacitor, C_OUT, is sized to meet holdup requirements of the converter. Assuming the downstream converters require the output of the PFC stage to never fall below 300 V, V_{OUT_HOLDUP(min)}, during one line cycle, t_HOLDUP = 1/f_LINE(min), the minimum calculated value for the capacitor is:

Equation 56.

Equation 57.

It is advisable to de-rate this capacitor value by 20%; the actual capacitor used is 270 μF.

Setting the maximum peak-to-peak output ripple voltage to be less than 5% of the output voltage will ensure that the ripple voltage will not trigger the output over-voltage or output under-voltage protection features of the controller. The maximum peak-to-peak ripple voltage, occurring at twice the line frequency, and the ripple current of the output capacitor are calculated:

Equation 58.

Equation 59.

Equation 60.

Equation 61.

The required ripple current rating at twice the line frequency is equal to:

Equation 62.

Equation 63.

There will also be a high frequency ripple current through the output capacitor:

Equation 64.

Equation 65.

The total ripple current in the output capacitor is the combination of both and the output capacitor must be selected accordingly:

Equation 66.

Equation 67.

8.2.2.9 Output Voltage Set Point

For low power dissipation and minimal contribution to the voltage set point error, it is recommended to use 1 MΩ for the top voltage feedback divider resistor, R_FB1. Multiple resistors in series are used due to the maximum allowable voltage across each. Using the internal 5-V reference, V_REF, select the bottom divider resistor, R_FB2, to meet the output voltage design goals.

Equation 68.

Equation 69.

Using 13 kΩ for R_FB2 results in a nominal output voltage set point of 391 V.

The over-voltage protection, OVD, will be triggered when the output voltage exceeds 5% of its nominal set-point:

Equation 70.

Equation 71.

The under-voltage detection, UVD, will be triggered when the output voltage falls below 5% of its nominal set-point:

Equation 72.

Equation 73.

A small capacitor on VSENSE must be added to filter out noise. Limit the value of the filter capacitor such that the RC time constant is less than 0.1 ms so as not to significantly reduce the control response time to output voltage deviations. With careful layout, the noise on this design is minimal, so an RC time constant of 0.01 ms was all that was needed:

Equation 74.

Equation 75.

8.2.2.10 Loop Compensation

The selection of compensation components, for both the current loop and the voltage loop, is made easier by using the UCC28019A Design Calculator spreadsheet that can be found in the Tools section of the UCC28019A product folder on the Texas Instruments website. The current loop is compensated first by determining the product of the internal loop variables, M₁M₂, using the internal controller constants K₁ and K_FQ:

Equation 76.

Equation 77.

Equation 78.

Equation 79.

Equation 80.

The VCOMP operating point is found on Figure 27. The Design Calculator spreadsheet enables the user to iteratively select the appropriate VCOMP value.

Figure 27. M₁M₂ vs. VCOMP

For the given M₁M₂ of 0.374 V/μs, the VCOMP is approximately equal to 4, as shown in Figure 27.

The individual loop factors, M₁ which is the current loop gain factor, and M₂ which is the voltage loop PWM ramp slope, are calculated using the following conditions:

The M₁ current loop gain factor:

• if : 0 < VCOMP < 2

Equation 81.

• if : 2 ≤ VCOMP < 3

Equation 82.

• if : 3 ≤ VCOMP < 5.5

Equation 83.

• if : 5.5 ≤ VCOMP < 7

Equation 84.

In this example:

Equation 85.

The M₂ PWM ramp slope:

• if : 0 < VCOMP < 1.5

Equation 86.

• if : 1.5 ≤ VCOMP < 5.6

Equation 87.

• if : 5.6 ≤ VCOMP < 7

Equation 88.

In this example:

Equation 89.

Verify that the product of the individual gain factors is approximately equal to the M₁M₂ factor determined above, if not, reselect VCOMP and recalculate M₁M₂.

Equation 90.

Equation 91.

The non-linear gain variable, M₃, can now be calculated:

• if : 0 < VCOMP < 3

Equation 92.

• if : 3 ≤ VCOMP < 7

Equation 93.

In this example:

Equation 94.

The frequency of the current averaging pole, f_IAVG, is chosen to be at 9.5 kHz. The required capacitor on ICOMP, C_ICOMP, for this is determined using the transconductance gain, g_mi, of the internal current amplifier:

Equation 95.

Equation 96.

Using a 1200 pF capacitor for C_ICOMP results in a current averaging pole frequency of 8.7 kHz:

Equation 97.

Equation 98.

The transfer function of the current loop can be plotted:

Equation 99.

Equation 100.

Figure 28. Bode Plot of the Current Averaging Circuit.

The open loop of the voltage transfer function, G_VL(f) contains the product of the voltage feedback gain, G_FB, and the gain from the pulse width modulator to the power stage, G_{PWM_PS}, which includes the pulse width modulator to power stage pole, f_{PWM_PS}. The plotted result is shown in Figure 29.

Equation 101.

Equation 102.

Equation 103.

Equation 104.

Equation 105.

Equation 106.

Equation 107.

Figure 29. Bode Plot of the Open Loop Voltage Transfer Function

The voltage error amplifier is compensated with a zero, f_ZERO, at the f_{PWM_PS} pole and a pole, f_POLE, placed at 20 Hz to reject high frequency noise and roll off the gain amplitude. The overall voltage loop crossover, f_V, is desired to be at 10 Hz. The compensation components of the voltage error amplifier are selected accordingly.

Equation 108.

Equation 109.

Equation 110.

Equation 111.

From Figure 29, and the Design Calculator spreadsheet, the open loop gain of the voltage transfer function at 10 Hz is approximately 0.667 dB. Estimating that the parallel capacitor, C_{VCOMP_P}, is much smaller than the series capacitor, C_VCOMP, the unity gain will be at f_V, and the zero will be at f_{PWM_PS}, the series compensation capacitor is determined:

Equation 112.

Equation 113.

A 3.3-μF capacitor is used for C_VCOMP.

Equation 114.

Equation 115.

A 33.2-kΩ resistor is used for R_VCOMP.

Equation 116.

Equation 117.

A 0.22-μF capacitor is used for C_{VCOMP_P}.

The total closed loop transfer function, G_{VL_total}, contains the combined stages and is plotted in Figure 30.

Equation 118.

Equation 119.

Figure 30. Closed Loop Voltage Bode Plot

8.2.2.11 Brown Out Protection

Select the top divider resistor into the VINS pin so as not to contribute excessive power loss. The extremely low bias current into VINS means the value of R_VINS1 could be hundreds of megaOhms. For practical purposes, a value less than 10 MΩ is usually chosen. Assuming approximately 150 times the input bias current through the resistor dividers will result in an R_VINS1 that is less than 10 MΩ , so as to not contribute excessive noise, and still maintain minimal power loss. The brown out protection will turn off the gate drive when the input falls below the user programmable minimum voltage, V_AC(off), and turn on when the input rises above V_AC(on).

Equation 120.

Equation 121.

Equation 122.

Equation 123.

Equation 124.

Equation 125.

A 6.5-M resistance is chosen.

Equation 126.

Equation 127.

The capacitor on VINS, C_VINS, is selected so that it's discharge time is greater than the output capacitor hold up time. C_OUT was chosen to meet one-cycle hold-up time so C_VINS will be chosen to meet 2.5 half-line cycles.

Equation 128.

Equation 129.

Equation 130.

Equation 131.

Table 3. Related Products