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  • TRF7970A Multiprotocol Fully Integrated 13.56-MHz RFID and Near Field Communication (NFC) Transceiver IC

    • SLOS743M August   2011  – March 2020

      PRODUCTION DATA.  

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  • TRF7970A Multiprotocol Fully Integrated 13.56-MHz RFID and Near Field Communication (NFC) Transceiver IC
  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Characteristics
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Signal Descriptions
      1. Table 4-1 Terminal Functions
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Electrical Characteristics
    5. 5.5 Thermal Resistance Characteristics
    6. 5.6 Switching Characteristics
  6. 6Detailed Description
    1. 6.1  Overview
      1. 6.1.1 RFID and NFC Operation – Reader and Writer
      2. 6.1.2 NFC Device Operation – Initiator
      3. 6.1.3 NFC Device Operation – Target
        1. 6.1.3.1 Active Target
        2. 6.1.3.2 Passive Target
        3. 6.1.3.3 Card Emulation
    2. 6.2  System Block Diagram
    3. 6.3  Power Supplies
      1. 6.3.1 Supply Arrangements
      2. 6.3.2 Supply Regulator Settings
      3. 6.3.3 Power Modes
    4. 6.4  Receiver – Analog Section
      1. 6.4.1 Main and Auxiliary Receivers
      2. 6.4.2 Receiver Gain and Filter Stages
    5. 6.5  Receiver – Digital Section
      1. 6.5.1 Received Signal Strength Indicator (RSSI)
        1. 6.5.1.1 Internal RSSI – Main and Auxiliary Receivers
        2. 6.5.1.2 External RSSI
    6. 6.6  Oscillator Section
    7. 6.7  Transmitter – Analog Section
    8. 6.8  Transmitter – Digital Section
    9. 6.9  Transmitter – External Power Amplifier and Subcarrier Detector
    10. 6.10 TRF7970A IC Communication Interface
      1. 6.10.1 General Introduction
        1. 6.10.1.1 Continuous Address Mode
        2. 6.10.1.2 Noncontinuous Address Mode (Single Address Mode)
        3. 6.10.1.3 Direct Command Mode
        4. 6.10.1.4 FIFO Operation
      2. 6.10.2 Parallel Interface Mode
      3. 6.10.3 Reception of Air Interface Data
      4. 6.10.4 Data Transmission From MCU to TRF7970A
      5. 6.10.5 Serial Interface Communication (SPI)
        1. 6.10.5.1 Serial Interface Mode With Slave Select (SS)
      6. 6.10.6 Direct Mode
    11. 6.11 TRF7970A Initialization
    12. 6.12 Special Direct Mode for Improved MIFARE Compatibility
    13. 6.13 NFC Modes
      1. 6.13.1 Target
      2. 6.13.2 Initiator
    14. 6.14 Direct Commands from MCU to Reader
      1. 6.14.1 Command Codes
        1. 6.14.1.1  Idle (0x00)
        2. 6.14.1.2  Software Initialization (0x03)
        3. 6.14.1.3  Initial RF Collision Avoidance (0x04)
        4. 6.14.1.4  Response RF Collision Avoidance (0x05)
        5. 6.14.1.5  Response RF Collision Avoidance (0x06, n = 0)
        6. 6.14.1.6  Reset FIFO (0x0F)
        7. 6.14.1.7  Transmission With CRC (0x11)
        8. 6.14.1.8  Transmission Without CRC (0x10)
        9. 6.14.1.9  Delayed Transmission With CRC (0x13)
        10. 6.14.1.10 Delayed Transmission Without CRC (0x12)
        11. 6.14.1.11 Transmit Next Time Slot (0x14)
        12. 6.14.1.12 Block Receiver (0x16)
        13. 6.14.1.13 Enable Receiver (0x17)
        14. 6.14.1.14 Test Internal RF (RSSI at RX Input With TX ON) (0x18)
        15. 6.14.1.15 Test External RF (RSSI at RX Input with TX OFF) (0x19)
    15. 6.15 Register Description
      1. 6.15.1 Register Preset
      2. 6.15.2 Register Overview
      3. 6.15.3 Detailed Register Description
        1. 6.15.3.1 Main Configuration Registers
          1. 6.15.3.1.1 Chip Status Control Register (0x00)
          2. 6.15.3.1.2 ISO Control Register (0x01)
        2. 6.15.3.2 Control Registers – Sublevel Configuration Registers
          1. 6.15.3.2.1  ISO/IEC 14443 TX Options Register (0x02)
          2. 6.15.3.2.2  ISO/IEC 14443 High-Bit-Rate and Parity Options Register (0x03)
          3. 6.15.3.2.3  TX Timer High Byte Control Register (0x04)
          4. 6.15.3.2.4  TX Timer Low Byte Control Register (0x05)
          5. 6.15.3.2.5  TX Pulse Length Control Register (0x06)
          6. 6.15.3.2.6  RX No Response Wait Time Register (0x07)
          7. 6.15.3.2.7  RX Wait Time Register (0x08)
          8. 6.15.3.2.8  Modulator and SYS_CLK Control Register (0x09)
          9. 6.15.3.2.9  RX Special Setting Register (0x0A)
          10. 6.15.3.2.10 Regulator and I/O Control Register (0x0B)
        3. 6.15.3.3 Status Registers
          1. 6.15.3.3.1  IRQ Status Register (0x0C)
          2. 6.15.3.3.2  Interrupt Mask Register (0x0D) and Collision Position Register (0x0E)
          3. 6.15.3.3.3  RSSI Levels and Oscillator Status Register (0x0F)
          4. 6.15.3.3.4  Special Functions Register (0x10)
          5. 6.15.3.3.5  Special Functions Register (0x11)
          6. 6.15.3.3.6  Adjustable FIFO IRQ Levels Register (0x14)
          7. 6.15.3.3.7  NFC Low Field Level Register (0x16)
          8. 6.15.3.3.8  NFCID1 Number Register (0x17)
          9. 6.15.3.3.9  NFC Target Detection Level Register (0x18)
          10. 6.15.3.3.10 NFC Target Protocol Register (0x19)
        4. 6.15.3.4 Test Registers
          1. 6.15.3.4.1 Test Register (0x1A)
          2. 6.15.3.4.2 Test Register (0x1B)
        5. 6.15.3.5 FIFO Control Registers
          1. 6.15.3.5.1 FIFO Status Register (0x1C)
          2. 6.15.3.5.2 TX Length Byte1 Register (0x1D), TX Length Byte2 Register (0x1E)
  7. 7Applications, Implementation, and Layout
    1. 7.1 TRF7970A Reader System Using SPI With SS Mode
      1. 7.1.1 General Application Considerations
      2. 7.1.2 Schematic
    2. 7.2 Layout Considerations
    3. 7.3 Impedance Matching TX_Out (Pin 5) to 50 Ω
    4. 7.4 Reader Antenna Design Guidelines
  8. 8Device and Documentation Support
    1. 8.1 Getting Started and Next Steps
    2. 8.2 Device Nomenclature
    3. 8.3 Tools and Software
    4. 8.4 Documentation Support
    5. 8.5 Support Resources
    6. 8.6 Trademarks
    7. 8.7 Electrostatic Discharge Caution
    8. 8.8 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
  10. IMPORTANT NOTICE
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DATA SHEET

TRF7970A Multiprotocol Fully Integrated 13.56-MHz RFID and Near Field Communication (NFC) Transceiver IC

1 Device Overview

1.1 Features

  • Supports Near Field Communication (NFC) Standards NFCIP-1 (ISO/IEC 18092) and NFCIP‑2 (ISO/IEC 21481)
  • Completely Integrated Protocol Handling for ISO/IEC 15693, ISO/IEC 18000-3, ISO/IEC 14443 A and B, and FeliCa™
  • Integrated Encoders, Decoders, and Data Framing for NFC Initiator, Active and Passive Target Operation for All Three Bit Rates (106 kbps, 212 kbps, 424 kbps), and Card Emulation
  • RF Field Detector With Programmable Wake-up Levels for NFC Passive Transponder Emulation Operation
  • RF Field Detector for NFC Physical Collision Avoidance
  • Integrated State Machine for ISO/IEC 14443 A Anticollision (Broken Bytes) Operation (Transponder Emulation or NFC Passive Target)
  • Input Voltage Range: 2.7 VDC to 5.5 VDC
  • Programmable Output Power: +20 dBm (100 mW), +23 dBm (200 mW)
  • Programmable I/O Voltage Levels From 1.8 VDC to 5.5 VDC
  • Programmable System Clock Frequency Output (RF, RF/2, RF/4) from 13.56-MHz or 27.12-MHz Crystal or Oscillator
  • Integrated Voltage Regulator Output for Other System Components (MCU, Peripherals, Indicators), 20 mA (Max)
  • Programmable Modulation Depth
  • Dual Receiver Architecture With RSSI for Elimination of "Read Holes" and Adjacent Reader System or Ambient In-Band Noise Detection
  • Programmable Power Modes for Ultra Low-Power System Design (Power Down <1 µA)
  • Parallel or SPI Interface (With 127-Byte FIFO)
  • Temperature Range: –40°C to 110°C
  • 32-Pin QFN Package (5 mm × 5 mm)

1.2 Applications

  • Mobile Devices (Tablets, Handsets)
  • Secure Pairing (Bluetooth®, Wi-Fi®, Other Paired Wireless Networks)
  • Public Transport or Event Ticketing
  • Passport or Payment (POS) Reader Systems
  • Short-Range Wireless Communication Tasks (Firmware Updates)
  • Product Identification or Authentication
  • Medical Equipment or Consumables
  • Access Control, Digital Door Locks
  • Sharing of Electronic Business Cards

1.3 Description

The TRF7970A device is an integrated analog front end (AFE) and multiprotocol data-framing device for a 13.56-MHz NFC/RFID system supporting all three NFC operation modes – reader/writer, peer-to-peer, and card emulation according to ISO/IEC 14443 A and B, Sony FeliCa, ISO/IEC 15693, NFCIP-1 (ISO/IEC 18092), and NFCIP-2 (ISO/IEC 21481). Built-in programming options make the device suitable for a wide range of applications for NFC, proximity, and vicinity identification systems.

The device is configured by selecting the desired protocol in the control registers. Direct access to all control registers allows fine tuning of various reader parameters as needed.

The TRF7970A device supports data rates up to 848 kbps with all framing and synchronization tasks for the ISO protocols onboard. The TRF7970A device also supports reader and writer mode for NFC Forum tag types 1, 2, 3, 4, and 5. Other standards and even custom protocols can be implemented by using one of the direct modes the device offers. These direct modes let the user fully control the AFE and also gain access to the raw subcarrier data or the unframed, but already ISO-formatted, data and the associated (extracted) clock signal.

The receiver system has a dual-input receiver architecture to maximize communication robustness. The receivers also include various automatic and manual gain control options. The received signal strength from transponders, ambient sources, or internal levels is available in the RSSI register.

A SPI or parallel interface can be used for the communication between the MCU and the TRF7970A device. When the built-in hardware encoders and decoders are used, transmit and receive functions use a 127-byte FIFO register. For direct transmit or receive functions, the encoders or decoders can be bypassed so the MCU can process the data in real time.

The TRF7970A device supports a wide supply voltage range of 2.7 V to 5.5 V and data communication levels from 1.8 V to 5.5 V for the MCU I/O interface.

The transmitter has selectable output power levels of 100 mW (+20 dBm) or 200 mW (+23 dBm) equivalent into a 50-Ω load when using a 5-V supply and supports OOK and ASK modulation with selectable modulation depth.

The built-in programmable auxiliary voltage regulator delivers up to 20 mA to supply an MCU and additional external circuits within the reader system.

Integrated RF field detector with programmable wake-up levels, eight selectable power modes, and ultra-low power operation enable easy development of robust and cost-efficient designs for long battery life.

Start evaluating the TRF7970A multiprotocol transceiver IC with the DLP-7970ABP.

Device Information

PART NUMBER PACKAGE BODY SIZE
TRF7970ARHB VQFN (32) 5 mm × 5 mm

1.4 Functional Block Diagram

Figure 1-1 shows the block diagram.

TRF7970A system_block_dgm_slos743.gifFigure 1-1 Block Diagram

2 Revision History

Changes from March 28, 2017 to March 11, 2020

  • Removed links to obsolete EVMs in Section 1.3DescriptionGo
  • Removed "(Optional)" from the step that begins "Write the Regulator and I/O Control register (0x0B)..." in Section 6.11TRF7970A InitializationGo
  • Updated linked documents in Section 7.4Reader Antenna Design GuidelinesGo
  • Removed obsolete EVMs in Section 8.3Tools and SoftwareGo

3 Device Characteristics

Table 3-1 lists the supported modes of operation for the TRF7970A device.

Table 3-1 Supported Modes of Operation

P2P INITIATOR OR READER/WRITER CARD EMULATION P2P TARGET
TECHNOLOGY BIT RATE
(kbps)		 TECHNOLOGY BIT RATE
(kbps)		 TECHNOLOGY BIT RATE
(kbps)
NFC-A and NFC-B
(ISO/IEC 14443 A and B)		 106, 212, 424, 848(1) NFC-A, NFC-B 106 NFC-A 106
NFC-F (JIS: X6319-4) 212, 424 N/A N/A NFC-F 212, 424
NFC-V (ISO/IEC 15693) 6.7, 26.7 N/A N/A N/A N/A
(1) 848 kbps applies to reader/writer mode only.

3.1 Related Products

For information about other devices in this family of products or related products, see the following links.

    Products for TI Wireless ConnectivityConnect more with the industry’s broadest wireless connectivity portfolio.
    Products for NFC / RFIDTI provides one of the industry’s most differentiated NFC and RFID product portfolios and is your solution to meet a broad range of NFC connectivity and RFID identification needs.
    Companion Products for TRF7970AReview products that are frequently purchased or used with this product.
    Reference Designs for TRF7970AThe TI Designs Reference Design Library is a robust reference design library that spans analog, embedded processor, and connectivity. Created by TI experts to help you jump start your system design, all TI Designs include schematic or block diagrams, BOMs, and design files to speed your time to market. Search and download designs at ti.com/tidesigns.

4 Terminal Configuration and Functions

4.1 Pin Diagram

Figure 4-1 shows the pinout for the 32-pin RHB package.

TRF7970A pinout_rhb32_slos743.gifFigure 4-1 32-Pin RHB Package (Top View)

4.2 Signal Descriptions

Table 4-1 describes the signals.

Table 4-1 Terminal Functions

TERMINAL TYPE (1) DESCRIPTION
NAME NO.
VDD_A 1 OUT Internal regulated supply (2.7 V to 3.4 V) for analog circuitry
VIN 2 SUP External supply input to chip (2.7 V to 5.5 V)
VDD_RF 3 OUT Internal regulated supply (2.7 V to 5 V), normally connected to VDD_PA (pin 4)
VDD_PA 4 INP Supply for PA; normally connected externally to VDD_RF (pin 3)
TX_OUT 5 OUT RF output (selectable output power, 100 mW or 200 mW, with VDD = 5 V)
VSS_PA 6 SUP Negative supply for PA; normally connected to circuit ground
VSS_RX 7 SUP Negative supply for RX inputs; normally connected to circuit ground
RX_IN1 8 INP Main RX input
RX_IN2 9 INP Auxiliary RX input
VSS 10 SUP Chip substrate ground
BAND_GAP 11 OUT Bandgap voltage (VBG = 1.6 V); internal analog voltage reference
ASK/OOK 12 BID Selection between ASK and OOK modulation (0 = ASK, 1 = OOK) for direct mode 0 or 1.
Can be configured as an output to provide the received analog signal output.
IRQ 13 OUT Interrupt request
MOD 14 INP External data modulation input for direct mode 0 or 1
OUT Subcarrier digital data output (see registers 0x1A and 0x1B)
VSS_A 15 SUP Negative supply for internal analog circuits; connected to GND
VDD_I/O 16 INP Supply for I/O communications (1.8 V to VIN) level shifter. VIN should be never exceeded.
I/O_0 17 BID I/O pin for parallel communication
I/O_1 18 BID I/O pin for parallel communication
I/O_2 19 BID I/O pin for parallel communication
TX enable (in special direct mode)
I/O_3 20 BID I/O pin for parallel communication
TX data (in special direct mode)
I/O_4 21 BID I/O pin for parallel communication
Slave select signal in SPI mode
I/O_5 22 BID I/O pin for parallel communication
Data clock output in direct mode 1 and special direct mode
I/O_6 23 BID I/O pin for parallel communication
MISO for serial communication (SPI)
Serial bit data output in direct mode 1 or subcarrier signal in direct mode 0
I/O_7 24 BID I/O pin for parallel communication.
MOSI for serial communication (SPI)
EN2 25 INP Selection of power down mode. If EN2 is connected to VIN, then VDD_X is active during power down mode 2 (for example, to supply the MCU).
DATA_CLK 26 INP Data clock input for MCU communication (parallel and serial)
SYS_CLK 27 OUT

If EN = 1 (EN2 = don't care) the system clock for MCU is configured. Depending on the crystal that is used, options are as follows (see register 0x09):

13.56-MHz crystal: Off, 3.39 MHz, 6.78 MHz, or 13.56 MHz

27.12-MHz crystal: Off, 6.78 MHz, 13.56 MHz, or 27.12 MHz
If EN = 0 and EN2 = 1, then system clock is set to 60 kHz
EN 28 INP Chip enable input (If EN = 0, then chip is in sleep or power-down mode).
VSS_D 29 SUP Negative supply for internal digital circuits
OSC_OUT 30 OUT Crystal or oscillator output
OSC_IN 31 INP Crystal or oscillator input
OUT Crystal oscillator output
VDD_X 32 OUT Internally regulated supply (2.7 V to 3.4 V) for digital circuit and external devices (for example, an MCU)
Thermal Pad PAD SUP Chip substrate ground
(1) SUP = Supply, INP = Input, BID = Bidirectional, OUT = Output

5 Specifications

5.1 Absolute Maximum Ratings(1)(2)

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VIN Input voltage range –0.3 6 V
IIN Maximum current VIN 150 mA
TJ Maximum operating virtual junction temperature Any condition 140 °C
Continuous operation, long-term reliability(3) 125 °C
TSTG Storage temperature –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions are not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to substrate ground terminal VSS.
(3) The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may result in reduced reliability or lifetime of the device.

5.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±500 V
Machine model (MM) ±200 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±2000 V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±500 V may actually have higher performance.

5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN TYP MAX UNIT
VIN Operating input voltage 2.7 5 5.5 V
TA Operating ambient temperature –40 25 110 °C
TJ Operating virtual junction temperature –40 25 125 °C
VIL Input voltage, logic low I/O lines, IRQ, SYS_CLK, DATA_CLK, EN, EN2, ASK/OOK, MOD 0.2 × VDD_I/O V
VIH Input voltage threshold, logic high I/O lines, IRQ, SYS_CLK, DATA_CLK, EN, EN2, ASK/OOK, MOD 0.8 × VDD_I/O V

 
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