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  • THS4509 Wideband, Low-Noise, Low-Distortion, Fully-Differential Amplifier

    • SLOS454I January   2005  – July 2016 THS4509

      PRODUCTION DATA.  

  • CONTENTS
  • SEARCH
  • THS4509 Wideband, Low-Noise, Low-Distortion, Fully-Differential Amplifier
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: VS+ - VS- = 5 V
    6. 7.6 Electrical Characteristics: VS+ - VS- = 3 V
    7. 7.7 Dissipation Ratings
    8. 7.8 Typical Characteristics
      1. 7.8.1 Typical Characteristics: VS+ - VS- = 5 V
      2. 7.8.2 Typical Characteristics: VS+ - VS- = 3 V
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Test Circuits
        1. 8.3.1.1 Frequency Response
        2. 8.3.1.2 Distortion and 1-dB Compression
        3. 8.3.1.3 S-Parameter, Slew Rate, Transient Response, Settling Time, Output Impedance, Overdrive, Output Voltage, Turnon, and Turnoff Time
        4. 8.3.1.4 CM Input
        5. 8.3.1.5 CMRR and PSRR
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Differential Input to Differential Output Amplifier
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Input Common-Mode Voltage Range
          2. 9.2.1.2.2 Setting the Output Common-Mode Voltage
          3. 9.2.1.2.3 Single-Supply Operation (3 V to 5 V)
          4. 9.2.1.2.4 THS4509 and ADS5500 Combined Performance
          5. 9.2.1.2.5 THS4509 and ADS5424 Combined Performance
        3. 9.2.1.3 Application Curve
      2. 9.2.2 Single-Ended Input to Differential Output Amplifier
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 General Guidelines
      2. 11.1.2 PowerPAD PCB Layout Considerations
    2. 11.2 Layout Example
    3. 11.3 PowerPAD Design Considerations
  12. 12Device and Documentation Support
    1. 12.1 Device Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
  14. IMPORTANT NOTICE
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DATA SHEET

THS4509 Wideband, Low-Noise, Low-Distortion, Fully-Differential Amplifier

1 Features

  • Fully-Differential Architecture
  • Centered Input Common-Mode Range
  • Output Common-Mode Control
  • Minimum Gain of 2 V/V (6 dB)
  • Bandwidth: 1900 MHz
  • Slew Rate: 6600 V/μs
  • 1% Settling Time: 2 ns
  • HD2: –75 dBc at 100 MHz
  • HD3: –80 dBc at 100 MHz
  • OIP3: 37 dBm at 70 MHz
  • Input Voltage Noise: 1.9 nV/√Hz (f > 10 MHz)
  • Power-Supply Voltage: 3 V to 5 V
  • Power-Supply Current: 37.7 mA
  • Power-Down Current: 0.65 mA

2 Applications

  • 5-V Data Acquisition Systems High
    Linearity ADC Amplifiers
  • Wireless Communication
  • Medical Imaging
  • Test and Measurement

3 Description

The THS4509 device is a wideband, fully-differential op amp designed for 5-V data acquisition systems. It has a low noise at 1.9 nV/√Hz, and low harmonic distortion of –75 dBc HD2 and –80 dBc HD3 at 100 MHz with 2 VPP, G = 10 dB, and 1-kΩ load. Slew rate is high at 6600 V/μs, and with settling time of 2 ns to 1% (2-V step), it is ideal for pulsed applications. It is designed for a minimum gain of 6 dB, but is optimized for gains of 10 dB.

To allow for DC coupling to analog-to-digital converters (ADCs), its unique output common-mode control circuit maintains the output common-mode voltage within 3-mV offset (typical) from the set voltage, when set within 0.5-V of midsupply, with less than 4-mV differential offset voltage. The common-mode set point is set to midsupply by internal circuitry, which may be overdriven from an external source.

The input and output are optimized for best performance with the common-mode voltages set to midsupply. Along with high performance at low power-supply voltage, this design makes it ideal for high-performance, single-supply 5-V data acquisition systems. The combined performance of the THS4509 in a gain of 10 dB driving the ADS5500 ADC, sampling at 125 MSPS, is 81-dBc SFDR and
69.1-dBc SNR with a –1 dBFS signal at 70 MHz.

The THS4509 is offered in a quad, leadless VQFN-16 package (RGT), and is characterized for operation over the full industrial temperature range from –40°C to +85°C.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
THS4509 VQFN (16) 3.00 mm × 3.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Test Configuration

THS4509 pg1_cir_app_los454.gif

Measured 3rd Order Intermodulation Spurious Signal Level

THS4509 pg1_cir_graph_los454.gif

4 Revision History

Changes from H Revision (November 2009) to I Revision

  • Added ESD Ratings table, Thermal Information table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section.Go
  • Deleted the Packaging/Ordering Information table, see POA at the end of the data sheet Go
  • Deleted the THS4509 EVM section to the Layout Example section Go

Changes from G Revision (May 2008) to H Revision

  • Changed title of Typical Characteristics: VS+ – VS– = 5 VGo
  • Deleted conditions from Typical Characteristics: VS+ – VS– = 5 V table of graphsGo
  • Changed title of Typical Characteristics: VS+ – VS– = 3 VGo
  • Deleted conditions from Typical Characteristics: VS+ – VS– = 3 V table of graphsGo
  • Added y-axis to Figure 87Go
  • Added y-axis to Figure 90Go
  • Changed item 10 in Layout Recommendations sectionGo
  • Added the PowerPAD PCB Layout Considerations sectionGo
  • Moved Figure 92 and associated paragraph to PowerPAD PCB Layout Considerations sectionGo
  • Added the PowerPAD Design Considerations sectionGo

Changes from F Revision (October 2007) to G Revision

  • Updated document formatGo
  • Changed common-mode range column for THS4509 and THS4513 rows in the Related Products tableGo
  • Added footnote 1 to Absolute Maximum Ratings tableGo
  • Added V (volts) to unit column of ESD ratings rows in Absolute Maximum Ratings tableGo
  • Changed VS+ – VS– = 5 V Input specifications from 1.75 V typ (common-mode input range high) to 1.4 V typ; –1.75 V (common-mode input range low) to –1.4 V; 1.35 MΩ || 1.77 pF (differential input impedance) to 1.3 MΩ || 1.8 pF; 1.02 MΩ || 2.26 pF (common-mode input impedance) to 1.0 MΩ || 2.3 pFGo
  • Changed VS+ – VS– = 3 V Input specifications from 0.75 V typ (common-mode input range high) to 0.4 V typ; –0.75 V (common-mode input range low) to –0.4 V; 1.35 MΩ || 1.77 pF (differential input impedance) to 1.3 MΩ || 1.8 pF; 1.02 MΩ || 2.26 pF (common-mode input impedance) to 1.0 MΩ || 2.3 pFGo

5 Device Comparison Table

DEVICE MIN. GAIN COMMON-MODE RANGE OF INPUT(1)
THS4508 6 dB –0.3 V to 2.3 V
THS4509 6 dB 1.1 V to 3.9 V
THS4511 0 dB –0.3 V to 2.3 V
THS4513 0 dB 1.1 V to 3.9 V
(1) Assumes a 5-V single-ended power supply

6 Pin Configuration and Functions

RGT Package
16-Pin VQFN
Top View
THS4509 po_los454.gif

Pin Functions

PIN TYPE DESCRIPTION
NAME NO.
NC 1 N/A No internal connection
VIN– 2 I Inverting amplifier input
VOUT+ 3 O Noninverting amplifier output
CM 4, 9 I Common-mode voltage input
VS+ 5-8 P Positive amplifier power-supply input
VOUT– 10 O Inverted amplifier output
VIN+ 11 I Noninverting amplifier input
PD 12 I Power-down; PD = logic low puts part into low power mode, PD = logic high or open for normal operation
VS– 13, 14, 15, 16 P Negative amplifier power-supply input

7 Specifications

7.1 Absolute Maximum Ratings

Over operating free-air temperature range, unless otherwise noted.(1)
MIN MAX UNIT
VS– to VS+ Supply voltage 6 V
VI Input voltage ±VS
VID Differential input voltage 4 V
IO Output current(2) 200 mA
Continuous power dissipation See Dissipation Ratings
TJ Maximum junction temperature 150 °C
TA Operating free-air temperature –40 85 °C
Tstg Storage temperature –65 150 °C
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied.
(2) The THS4509 incorporates a (QFN) exposed thermal pad on the underside of the chip. This pad acts as a heatsink and must be connected to a thermally dissipative plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature which could permanently damage the device. See TI technical briefs SLMA002 and SLMA004 for more information about using the QFN thermally-enhanced package.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1500
Machine model ±100
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Supply voltage 3 5 5.25 V
Ambient temperature –40 25 85 °C

7.4 Thermal Information

THERMAL METRIC(1) THS4509 UNIT
RGT (VQFN)
16 PINS
RθJA Junction-to-ambient thermal resistance 49.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 66.9 °C/W
RθJB Junction-to-board thermal resistance 23.7 °C/W
ψJT Junction-to-top characterization parameter 1.7 °C/W
ψJB Junction-to-board characterization parameter 23.7 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 7.1 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Electrical Characteristics: VS+ – VS– = 5 V

Test conditions are at VS+ = +2.5 V, VS– = –2.5 V, G = 10 dB, CM = open, VO = 2 VPP, RF = 349 Ω, RL = 200-Ω differential,
TA = +25°C, single-ended input, differential output, and input and output referenced to midsupply, unless otherwise noted.
PARAMETER TEST CONDITIONS TEST
LEVEL(1) 		MIN TYP MAX UNIT
AC PERFORMANCE
Small-signal bandwidth G = 6 dB, VO = 100 mVPP C 2 GHz
G = 10 dB, VO = 100 mVPP 1.9 GHz
G = 14 dB, VO = 100 mVPP 600 MHz
G = 20 dB, VO = 100 mVPP 275 MHz
Gain-bandwidth product G = 20 dB 3 GHz
Bandwidth for 0.1-dB flatness G = 10 dB, VO = 2 VPP 300 MHz
Large-signal bandwidth G = 10 dB, VO = 2 VPP 1.5 GHz
Slew rate (differential) 2-V step 6600 V/μs
Rise time 0.5 ns
Fall time 0.5
Settling time to 1% 2
Settling time to 0.1% 10
2nd-order harmonic distortion f = 10 MHz –104 dBc
f = 50 MHz –80
f = 100 MHz –68
3rd-order harmonic distortion f = 10 MHz –108 dBc
f = 50 MHz –92
f = 100 MHz –81
2nd-order intermodulation distortion 200-kHz tone spacing,
RL = 499 Ω		 fC = 70 MHz –78 dBc
fC = 140 MHz –64
3rd-order intermodulation distortion fC = 70 MHz –95
fC = 140 MHz –78
2nd-order output intercept point 200-kHz tone spacing
RL = 100 Ω, referenced to 50-Ω output		 fC = 70 MHz 78 dBm
fC = 140 MHz 58
3rd-order output intercept point fC = 70 MHz 43
fC = 140 MHz 38
1-dB compression point fC = 70 MHz 12.2 dBm
fC = 140 MHz 10.8
Noise figure 50-Ω system, 10 MHz 17.1 dB
Input voltage noise f > 10 MHz 1.9 nV/√Hz
Input current noise f > 10 MHz 2.2 pA/√Hz
DC PERFORMANCE
Open-loop voltage gain (AOL) C 68 dB
Input offset voltage TA = +25°C A 1 4 mV
TA = –40°C to +85°C 1 5 mV
Average offset voltage drift TA = –40°C to +85°C B 2.6 μV/°C
Input bias current TA = +25°C A 8 15.5 μA
TA = –40°C to +85°C 8 18.5
Average bias current drift TA = –40°C to +85°C B 20 nA/°C
Input offset current TA = +25°C A 1.6 3.6 μA
TA = –40°C to +85°C 1.6 7
Average offset current drift TA = –40°C to +85°C B 4 nA/°C
INPUT
Common-mode input range high B 1.4 V
Common-mode input range low –1.4
Common-mode rejection ratio 90 dB
Differential input impedance C 1.3 || 1.8 MΩ || pF
Common-mode input impedance C 1.0 || 2.3 MΩ || pF
OUTPUT
Maximum output voltage high Each output with 100 Ω to midsupply TA = +25°C A 1.2 1.4 V
TA = –40°C to +85°C 1.1 1.4
Minimum output voltage low TA = +25°C –1.4 –1.2 V
TA = –40°C to +85°C –1.4 –1.1
Differential output voltage swing 4.8 5.6 V
TA = –40°C to +85°C 4.4
Differential output current drive RL = 10 Ω C 96 mA
Output balance error VO = 100 mV, f = 1 MHz –49 dB
Closed-loop output impedance f = 1 MHz 0.3 Ω
OUTPUT COMMON-MODE VOLTAGE CONTROL
Small-signal bandwidth C 700 MHz
Slew rate 110 V/μs
Gain 1 V/V
Output common-mode offset
from CM input 		1.25 V < CM < 3.5 V 5 mV
CM input bias current 1.25 V < CM < 3.5 V ±40 μA
CM input voltage high 1.5 V
CM input voltage low –1.5
CM input impedance 23 || 1 kΩ || pF
CM default voltage 0 V
POWER SUPPLY
Specified operating voltage C 3 5 5.25 V
Maximum quiescent current TA = +25°C A 37.7 40.9 mA
TA = –40°C to +85°C 37.7 41.9
Minimum quiescent current TA = +25°C 34.5 37.7 mA
TA = –40°C to +85°C 33.5 37.7
Power-supply rejection (±PSRR) C 90 dB
POWER-DOWN - Referenced to VS–
Enable voltage threshold Assured on above 2.1 V + VS– C > 2.1 + VS– V
Disable voltage threshold Assured off below 0.7 V + VS– < 0.7 + VS– V
Power-down quiescent current TA = +25°C A 0.65 0.9 mA
TA = –40°C to +85°C 0.65 1
Input bias current PD = VS– C 100 μA
Input impedance 50 || 2 kΩ || pF
Turnon time delay Measured to output on 55 ns
Turnoff time delay Measured to output off 10 μs
(1) Test levels: (A) 100% tested at +25°C. Over-temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information.

7.6 Electrical Characteristics: VS+ – VS– = 3 V

Test conditions at VS+ = +1.5 V, VS– = –1.5 V, G = 10 dB, CM = open, VO = 1 VPP, RF = 349 Ω, RL = 200-Ω differential,
TA = +25°C, single-ended input, differential output, and input and output referenced to midsupply, unless otherwise noted.
PARAMETER TEST CONDITIONS TEST
LEVEL(1) 		MIN TYP MAX UNIT
AC PERFORMANCE
Small-signal bandwidth G = 6 dB, VO = 100 mVPP C 1.9 GHz
G = 10 dB, VO = 100 mVPP 1.6 GHz
G = 14 dB, VO = 100 mVPP 625 MHz
G = 20 dB, VO = 100 mVPP 260 MHz
Gain-bandwidth product G = 20 dB 3 GHz
Bandwidth for 0.1-dB flatness G = 10 dB, VO = 1 VPP 400 MHz
Large-signal bandwidth G = 10 dB, VO = 1 VPP 1.5 GHz
Slew rate (differential) 2-V step 3500 V/μs
Rise time 0.25 ns
Fall time 0.25
Settling time to 1% 1
Settling time to 0.1% 10
2nd-order harmonic distortion f = 10 MHz –107 dBc
f = 50 MHz –83
f = 100 MHz –60
3rd-order harmonic distortion f = 10 MHz –87 dBc
f = 50 MHz –65
f = 100 MHz –54
2nd-order intermodulation distortion 200-kHz tone spacing,
RL = 499 Ω		 fC = 70 MHz –77 dBc
fC = 140 MHz –54
3rd-order intermodulation distortion fC = 70 MHz –77
fC = 140 MHz –62
2nd-order output intercept point 200-kHz tone spacing
RL = 100 Ω		 fC = 70 MHz 72 dBm
fC = 140 MHz 52
3rd-order output intercept point fC = 70 MHz 38.5
fC = 140 MHz 30
1-dB compression point fC = 70 MHz 2.2 dBm
fC = 140 MHz 0.25
Noise figure 50 Ω system, 10 MHz 17.1 dB
Input voltage noise f > 10 MHz 1.9 nV/√Hz
Input current noise f > 10 MHz 2.2 pA/√Hz
DC PERFORMANCE
Open-loop voltage gain (AOL) C 68 dB
Input offset voltage TA = +25°C 1 mV
Average offset voltage drift TA = –40°C to +85°C 2.6 μV/°C
Input bias current TA = +25°C 6 μA
Average bias current drift TA = –40°C to +85°C 20 nA/°C
Input offset current TA = +25°C 1.6 μA
Average offset current drift TA = –40°C to +85°C 4 nA/°C
INPUT
Common-mode input range high B 0.4 V
Common-mode input range low –0.4
Common-mode rejection ratio 80 dB
Differential input impedance C 1.3 || 1.8 MΩ || pF
Common-mode input impedance C 1.0 || 2.3 MΩ || pF
OUTPUT
Maximum output voltage high Each output with 100 Ω to midsupply TA = +25°C C 0.45 V
Minimum output voltage low TA = +25°C –0.45 V
Differential output voltage swing 1.8 V
Differential output current drive RL = 10 Ω 50 mA
Output balance error VO = 100 mV, f = 1 MHz –49 dB
Closed-loop output impedance f = 1 MHz 0.3 Ω
OUTPUT COMMON-MODE VOLTAGE CONTROL
Small-signal bandwidth C 570 MHz
Slew rate 60 V/μs
Gain 1 V/V
Output common-mode offset
from CM input 		1.25 V < CM < 3.5 V 4 mV
CM input bias current 1.25 V < CM < 3.5 V ±40 μA
CM input voltage high 1.5 V
CM input voltage low –1.5
CM input impedance 20 || 1 kΩ || pF
CM default voltage 0 V
POWER SUPPLY
Specified operating voltage C 3 V
Quiescent current TA = +25°C A 34.8 mA
Power-supply rejection (±PSRR) C 70 dB
POWER-DOWN Referenced to VS–
Enable voltage threshold Assured on above 2.1 V + VS– C > 2.1 + VS– V
Disable voltage threshold Assured off below 0.7 V + VS– < 0.7 + VS- V
Power-down quiescent current 0.46 mA
Input bias current PD = VS– 65 μA
Input impedance 50 || 2 kΩ || pF
Turnon time delay Measured to output on 100 ns
Turnoff time delay Measured to output off 10 μs
(1) Test levels: (A) 100% tested at +25°C. Over-temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information.

7.7 Dissipation Ratings

PACKAGE θJC θJA POWER RATING
TA ≤ +25°C TA = +85°C
RGT (16) 2.4°C/W 39.5°C/W 2.3 W 225 mW

7.8 Typical Characteristics

7.8.1 Typical Characteristics: VS+ – VS– = 5 V

Test conditions at VS+ = +2.5 V, VS– = –2.5V, CM = open, VO = 2 VPP, RF = 349 Ω, RL = 200-Ω differential, G = 10 dB, single-ended input, and input and output referenced to midrail, unless otherwise noted.

Table 1. Table of Graphs

FIGURE
Small-Signal Frequency Response Figure 1
Large-Signal Frequency Response Figure 2
Harmonic
Distortion		 HD2, G = 6 dB, VOD = 2 VPP vs Frequency Figure 3
HD3, G = 6 dB, VOD = 2 VPP vs Frequency Figure 4
HD2, G = 10 dB, VOD = 2 VPP vs Frequency Figure 5
HD3, G = 10 dB, VOD = 2 VPP vs Frequency Figure 6
HD2, G = 14 dB, VOD = 2 VPP vs Frequency Figure 7
HD3, G = 14 dB, VOD = 2 VPP vs Frequency Figure 8
HD2, G = 10 dB vs Output Voltage Figure 9
HD3, G = 10 dB vs Output Voltage Figure 10
HD2, G = 10 dB vs Common-Mode Input Voltage Figure 11
HD3, G = 10 dB vs Common-Mode Input Voltage Figure 12
Intermodulation
Distortion		 IMD2, G = 6 dB, VOD = 2 VPP vs Frequency Figure 13
IMD3, G = 6 dB, VOD = 2 VPP vs Frequency Figure 14
IMD2, G = 10 dB, VOD = 2 VPP vs Frequency Figure 15
IMD3, G = 10 dB, VOD = 2 VPP vs Frequency Figure 16
IMD2, G = 14 dB, VOD = 2 VPP vs Frequency Figure 17
IMD3, G = 14 dB, VOD = 2 VPP vs Frequency Figure 18
Output Intercept Point OIP2 vs Frequency Figure 19
OIP3 vs Frequency Figure 20
0.1-dB Flatness Figure 21
S-Parameters vs Frequency Figure 22
Transition Rate vs Output Voltage Figure 23
Transient Response Figure 24
Settling Time Figure 25
Rejection Ratio vs Frequency Figure 26
Output Impedance vs Frequency Figure 27
Overdrive Recovery Figure 28
Output Voltage Swing vs Load Resistance Figure 29
Turnoff Time Figure 30
Turnon Time Figure 31
Input Offset Voltage vs Input Common-Mode Voltage Figure 32
Open-Loop Gain vs Frequency Figure 33
Input-Referred Noise vs Frequency Figure 34
Noise Figure vs Frequency Figure 35
Quiescent Current vs Supply Voltage Figure 36
Power-Supply Current vs Supply Voltage in Power-Down Mode Figure 37
Output Balance Error vs Frequency Figure 38
CM Input Impedance vs Frequency Figure 39
CM Small-Signal Frequency Response Figure 40
CM Input Bias Current vs CM Input Voltage Figure 41
Differential Output Offset Voltage vs CM Input Voltage Figure 42
Output Common-Mode Offset vs CM Input Voltage Figure 43
THS4509 ss_fr_los454.gif Figure 1. Small-Signal Frequency Response
THS4509 sec2_hd_f_los454.gif Figure 3. HD2 vs Frequency
THS4509 sec4_hd_f_los454.gif Figure 5. HD2 vs Frequency
THS4509 sec6_hd_f_los454.gif Figure 7. HD2 vs Frequency
THS4509 hd2_vout_los454.gif Figure 9. HD2 vs Output Voltage
THS4509 hd2_v_cm_los454.gif Figure 11. HD2 vs Common-Mode Output Voltage
THS4509 tc_imd_2_f_los454.gif Figure 13. IMD2 vs Frequency
THS4509 imd_4_f_los454.gif Figure 15. IMD2 vs Frequency
THS4509 imd_6_f_los454.gif Figure 17. IMD2 vs Frequency
THS4509 oip3_2_f_los454.gif Figure 19. OIP2 vs Frequency
THS4509 flatness_los454.gif Figure 21. 0.1-dB Flatness
THS4509 tc_slew_vo_los454.gif Figure 23. Transition Rate vs Output Voltage
THS4509 sett_t_los454.gif Figure 25. Settling Time
THS4509 zo_f_los454.gif Figure 27. Output Impedance vs Frequency
THS4509 vos_lr_los454.gif Figure 29. Output Voltage Swing vs Load Resistance
THS4509 ton_t_los454.gif Figure 31. Turnon Time
THS4509 aol_f_los454.gif Figure 33. Open-Loop Gain and Phase vs Frequency
THS4509 nf2_f_los454.gif Figure 35. Noise Figure vs Frequency
THS4509 psc_vs_los454.gif Figure 37. Power-Supply Current vs Supply Voltage in Power-Down Mode
THS4509 cm_zo_f_los454.gif Figure 39. CM Input Impedance vs Frequency
THS4509 iib_vi_los454.gif Figure 41. CM Input Bias Current vs CM Input Voltage
THS4509 ocm2_cm_los454.gif Figure 43. Output Common-Mode Offset vs CM Input Voltage
THS4509 ls_fr_los454.gif Figure 2. Large-Signal Frequency Response
THS4509 thrd2_hd_f_los454.gif Figure 4. HD3 vs Frequency
THS4509 thrd4_hd_f_los454.gif Figure 6. HD3 vs Frequency
THS4509 thrd6_hd_f_los454.gif Figure 8. HD3 vs Frequency
THS4509 hd3_vout_los454.gif Figure 10. HD3 vs Output Voltage
THS4509 hd3_v_cm_los454.gif Figure 12. HD3 vs Common-Mode Output Voltage
THS4509 imd3_2_f_los454.gif Figure 14. IMD3 vs Frequency
THS4509 imd3_4_f_los454.gif Figure 16. IMD3 vs Frequency
THS4509 imd3_6_f_los454.gif Figure 18. IMD3 vs Frequency
THS4509 oip3_3_f_los454.gif Figure 20. OIP3 vs Frequency
THS4509 spar_f_los454.gif Figure 22. S-Parameters vs Frequency
THS4509 trns_res_los454.gif Figure 24. Transient Response
THS4509 rejr_f_los454.gif Figure 26. Rejection Ratio vs Frequency
THS4509 od_rec_los454.gif Figure 28. Overdrive Recovery
THS4509 toff_t_los454.gif Figure 30. Turnoff Time
THS4509 vio_vicr_los454.gif Figure 32. Input Offset Voltage vs Input Common-Mode Voltage
THS4509 irn_f_los454.gif Figure 34. Input-Referred Noise vs Frequency
THS4509 iq_vs_los454.gif Figure 36. Quiescent Current vs Supply Voltage
THS4509 obe_f_los454.gif Figure 38. Output Balance Error vs Frequency
THS4509 sm_sig_res_los454.gif Figure 40. CM Small-Signal Frequency Response
THS4509 dif_osv_v_los454.gif Figure 42. Differential Output Offset Voltage vs CM Input Voltage

7.8.2 Typical Characteristics: VS+ – VS– = 3 V

Test conditions at VS+ = +1.5 V, VS– = –1.5 V, CM = open, VOD = 1 VPP, RF = 349 Ω, RL = 200-Ω differential, G = 10 dB, single-ended input, and input and output referenced to midrail, unless otherwise noted.

Table 2. Table of Graphs

FIGURE
Small-Signal Frequency Response Figure 44
Large-Signal Frequency Response Figure 45
Harmonic
Distortion		 HD2, G = 6 dB, VOD = 1 VPP vs Frequency Figure 46
HD3, G = 6 dB, VOD = 1 VPP vs Frequency Figure 47
HD2, G = 10 dB, VOD = 1 VPP vs Frequency Figure 48
HD3, G = 10 dB, VOD = 1 VPP vs Frequency Figure 49
HD2, G = 14 dB, VOD = 1 VPP vs Frequency Figure 50
HD3, G = 14 dB, VOD = 1 VPP vs Frequency Figure 51
Intermodulation
Distortion		 IMD2, G = 6 dB, VOD = 1 VPP vs Frequency Figure 52
IMD3, G = 6 dB, VOD = 1 VPP vs Frequency Figure 53
IMD2, G = 10 dB, VOD = 1 VPP vs Frequency Figure 54
IMD3, G = 10 dB, VOD = 1 VPP vs Frequency Figure 55
IMD2, G = 14 dB, VOD = 1 VPP vs Frequency Figure 56
IMD3, G = 14 dB, VOD = 1 VPP vs Frequency Figure 57
Output Intercept Point OIP2 vs Frequency Figure 58
OIP3 vs Frequency Figure 59
0.1 dB Flatness Figure 60
S-Parameters vs Frequency Figure 61
Transition Rate vs Output Voltage Figure 62
Transient Response Figure 63
Settling Time Figure 64
Output Voltage Swing vs Load Resistance Figure 65
Rejection Ratio vs Frequency Figure 66
Overdrive Recovery Figure 67
Output Impedance vs Frequency Figure 68
Turnoff Time Figure 69
Turnon Time Figure 70
Output Balance Error vs Frequency Figure 71
Noise Figure vs Frequency Figure 72
CM Input Impedance vs Frequency Figure 73
Differential Output Offset Voltage vs CM Input Voltage Figure 74
Output Common-Mode Offset vs CM Input Voltage Figure 75
THS4509 ss2_fr_los454.gif Figure 44. Small-Signal Frequency Response
THS4509 sec7_hd_f_los454.gif Figure 46. HD2 vs Frequency
THS4509 sec8_hd_f_los454.gif Figure 48. HD2 vs Frequency
THS4509 sec9_hd_f_los454.gif Figure 50. HD2 vs Frequency
THS4509 imd2_f_los454.gif Figure 52. IMD2 vs Frequency
THS4509 imd22_f_los454.gif Figure 54. IMD2 vs Frequency
THS4509 imd23_f_los454.gif Figure 56. IMD2 vs Frequency
THS4509 oip3_f_los454.gif Figure 58. OIP2, dBm vs Frequency
THS4509 flatness2_los454.gif Figure 60. 0.1-dB Flatness
THS4509 slew2_vo_los454.gif Figure 62. Transition Rate vs Output Voltage
THS4509 sett2_t_los454.gif Figure 64. Settling Time
THS4509 rejr2_f_los454.gif Figure 66. Rejection Ratio vs Frequency
THS4509 zo2_f_los454.gif Figure 68. Output Impedance vs Frequency
THS4509 ton2_t_los454.gif Figure 70. Turnon Time
THS4509 nf_f_los454.gif Figure 72. Noise Figure vs Frequency
THS4509 dif2_osv_v_los454.gif Figure 74. Differential Output Offset Voltage vs CM Input Voltage
THS4509 is2_fr_los454.gif Figure 45. Large-Signal Frequency Response
THS4509 thrd7_hd_f_los454.gif Figure 47. HD3 vs Frequency
THS4509 thrd8_hd_f_los454.gif Figure 49. HD3 vs Frequency
THS4509 thrd9_hd_f_los454.gif Figure 51. HD3 vs Frequency
THS4509 imd3_f_los454.gif Figure 53. IMD3 vs Frequency
THS4509 imd32_f_los454.gif Figure 55. IMD3 vs Frequency
THS4509 imd33_f_los454.gif Figure 57. IMD3 vs Frequency
THS4509 oip32_f_los454.gif Figure 59. OIP3, dBm vs Frequency
THS4509 spar2_f_los454.gif Figure 61. S-Parameters vs Frequency
THS4509 trns2_res_los454.gif Figure 63. Transient Response
THS4509 vos2_lr_los454.gif Figure 65. Output Voltage Swing vs Load Resistance
THS4509 od2_rec_los454.gif Figure 67. Overdrive Recovery
THS4509 toff2_t_los454.gif Figure 69. Turnoff Time
THS4509 obe2_f_los454.gif Figure 71. Output Balance Error vs Frequency
THS4509 cm2_zo_f_los454.gif Figure 73. CM Input Impedance vs Frequency
THS4509 ocm_cm_los454.gif Figure 75. Output Common-Mode Offset vs CM Input Voltage

8 Detailed Description

8.1 Overview

The THS4509 is a fully differential amplifier with integrated common-mode control designed to provide low distortion amplification to wide bandwidth differential signals. The common-mode feedback circuit sets the output common-mode voltage independent of the input common mode, as well as forcing the V+ and V − outputs to be equal in magnitude and opposite in phase, even when only one of the inputs is driven as in single to differential conversion.

8.2 Functional Block Diagram

THS4509 fbd_THS4509.gif

8.3 Feature Description

8.3.1 Test Circuits

The THS4509 is tested with the following test circuits built on the evaluation module (EVM). For simplicity, power-supply decoupling is not shown—see Layout for recommendations. Depending on the test conditions, component values are changed per Table 3 and Table 4, or as otherwise noted. The signal generators used are AC-coupled, 50-Ω sources, and a 0.22-μF capacitor and 49.9-Ω resistor to ground are inserted across RIT on the alternate input to balance the circuit. A split power supply is used to ease the interface to common test equipment, but the amplifier can be operated single-supply as described in Typical Applications with no impact on performance.

Table 3. Gain Component Values

GAIN RF RG RIT
6 dB 348 Ω 165 Ω 61.9 Ω
10 dB 348 Ω 100 Ω 69.8 Ω
14 dB 348 Ω 56.2 Ω 88.7 Ω
20 dB 348 Ω 16.5 Ω 287 Ω

Note the gain setting includes 50-Ω source impedance. Components are chosen to achieve gain and 50-Ω input termination.

Table 4. Load Component Values

RL RO ROT ATTEN.
100 Ω 25 Ω Open 6 dB
200 Ω 86.6 Ω 69.8 Ω 16.8 dB
499 Ω 237 Ω 56.2 Ω 25.5 dB
1k Ω 487 Ω 52.3 Ω 31.8 dB

Note the total load includes 50-Ω termination by the test equipment. Components are chosen to achieve load and 50-Ω line termination through a 1:1 transformer.

Due to the voltage divider on the output formed by the load component values, the amplifier output is attenuated. The column Atten in Table 4 shows the attenuation expected from the resistor divider. When using a transformer at the output as shown in Figure 77, the signal sees slightly more loss, and these numbers are approximate.

8.3.1.1 Frequency Response

The circuit shown in Figure 76 is used to measure the frequency response of the circuit.

THS4509 fr_tc_los454.gif Figure 76. Frequency Response Test Circuit

A network analyzer is used as the signal source and as the measurement device. The output impedance of the network analyzer is 50 Ω. RIT and RG are chosen to impedance match to 50 Ω, and to maintain the proper gain. To balance the amplifier, a 0.22-μF capacitor and 49.9-Ω resistor to ground are inserted across RIT on the alternate input.

The output is probed using a high-impedance differential probe across the 100-Ω resistor. The gain is referred to the amplifier output by adding back the 6-dB loss due to the voltage divider on the output.

8.3.1.2 Distortion and 1-dB Compression

The circuit shown in Figure 77 is used to measure harmonic distortion, intermodulation distortion, and 1-db compression point of the amplifier.

THS4509 dis_tc_los454.gif Figure 77. Distortion Test Circuit

A signal generator is used as the signal source and the output is measured with a spectrum analyzer. The output impedance of the signal generator is 50 Ω. RIT and RG are chosen to impedance-match to 50 Ω, and to maintain the proper gain. To balance the amplifier, a 0.22-μF capacitor and 49.9-Ω resistor to ground are inserted across RIT on the alternate input.

A low-pass filter is inserted in series with the input to reduce harmonics generated at the signal source. The level of the fundamental is measured, then a high-pass filter is inserted at the output to reduce the fundamental so that it does not generate distortion in the input of the spectrum analyzer.

The transformer used in the output to convert the signal from differential to single-ended is an ADT1-1WT. It limits the frequency response of the circuit so that measurements cannot be made below approximately 1 MHz.

The 1-dB compression point is measured with a spectrum analyzer with 50-Ω double termination or 100-Ω termination; see Table 4. The input power is increased until the output is 1 dB lower than expected. The number reported in the table data is the power delivered to the spectrum analyzer input. Add 3 dB to refer to the amplifier output.

8.3.1.3 S-Parameter, Slew Rate, Transient Response, Settling Time, Output Impedance, Overdrive, Output Voltage, Turnon, and Turnoff Time

The circuit shown in Figure 78 is used to measure s-parameters, slew rate, transient response, settling time, output impedance, overdrive recovery, output voltage swing, turnon, and turnoff times of the amplifier. For output impedance, the signal is injected at VOUT with VIN left open and the drop across the 49.9-Ω resistor is used to calculate the impedance seen looking into the amplifier output.

Because S21 is measured single-ended at the load with 50-Ω double termination, add 12 dB to refer to the amplifier output as a differential signal.

THS4509 s_par_los454.gif Figure 78. S-Parameter, SR, Transient Response, Settling Time, ZO, Overdrive Recovery, VOUT Swing, Turnon, and Turnoff Test Circuit

8.3.1.4 CM Input

The circuit shown in Figure 79 is used to measure the frequency response and input impedance of the CM input. Frequency response is measured single-ended at VOUT+ or VOUT– with the input injected at VIN, RCM = 0 Ω, and RCMT = 49.9 Ω. The input impedance is measured with RCM = 49.9 Ω with RCMT = open, and calculated by measuring the voltage drop across RCM to determine the input current.

THS4509 tc_cmin_los454.gif Figure 79. CM Input Test Circuit

8.3.1.5 CMRR and PSRR

The circuit shown in Figure 80 is used to measure the CMRR and PSRR of VS+ and VS–. The input is switched appropriately to match the test being performed.

THS4509 cmrr_psrr_los454.gif Figure 80. CMRR and PSRR Test Circuit

8.4 Device Functional Modes

The THS4509 has one main functional mode with two variants. The amplifier functions as either a differential to differential or a single-ended to differential amplifier. In either of these modes the amplifier output operating point (common-mode voltage) is set independently by the CM pin.

The THS4509 also features a power-down state for reduced power consumption when the amplifier is not required to be operational.

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

The THS4509 is a fully-configurable, differential operational amplifier. The closed-loop gain is set by external resistors. Many performance metrics are set by the matching of these external resistors, so 0.1% or better tolerance resistors are recommended.

The amplifier output common-mode voltage is set by the CM pin. From the CM pin to the amplifier outputs there is a fixed gain of 1 V/V so that the amplifier output voltage is identical to the voltage applied to the CM pin. This pin must be driven by a low impedance reference and must also be bypassed to ground using a 0.1-µF ceramic, low ESR resistor. The ideal common-mode voltage is equal to the voltage that is midway between the positive and negative supply voltages.

The THS4509 can be operated from either single or split power supplies with a range of 3 V to 5 V of total supply voltage. When selecting a power supply voltage, make sure to provide adequate margin for input and output voltage levels. In many cases, split supplies are the best option. It is not necessary to have power supply voltages symmetrical around ground. For example, –1 V and +4 V is a valid power supply configuration.

9.2 Typical Applications

The following circuits show application information for the THS4509. For simplicity, power-supply decoupling capacitors are not shown in these diagrams. See the Layout section for recommendations. For more detail on the use and operation of fully-differential op amps refer to the application report, Fully-Differential Amplifiers (SLOA054).

9.2.1 Differential Input to Differential Output Amplifier

The THS4509 is a fully-differential op amp, and can be used to amplify differential input signals to differential output signals. A basic block diagram of the circuit is shown in Figure 81 (CM input not shown). The gain of the circuit is set by RF divided by RG.

Depending on the source and load, input and output termination can be accomplished by adding RIT and RO.

THS4509 dif_dif_amp_los454.gif Figure 81. Differential Input to Differential-Output Amplifier

9.2.1.1 Design Requirements

The following sections detail how to determine if your design meets these requirements.

The main design requirements for the THS4509 are the input common mode, the output swing voltage. Other design requirements are signal linearity and accuracy. With flexible supply voltage ranges and externally configurable resistors the THS4509 can be configured to meet many design requirements.

Table 5 lists the design parameters of this example.

Table 5. Design Parameters

PARAMETER EXAMPLE VALUE
Gain 6 dB
Output swing 2 Vpp
Harmonic distortion >75 dBc
Load resistance 100 Ω

9.2.1.2 Detailed Design Procedure

The first parameter is gain. Gain is set by external resistors as shown in Table 3. With a gain of 6 dB, the appropriate resistor values are 348 Ω for RF and 165 Ω for RG and 61.9 Ω for the termination resistor. These resistor values are for a 50-Ω source. The desired output swing of 2 Vpp and distortion of –75 dBc means that a supply voltage of 5 V is required. Further design details are covered in this section.

9.2.1.2.1 Input Common-Mode Voltage Range

The input common-mode voltage of a fully-differential op amp is the voltage at the + and – input pins of the op amp.

It is important to not violate the input common-mode voltage range (VICR) of the op amp. Assuming the op amp is in linear operation the voltage across the input pins is only a few millivolts at most. So finding the voltage at one input pin determines the input common-mode voltage of the op amp.

Treating the negative input as a summing node, the voltage is given by Equation 1:

Equation 1. THS4509 eq1_los454.gif

To determine the VICR of the op amp, the voltage at the negative input is evaluated at the extremes of VOUT+.

As the gain of the op amp increases, the input common-mode voltage becomes closer and closer to the input common-mode voltage of the source.

9.2.1.2.2 Setting the Output Common-Mode Voltage

The output common-mode voltage is set by the voltage at the CM pin(s). The internal common-mode control circuit maintains the output common-mode voltage within 3-mV offset (typical) from the set voltage, when set within 0.5 V of midsupply, with less than 4-mV differential offset voltage. If left unconnected, the common-mode set point is set to midsupply by internal circuitry, which may be overdriven from an external source. Figure 82 is representative of the CM input. The internal CM circuit has about 700 MHz of –3-dB bandwidth, which is required for best performance, but it is intended to be a DC bias input pin. Bypass capacitors are recommended on this pin to reduce noise at the output. The external current required to overdrive the internal resistor divider is given by Equation 2:

Equation 2. THS4509 eq2_los454.gif

where

  • VCM is the voltage applied to the CM pin
THS4509 cm_in_los454.gif Figure 82. CM Input Circuit

9.2.1.2.3 Single-Supply Operation (3 V to 5 V)

To facilitate testing with common lab equipment, the THS4509 EVM allows split-supply operation, and the characterization data presented in this data sheet were taken with split-supply power inputs. The device can easily be used with a single-supply power input without degrading the performance. Figure 83, Figure 84, and Figure 85 show DC and AC-coupled single-supply circuits with single-ended inputs. These configurations all allow the input and output common-mode voltage to be set to midsupply allowing for optimum performance. The information presented here can also be applied to differential input sources.

In Figure 83, the source is referenced to the same voltage as the CM pin (VCM). VCM is set by the internal circuit to midsupply. RT along with the input impedance of the amplifier circuit provides input termination, which is also referenced to VCM.

NOTE

RS and RT are added to the alternate input from the signal input to balance the amplifier. Alternately, one resistor can be used equal to the combined value RG+ RS || RT on this input. This is also true of the circuits shown in Figure 84 and Figure 85.
THS4509 ss_dc-cpl_los454.gif Figure 83. THS4509 DC-Coupled Single-Supply With Input Biased to VCM

In Figure 84 the source is referenced to ground and so is the input termination resistor. RPU is added to the circuit to avoid violating the VICR of the op amp. The proper value of resistor to add can be calculated from Equation 3:

Equation 3. THS4509 eq3_los454.gif
THS4509 ss1_dc-cpl_los454.gif Figure 84. THS4509 DC-Coupled Single-Supply With RPU Used to Set VIC

VIC is the desired input common-mode voltage, VCM = CM, and RIN = RG+ RS || RT. To set to midsupply, make the value of RPU = RG+ RS || RT.

Table 6 is a modification of Table 3 to add the proper values with RPU assuming a 50-Ω source impedance and setting the input and output common-mode voltage to midsupply.

Table 6. RPU Values for Various Gains

GAIN RF RG RIT RPU
6 dB 348 Ω 169 Ω 64.9 Ω 200 Ω
10 dB 348 Ω 102 Ω 78.7 Ω 133 Ω
14 dB 348 Ω 61.9 Ω 115 Ω 97.6 Ω
20 dB 348 Ω 40.2 Ω 221 Ω 80.6 Ω

There are two drawbacks to this configuration. One is that it requires additional current from the power supply. Using the values shown for a gain of 10 dB requires 37 mA more current with 5-V supply, and 22-mA more current with 3-V supply.

The other drawback is that this configuration also increases the noise gain of the circuit. In the 10-dB gain case, noise gain increases by a factor of 1.5.

Figure 85 shows AC coupling to the source. Using capacitors in series with the termination resistors allows the amplifier to self-bias both input and output to midsupply.

THS4509 ss_ac-cpl_los454.gif Figure 85. THS4509 AC-Coupled Single-Supply

9.2.1.2.4 THS4509 and ADS5500 Combined Performance

The THS4509 is designed to be a high-performance drive amplifier for high-performance data converters like the ADS5500 14-bit 125-MSPS ADC. Figure 86 shows a circuit combining the two devices, and Figure 87 shows the combined SNR and SFDR performance versus frequency with –1-dBFS input signal level sampling at 125 MSPS. The THS4509 amplifier circuit provides 10 dB of gain, converts the single-ended input to differential, and sets the proper input common-mode voltage to the ADS5500. The 100-Ω resistors and 2.7-pF capacitor between the THS4509 outputs and ADS5500 inputs along with the input capacitance of the ADS5500 limit the bandwidth of the signal to 115 MHz (–3 dB). For testing, a signal generator is used for the signal source. The generator is an ac-coupled 50-Ω source. A band-pass filter is inserted in series with the input to reduce harmonics and noise from the signal source. Input termination is accomplished through the 69.8-Ω resistor and 0.22-μF capacitor to ground in conjunction with the input impedance of the amplifier circuit. A 0.22-μF capacitor and 49.9-Ω resistor is inserted to ground across the 69.8-Ω resistor and 0.22-μF capacitor on the alternate input to balance the circuit. Gain is a function of the source impedance, termination, and 348-Ω feedback resistor. Refer to Table 6 for component values to set proper 50-Ω termination for other common gains. A split power supply of +4 V and –1 V is used to set the input and output common-mode voltages to approximately midsupply while setting the input common-mode of the ADS5500 to the recommended +1.55 V. This configuration maintains maximum headroom on the internal transistors of the THS4509 to insure optimum performance.

THS4509 ad_los454.gif Figure 86. THS4509 and ADS5500 Circuit
THS4509 ad_gr_los454.gif Figure 87. THS4509 and ADS5500 SFDR and SNR Performance vs Frequency

Figure 88 shows the two-tone FFT of the THS4509 and ADS5500 circuit with 65-MHz and 70-MHz input frequencies. The SFDR is 90 dBc.

THS4509 ad_fft_los454.gif Figure 88. THS4509 and ADS5500 2-Tone FFT With 65-MHz and 70-MHz Inputs

9.2.1.2.5 THS4509 and ADS5424 Combined Performance

Figure 89 shows the THS4509 driving the ADS5424 ADC, and Figure 90 shows the combined SNR and SFDR performance versus frequency with –1-dBFS input signal level and sampling at 80 MSPS.

As before, the THS4509 amplifier provides 10 dB of gain, converts the single-ended input to differential, and sets the proper input common-mode voltage to the ADS5424. Input termination and circuit testing is the same as described above for the THS4509 and ADS5500 circuit.

The 225-Ω resistors and 2.7-pF capacitor between the THS4509 outputs and ADS5424 inputs (along with the input capacitance of the ADC) limit the bandwidth of the signal to about 100MHz (–3 dB).

Because the ADS5424 recommended input common-mode voltage is 2.4 V, the THS4509 is operated from a single power-supply input with VS+ = 5 V and VS– = 0 V (ground).

THS4509 ad2_los454.gif Figure 89. THS4509 and ADS5424 Circuit

9.2.1.3 Application Curve

THS4509 ad2_gr_los454.gif Figure 90. THS4509 and ADS5424 SFDR and SNR Performance vs Frequency

9.2.2 Single-Ended Input to Differential Output Amplifier

The THS4509 can be used to amplify and convert single-ended input signals to differential output signals. A basic block diagram of the circuit is shown in Figure 91 (CM input not shown). The gain of the circuit is again set by RF divided by RG.

THS4509 se_dif_amp_los454.gif Figure 91. Single-Ended Input to Differential Output Amplifier

10 Power Supply Recommendations

The THS4509 can accommodate supply voltages from 3 V to 5 V, either single supply or split supply. Unless the application calls for AC coupling and a very small signal the 5-V supply option must be chosen. In many cases, split supplies are necessary because it is important to have the output common-mode voltage set very close to the midsupply voltage. For example, when driving an ADC with an input common-mode voltage of 1 V the ideal power supply voltage would be +3.5 V and –1.5 V.

Power supply decoupling capacitors must be placed within 2 mm of the amplifier power supply pins. These capacitors must be very low ESR and must have a self resonant frequency above 200 mHz.

 
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