SLAZ741A march   2023  – april 2023 MSPM0L1105 , MSPM0L1106 , MSPM0L1303 , MSPM0L1304 , MSPM0L1305 , MSPM0L1306 , MSPM0L1343 , MSPM0L1344 , MSPM0L1345 , MSPM0L1346

 

  1.   Abstract
  2. 1Functional Advisories
  3. 2Preprogrammed Software Advisories
  4. 3Debug Only Advisories
  5. 4Fixed by Compiler Advisories
  6. 5Device Nomenclature
    1. 5.1 Device Symbolization and Revision Identification
  7. 6Advisory Descriptions
    1. 6.1  ADC_ERR_01
    2. 6.2  ADC_ERR_02
    3. 6.3  COMP_ERR_01
    4. 6.4  GPIO_ERR_01
    5. 6.5  I2C_ERR_01
    6. 6.6  IO_ERR_01
    7. 6.7  PMCU_ERR_01
    8. 6.8  PMCU_ERR_02
    9. 6.9  PMCU_ERR_03
    10. 6.10 PWREN_ERR_01
    11. 6.11 SPI_ERR_01
    12. 6.12 SYSOSC_ERR_01
  8. 7Revision History

6.12 SYSOSC_ERR_01

MFCLK drift when using SYSOSC FCL together with STOP1 mode

Revisions Affected

Rev C

Details

When MFCLK is enabled AND SYSOSC is using the frequency correction loop (FCL) mode AND the STOP1 low power operating mode is used, THEN the MFCLK may drift by 2 cycles when SYSOSC shifts from 4MHz back to 32MHz (either upon exit from STOP1 to RUN mode or upon an asynchronous fast clock request that forces SYSOSC to 32MHz).

Workaround1

Use STOP0 mode instead of STOP1 mode. There is no MFCLK drift when STOP0 mode is used.

Workaround2

Do not use SYSOSC in the FCL mode (leave FCL disabled) when using STOP1.