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  • DAC38RF8x Dual-Channel, Differential-Output, 14-Bit, 9-GSPS, RF-Sampling DAC With JESD204B Interface, On-Chip PLL and Wide-Band Interpolation

    • SLASEA6D February   2017  – June 2020

      PRODUCTION DATA.  

  • CONTENTS
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  • DAC38RF8x Dual-Channel, Differential-Output, 14-Bit, 9-GSPS, RF-Sampling DAC With JESD204B Interface, On-Chip PLL and Wide-Band Interpolation
  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     32x6 MHz 256-QAM Carriers
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics - DC Specifications
    6. 7.6  Electrical Characteristics - Digital Specifications
    7. 7.7  Electrical Characteristics - AC Specifications
    8. 7.8  PLL/VCO Electrical Characteristics
    9. 7.9  Timing Requirements
    10. 7.10 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1  SerDes Inputs
      2. 8.3.2  SerDes Rate
      3. 8.3.3  SerDes PLL
      4. 8.3.4  SerDes Equalizer
      5. 8.3.5  JESD204B Descrambler
      6. 8.3.6  JESD204B Frame Assembly
      7. 8.3.7  SYNC Interface
      8. 8.3.8  Single or Dual Link Configuration
      9. 8.3.9  Multi-Device Synchronization
      10. 8.3.10 SYSREF Capture Circuit
      11. 8.3.11 SerDes Test Modes through Serial Programming
      12. 8.3.12 SerDes Test Modes through IEEE 1500 Programming
      13. 8.3.13 Error Counter
      14. 8.3.14 Eye Scan
      15. 8.3.15 JESD204B Pattern Test
      16. 8.3.16 Wideband DUC (wide-DUC)
      17. 8.3.17 Interpolation Block
        1. 8.3.17.1 Multi-DUC input
        2. 8.3.17.2 Interpolation Filters
        3. 8.3.17.3 JESD204B Modes, Interpolation and Clock phase Programming
        4. 8.3.17.4 Digital Quadrature Modulator
        5. 8.3.17.5 Low Power Coarse Resolution Mixing Modes
        6. 8.3.17.6 Inverse Sinc Filter
      18. 8.3.18 PA Protection Block
      19. 8.3.19 Gain Block
      20. 8.3.20 Output Summation
      21. 8.3.21 Output Delay
      22. 8.3.22 Polarity Inversion
      23. 8.3.23 Temperature Sensor
      24. 8.3.24 Alarm Monitoring
      25. 8.3.25 Differential Clock Inputs
      26. 8.3.26 CMOS Digital Inputs
      27. 8.3.27 DAC Fullscale Output Current
      28. 8.3.28 Current Steering DAC Architecture
      29. 8.3.29 DAC Transfer Function
    4. 8.4 Device Functional Modes
      1. 8.4.1 Clocking Modes
      2. 8.4.2 PLL Bypass Mode Programming
      3. 8.4.3 Internal PLL/VCO
      4. 8.4.4 CLKOUT
      5. 8.4.5 Serial Peripheral Interface (SPI)
        1. 8.4.5.1 NORMAL (RW)
        2. 8.4.5.2 WRITE_TO_CLEAR (W0C)
        3. 8.4.5.3 Writing to Reserved Bits
    5. 8.5 Register Maps
      1. 8.5.1  Chip Reset and Configuration Register (address = 0x00) [reset = 0x5803]
        1. Table 48. RESET_CONFIG Field Descriptions
      2. 8.5.2  IO Configuration Register (address = 0x01) [reset = 0x1800]
        1. Table 49. IO_CONFIG Field Descriptions
      3. 8.5.3  Lane Single Detect Alarm Mask Register (address = 0x02) [reset = 0xFFFF]
        1. Table 50. ALM_SD_MASK Field Descriptions
      4. 8.5.4  Clock Alarms Mask Register (address = 0x03) [reset = 0xFFFF
        1. Table 51. ALM_CLK_MASK Field Descriptions
      5. 8.5.5  SERDES Loss of Signal Detection Alarms Register (address = 0x04) [reset = variable]
        1. Table 52. ALM_SD_DET Field Descriptions
      6. 8.5.6  SYSREF Alignment Circuit Alarms Register (address = 0x05) [reset = variable]
        1. Table 53. ALM_SYSREF_DET Field Descriptions
      7. 8.5.7  Temperature Sensor and PLL Loop Voltage Register (address = 0x06) [reset = variable]
        1. Table 54. TEMP_PLLVOLT Field Descriptions
      8. 8.5.8  Page Set Register (address = 0x09) [reset = 0x0000]
        1. Table 55. PAGE_SET Field Descriptions
      9. 8.5.9  SYSREF Align to r1 and r3 Count Register (address = 0x78) [reset = 0x0000]
        1. Table 56. SYSREF_ALIGN_R Field Descriptions
      10. 8.5.10 SYSREF Phase Count 1 and 2 Register (address = 0x79) [reset = 0x0000]
        1. Table 57. SYSREF12_CNT Field Descriptions
      11. 8.5.11 SYSREF Phase Count 3 and 4 Register (address = 0x7A) [reset = 0x0000]
        1. Table 58. SYSREF34_CNT Field Descriptions
      12. 8.5.12 Vendor ID and Chip Version Register (address = 0x7F) [reset = 0x0009]
        1. Table 59. VENDOR_VER Field Descriptions
      13. 8.5.13 Multi-DUC Configuration (PAP, Interpolation) Register (address = 0x0A) [reset = 0x02B0]
        1. Table 60. MULTIDUC_CFG1 Field Descriptions
      14. 8.5.14 Multi-DUC Configuration (Mixers) Register (address = 0x0C) [reset = 0x2402]
        1. Table 61. MULTIDUC_CFG2 Field Descriptions
      15. 8.5.15 JESD FIFO Control Register (address = 0x0D)[reset = 0x8000]
        1. Table 62. JESD_FIFO Field Descriptions
      16. 8.5.16 Alarm Mask 1 Register (address = 0x0E) [reset = 0x00FF]
        1. Table 63. ALM_MASK1 Field Descriptions
      17. 8.5.17 Alarm Mask 2 Register (address = 0x0F) [reset = 0xFFFF]
        1. Table 64. ALM_MASK2 Field Descriptions
      18. 8.5.18 Alarm Mask 3 Register (address = 0x10) [reset = 0xFFFF]
        1. Table 65. ALM_MASK3 Field Descriptions
      19. 8.5.19 Alarm Mask 4 Register (address = 0x11) [reset = 0xFFFF]
        1. Table 66. ALM_MASK4 Field Descriptions
      20. 8.5.20 JESD Lane Skew Register (address = 0x12) [reset = 0x0000]
        1. Table 67. JESD_LN_SKEW Field Descriptions
      21. 8.5.21 CMIX Configuration Register (address = 0x17) [reset = 0x0000]
        1. Table 68. CMIX Field Descriptions
      22. 8.5.22 Output Summation and Delay Register (address = 0x19) [reset = 0x0000]
        1. Table 69. OUTSUM Field Descriptions
      23. 8.5.23 NCO Phase Path AB Register (address = 0x1C) [reset = 0x0000]
        1. Table 70. PHASE_NCOAB Field Descriptions
      24. 8.5.24 NCO Phase Path CD Register (address = 0x1D) [reset = 0x0000]
        1. Table 71. PHASE_NCOCD Field Descriptions
      25. 8.5.25 NCO Frequency Path AB Register (address = 0x1E-0x20) [reset = 0x0000 0000 0000]
        1. Table 72. FREQ_NCOAB Field Descriptions
      26. 8.5.26 NCO Frequency Path CD Register (address = 0x21-0x23) [reset = 0x0000 0000 0000]
        1. Table 73. FREQ_NCOCD Field Descriptions
      27. 8.5.27 SYSREF Use for Clock Divider Register (address = 0x24) [reset = 0x0010]
        1. Table 74. SYSREF_CLKDIV Field Descriptions
      28. 8.5.28 Serdes Clock Control Register (address = 0x25) [reset = 0x7700]
        1. Table 75. SERDES_CLK Field Descriptions
      29. 8.5.29 Sync Source Control 1 Register (address = 0x27) [reset = 0x1144]
        1. Table 76. SYNCSEL1 Field Descriptions
      30. 8.5.30 Sync Source Control 2 Register (address = 0x28) [reset = 0x0000]
        1. Table 77. SYNCSEL2 Field Descriptions
      31. 8.5.31 PAP path AB Gain Attenuation Step Register (address = 0x29) [reset = 0x0000]
        1. Table 78. PAP_GAIN_AB Field Descriptions
      32. 8.5.32 PAP path AB Wait Time Register (address = 0x2A) [reset = 0x0000]
        1. Table 79. PAP_WAIT_AB Field Descriptions
      33. 8.5.33 PAP path CD Gain Attenuation Step Register (address = 0x2B) [reset = 0x0000]
        1. Table 80. PAP_GAIN_CD Field Descriptions
      34. 8.5.34 PAP Path CD Wait Time Register (address = 0x2C) [reset = 0x0000]
        1. Table 81. PAP_WAIT_CD Field Descriptions
      35. 8.5.35 PAP path AB Configuration Register (address = 0x2D) [reset = 0x0FFF]
        1. Table 82. PAP_CFG_AB Field Descriptions
      36. 8.5.36 PAP path CD Configuration Register (address = 0x2E) [reset = 0x0FFF]
        1. Table 83. PAP_CFG_CD Field Descriptions
      37. 8.5.37 DAC SPI Configuration Register (address = 0x2F) [reset = 0x0000]
        1. Table 84. SPIDAC_TEST1 Field Descriptions
      38. 8.5.38 DAC SPI Constant Register (address = 0x30) [reset = 0x0000]
        1. Table 85. SPIDAC_TEST2 Field Descriptions
      39. 8.5.39 Gain for path AB Register (address = 0x32) [reset = 0x0400]
        1. Table 86. GAINAB Field Descriptions
      40. 8.5.40 Gain for path CD Register (address = 0x33) [reset = 0x0400]
        1. Table 87. GAINCD Field Descriptions
      41. 8.5.41 JESD Error Counter Register (address = 0x41) [reset = 0x0000]
        1. Table 88. JESD_ERR_CNT Field Descriptions
      42. 8.5.42 JESD ID 1 Register (address = 0x46) [reset = 0x0044]
        1. Table 89. JESD_ID1 Field Descriptions
      43. 8.5.43 JESD ID 2 Register (address = 0x47) [reset = 0x190A]
        1. Table 90. JESD ID 2 Register (JESD_ID2)
      44. 8.5.44 JESD ID 3 and Subclass Register (address = 0x48) [reset = 0x31C3]
        1. Table 91. JESD_ID3 Field Descriptions
      45. 8.5.45 JESD Lane Enable Register (address = 0x4A) [reset = 0x0003]
        1. Table 92. JESD_LN_EN Field Descriptions
      46. 8.5.46 JESD RBD Buffer and Frame Octets Register (address = 0x4B) [reset = 0x1300]
        1. Table 93. JESD_RBD_F Field Descriptions
      47. 8.5.47 JESD K and L Parameters Register (address = 0x4C) [reset = 0x1303]
        1. Table 94. JESD_K_L Field Descriptions
      48. 8.5.48 JESD M and S Parameters Register (address = 0x4D) [reset = 0x0100]
        1. Table 95. JESD_M_S Field Descriptions
      49. 8.5.49 JESD N, HD and SCR Parameters Register (address = 0x4E) [reset = 0x0F4F]
        1. Table 96. JESD_N_HD_SCR Field Descriptions
      50. 8.5.50 JESD Character Match and Other Register (address = 0x4F) [reset = 0x1CC1]
        1. Table 97. JESD_MATCH Field Descriptions
      51. 8.5.51 JESD Link Configuration Data Register (address = 0x50) [reset = 0x0000]
        1. Table 98. JESD_Link_CFG Field Descriptions
      52. 8.5.52 JESD Sync Request Register (address = 0x51) [reset = 0x00FF]
        1. Table 99. JESD_SYNC_REQ Field Descriptions
      53. 8.5.53 JESD Error Output Register (address = 0x52) [reset = 0x00FF]
        1. Table 100. JESD_ERR_OUT Field Descriptions
      54. 8.5.54 JESD ILA Check 1 Register (address = 0x53) [reset = 0x0100]
        1. Table 101. JESD_ILA_CFG1 Field Descriptions
      55. 8.5.55 JESD ILA Check 2 Register (address = 0x54) [reset = 0x8E60]
        1. Table 102. JESD_ILA_CFG2 Field Descriptions
      56. 8.5.56 JESD SYSREF Mode Register (address = 0x5C) [reset = 0x0001]
        1. Table 103. JESD_SYSR_MODE Field Descriptions
      57. 8.5.57 JESD Crossbar Configuration 1 Register (address = 0x5F) [reset = 0x0123]
        1. Table 104. JESD_CROSSBAR1 Field Descriptions
      58. 8.5.58 JESD Crossbar Configuration 2 Register (address = 0x60) [reset = 0x4567]
        1. Table 105. JESD_CROSSBAR2 Field Descriptions
      59. 8.5.59 JESD Alarms for Lane 0 Register (address = 0x64) [reset = 0x0000]
        1. Table 106. JESD_ALM_L0 Field Descriptions
      60. 8.5.60 JESD Alarms for Lane 1 Register (address = 0x65) [reset = 0x0000]
        1. Table 107. JESD_ALM_L1 Field Descriptions
      61. 8.5.61 JESD Alarms for Lane 2 Register (address = 0x66) [reset = 0x0000]
        1. Table 108. JESD_ALM_L2 Field Descriptions
      62. 8.5.62 JESD Alarms for Lane 3 Register (address = 0x67) [reset = 0x0000]
        1. Table 109. JESD_ALM_L3 Field Descriptions
      63. 8.5.63 JESD Alarms for Lane 4 Register (address = 0x68) [reset = 0x0000]
        1. Table 110. JESD_ALM_L4 Field Descriptions
      64. 8.5.64 JESD Alarms for Lane 5 Register (address = 0x69) [reset = 0x0000]
        1. Table 111. JESD_ALM_L5 Field Descriptions
      65. 8.5.65 JESD Alarms for Lane 6 Register (address = 0x6A [reset = 0x0000]
        1. Table 112. JESD_ALM_L6 Field Descriptions
      66. 8.5.66 JESD Alarms for Lane 7 Register (address = 0x6B) [reset = 0x0000]
        1. Table 113. JESD Alarms for Lane 7 Register (JESD_ALM_L7)
      67. 8.5.67 SYSREF and PAP Alarms Register (address = 0x6C) [reset = 0x0000]
        1. Table 114. ALM_SYSREF_PAP Field Descriptions
      68. 8.5.68 Clock Divider Alarms 1 Register (address = 0x6D) [reset = 0x0000]
        1. Table 115. ALM_CLKDIV1 Field Descriptions
      69. 8.5.69 Clock Configuration Register (address = 0x0A) [reset = 0xFC03]
        1. Table 116. CLK_CONFIG Field Descriptions
      70. 8.5.70 Sleep Configuration Register (address = 0x0B) [reset = 0x0022]
        1. Table 117. SLEEP_CONFIG Field Descriptions
      71. 8.5.71 Divided Output Clock Configuration Register (address = 0x0C) [reset = 0x2002]
        1. Table 118. CLK_OUT Field Descriptions
      72. 8.5.72 DAC Fullscale Current Register (address = 0x0D) [reset = 0xF000]
        1. Table 119. DACFS Field Descriptions
      73. 8.5.73 Internal SYSREF Generator Register (address = 0x10) [reset = 0x0000]
        1. Table 120. LCMGEN Field Descriptions
      74. 8.5.74 Counter for Internal SYSREF Generator Register (address = 0x11) [reset = 0x0000]
        1. Table 121. LCMGEN_DIV Field Descriptions
      75. 8.5.75 SPI SYSREF for Internal SYSREF Generator Register (address = 0x12) [reset = 0x0000]
        1. Table 122. LCMGEN_SPISYSREF Field Descriptions
      76. 8.5.76 Digital Test Signals Register (address = 0x1B) [reset = 0x0000]
        1. Table 123. DTEST Field Descriptions
      77. 8.5.77 Sleep Pin Control Register (address = 0x23) [reset = 0xFFFF]
        1. Table 124. SLEEP_CNTL Field Descriptions
      78. 8.5.78 SYSREF Capture Circuit Control Register (address = 0x24) [reset = 0x1000]
        1. Table 125. SYSR_CAPTURE Field Descriptions
      79. 8.5.79 Clock Input and PLL Configuration Register (address = 0x31) [reset = 0x0200]
        1. Table 126. Clock Input and PLL Configuration Register (CLK_PLL_CFG)
      80. 8.5.80 PLL Configuration 1 Register (address = 0x32) [reset = 0x0308]
        1. Table 127. CONFIG1 Field Descriptions
      81. 8.5.81 PLL Configuration 2 Register (address = 0x33) [reset = 0x4018]
        1. Table 128. PLL_CONFIG2 Field Descriptions
      82. 8.5.82 LVDS Output Configuration Register (address = 0x34) [reset = 0x0000]
        1. Table 129. LVDS_CONFIG Field Descriptions
      83. 8.5.83 Fuse Farm clock divider Register (address = 0x35) [reset = 0x0018]
        1. Table 130. PLL_FDIV Field Descriptions
      84. 8.5.84 Serdes Clock Configuration Register (address = 0x3B) [reset = 0x1802]
        1. Table 131. SRDS_CLK_CFG Field Descriptions
      85. 8.5.85 Serdes PLL Configuration Register (address = 0x3C) [reset = 0x8228]
        1. Table 132. SRDS_PLL_CFG Field Descriptions
      86. 8.5.86 Serdes Configuration 1 Register (address = 0x3D) [reset = 0x0x0088]
        1. Table 133. RDS_CFG1 Field Descriptions
      87. 8.5.87 Serdes Configuration 2 Register (address = 0x3E) [reset = 0x0x0909]
        1. Table 134. SRDS_CFG2 Field Descriptions
      88. 8.5.88 Serdes Polarity Control Register (address = 0x3F) [reset = 0x0000]
        1. Table 135. SRDS_POL Field Descriptions
      89. 8.5.89 JESD204B SYNCB OUTPUT Register (address = 0x76) [reset = 0x0000]
        1. Table 136. SYNCBOUT Field Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Start-up Sequence
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Calculating the JESD204B SerDes rate
      4. 9.2.4 Calculating valid JESD204B SYSREF Frequency
      5. 9.2.5 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Sequencing
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Related Links
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
  14. IMPORTANT NOTICE
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DATA SHEET

DAC38RF8x Dual-Channel, Differential-Output, 14-Bit, 9-GSPS, RF-Sampling DAC With JESD204B Interface, On-Chip PLL and Wide-Band Interpolation

1 Features

  • 14-Bit resolution, 9-GSPS DAC with multimode operation
    • 16-Bit, Dual-channel data mode
      • Max input rate: 2.5-GSPS
      • Wideband digital up-converter
        • Interpolation: 1,2,4,6,8,10,12,16,18,20,24x
    • 12-Bit, Dual-channel data mode
      • Max input rate: 3.33-GSPS
      • Wideband digital Up-converter
        • Interpolation: 1,2,24x
    • 8-Bit, Single-channel data mode
      • Max input rate: 9-GSPS
  • JESD204B interface
    • Subclass 1 for multichip synchronization
    • DAC38RF89: Maximum lane rate: 12.5 Gbps
    • DAC38RF82: Maximum lane rate: 12.8 Gbps
  • Differential output
    • Supports DC coupling
    • RF Full-scale output power (with 2:1 balun):
      3 dBm at 2.14 GHz
  • Internal PLL and VCO with bypass
    • DAC38RF82: fC(VCO) = 5.9 or 8.9 GHz
    • DAC38RF89: fC(VCO) = 5 or 7.5 GHz
  • Power supplies: -1.8 V, 1.0 V, 1.8 V
  • Package: 10 x 10 mm BGA, 0.8 mm pitch,
    144-balls

2 Applications

  • Arbitrary waveform generators
  • Radar and electronic warfare
  • Communications test equipment
  • Direct RF synthesis for DOCSIS 3.0/3.1
  • Microwave backhaul

3 Description

The DAC38RF82 and DAC38RF89 are high performance, wide bandwidth RF-sampling digital-to-analog (DACs) that are capable of dual channel input data rate up to 3.33 GSPS or single-channel operation with 8-bits up to 9-GSPS. The devices have a low power JESD204B Interface with up to 8 lanes, with a maximum bit rate of 12.5 Gbps (DAC38RF89) and 12.8 Gbps (DAC38RF82).

In dual channel operation, the input interface is capable of data rates up to 3.33 GSPS at 12-bits and 2.5 GSPS at 16-bits resolution without interpolation. When used as a complex baseband transmitter with interpolation modes from 2x to 24x, the DAC38RF82 or DAC38RF89 is capable of synthesizing wideband signals up to 2 GHz bandwidth with 16-bit input resolution and 2.66 GHz bandwidth with 12-bit input resolution.

The 8-bit mode allows an input at the full 9 GSPS maximum DAC sample rate and can synthesize wideband signals from 0 to 4.5 GHz.

An optional low jitter PLL/VCO simplifies the DAC clock generation by allowing use of a lower frequency reference clock. DAC38RF82 and DAC38RF89 support different VCO frequency ranges, summarized in Device Comparison Table.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
DAC38RF82 FCBGA (144) 10.0 mm x 10.0 mm
DAC38RF89
  1. For all available packages, see the orderable addendum at the end of the data sheet.

32x6 MHz 256-QAM Carriers

DAC38RF82 DAC38RF89 192MHz_QAM_SLASEA6.gif

4 Revision History

Changes from C Revision (August 2017) to D Revision

  • Changed Feature From: Maximum lane rate: 12.5 Gbps To: DAC38RF89: Maximum lane rate: 12.5 GbpsGo
  • Changed Feature From: Maximum lane rate: 12.5 Gbps To: DAC38RF82: Maximum lane rate: 12.8 GbpsGo
  • Changed From: maximum bit rate of 12.5 Gbpss To: maximum bit rate of 12.5 Gbps (DAC38RF89) and 12.8 Gbps (DAC38RF82) the DescriptionGo
  • Added note to TJ in the Absolute Maximum RatingsGo
  • Changed the fSerDes MAX value From: 12.5 Gbps To: 12.8 Gbps for DAC38RF82Go
  • Changed From: maximum bit rate of 12.5 Gbps. To: maximum bit rate of 12.5 Gbps (DAC38RF89) and 12.8 Gbps (DAC38RF82) in the OverviewGo
  • Changed from: SerDes lane is 12.5 Gbps To: SerDes lane is 12.5 Gbps (DAC38RF89) and 12.8 Gbps (DAC38RF82) in SerDes RateGo
  • Deleted JESD204B Subclass 0 SupportGo
  • Added Writing to Reserved BitsGo
  • Changed 0x04 and 0x05 From: 0x0000 To: variable in Table 47Go
  • Added Note 1 to Table 47Go
  • Changed 0x7F From: 0x0008 To: 0x0009 in Table 47Go
  • Changed 0x0D From: 0x8300 To: 0x8000 in Table 47Go
  • Changed 0x0F From: 0x1F83 To: 0xFFFF in Table 47Go
  • Changed 0x32 and 0x33 From: 0x0800 To: 0x0400 in Table 47Go
  • Changed 0x23 From: 0x03F3 To: 0xFFFF in Table 47Go
  • Changed 0x3B From: 0x0002 To: 0x1802 in Table 47Go
  • Changed From: [reset = 0x0000] To: [reset = variable] in SERDES Loss of Signal Detection Alarms Register (address = 0x04) [reset = variable]Go
  • Changed From: [reset = 0x0000] To: [reset = variable] in SERDES Loss of Signal Detection Alarms Register (address = 0x04) [reset = variable]Go
  • Changed From: [reset = 0x0008] To: [reset = 0x0009] in Vendor ID and Chip Version Register (address = 0x7F) [reset = 0x0009]Go
  • Changed From: [reset = 0x1300] To: [reset = 0x8000] in JESD FIFO Control Register (address = 0x0D)[reset = 0x8000]Go
  • Changed From: [reset = 0x0000] To: [reset = 0x0400] in Gain for path AB Register (address = 0x32) [reset = 0x0400]Go
  • Changed From: [reset = 0x0000] To: [reset = 0x0400] in Gain for path CD Register (address = 0x33) [reset = 0x0400]Go
  • Changed all bits From R To R/W in Figure 94Go
  • Changed all bits From R To R/W in Figure 95Go
  • Changed the Description of Bit 3:1 in Table 91Go
  • Changed Bit 1 From: MIN_LATENCY_ENA To: Reserved in Table 97Go
  • Changed the title of Figure 110 To: JESD Crossbar Configuration 2 Register (JESD_CROSSBAR2)Go
  • Changed the title of Figure 111 To: JESD Alarms for Lane 0 Register (JESD_ALM_L2)Go
  • Changed the title of Figure 111 To: JESD Alarms for Lane 5 Register (JESD_ALM_L5)Go
  • Changed From: [reset = 0xF000] To: [reset = 0xFC03] in Clock Configuration Register (address = 0x0A) [reset = 0xFC03]Go
  • Changed From: [reset = 0x8000] To: [reset = 0x2002] in Divided Output Clock Configuration Register (address = 0x0C) [reset = 0x2002]Go
  • Added Note 1 to Table 120Go
  • Changed the description of Bit 1 From: TBD To: Enables SPI SYSREF for Internal SYSREF Generator in Table 120Go
  • Added Note 1 to Table 121Go
  • Added Note 1 to Table 122Go
  • Changed From: [reset = 0x0002] To: [reset = 0x1802] in Serdes Clock Configuration Register (address = 0x3B) [reset = 0x1802]Go
  • Changed the reset value of Bit 14:11 From: 0x0 To: 0111 in Table 131Go
  • Changed Bit 4:2 From: BUSWIDTH To: Reserved in Table 134Go

Changes from B Revision (August 2017) to C Revision

  • Changed the tr NOM value from 50 ns To 50 ps in the Anaolog Output of the Timing Requirements tableGo
  • Changed the tf NOM value from 50 ns To 50 ps in the Anaolog Output of the Timing Requirements tableGo
  • Changed the MPY values in Table 4Go
  • Changed The title From: SerDes PLL Modes Selection To: SerDes PLL Multiplier (MPY) Values in in Table 4Go
  • Added section: Digital Quadrature ModulatorGo
  • Added section: Low Power Coarse Resolution Mixing ModesGo
  • Added cross reference to MPY values in Table 132Go
  • Changed the enable/disable description for bit [15:13] of Table 134Go

Changes from A Revision (April 2017) to B Revision

  • Deleted Changed Feature From: Interpolation: 1,2,4,24x To: Interpolation: 1,2,24xGo
  • Changed the ALARM pin From: alarm_out_pol To: alm_out_pol in the Pin Functions tableGo
  • Changed the Description of pins A3, A4, A7, A6, A9, A10, A12, E12, F11, F7, G6, H5, H7, J6, J11 in the Pin Functions tableGo
  • Changed description of TXENABLE pin in the PIN Functions tableGo
  • Changed the MAX value of VEE18N rail From: 0.5 V To 0.3 V in the Absolute Maximum Ratings tableGo
  • Added "Supply Voltage Range" to the Recommended Operating Conditions tableGo
  • Changed DNL typical value From: ±0.5 to ±3 LSB in Electrical Characteristics - DC Specifications tableGo
  • Changed INL typical value From: ±1 To: ±4 LSB in Electrical Characteristics - DC Specifications tableGo
  • Added "Reference voltage drift" to the Electrical Characteristics - DC Specifications tableGo
  • Changed Power Dissipation Test Condition From: MODE 5: dual channel, 8-bit input mode, 2x Interpolation To: MODE 5: dual channel, 8-bit input mode, 1x Interpolation in the Electrical Characteristics - DC SpecificationsGo
  • Changed the ILOAD values to negative for CMOS interface parameter, low-level output voltage, in the Electrical Characteristics - Digital Specifications tableGo
  • Added 0 dBFS to the condition statement for the Electrical Characteristics - AC Specifications tableGo
  • Added MIN and TYP value to maximum DAC sample rate for DAC38RF89 only in the Electrical Characteristics - AC Specifications tableGo
  • Changed the Isolation values in the TEST CONDITIONS, TYP value From: 74 dBc To: 82 dBc and 56 dBc To 73 dBc in the Electrical Characteristics - AC Specifications tableGo
  • Added NSD values for DAC38RF82 with on-chip PLL enabled to Electrical Characteristics - AC Specifications tableGo
  • Added Figure 16Go
  • Added MPY value for 16.5x in the Table 4Go
  • Changed input rate max and fdac max for 6x interpolation mode in Table 9Go
  • Changed input data rate From: 6666 MSPS To: 3333 MSPS for LMFSHd=41380, 2x interpolation in Table 9Go
  • Changed Table 12, JESD204B frame format for LMFSHd=84111 Go
  • Changed Table 14, JESD204B frame format for LMFSHd=44210Go
  • Changed Table 16, JESD204B frame format for LMFSHd = 24410Go
  • Changed Table 17, JESD204B frame format for LMFSHd = 44210Go
  • Changed Table 18, JESD204B frame format for LMFSHd = 88210Go
  • Changed Table 19, JESD204B frame format for LMFSHd = 24410Go
  • Changed Table 20, JESD204B frame format for LMFSHd=48410Go
  • Changed Table 21, JESD204B frame format for LMFSHd = 24310Go
  • Changed Table 22, JESD204B frame format for LMFSHd = 48310Go
  • Changed Table 23, JESD204B frame format for LMFSHd = 81180Go
  • Changed Table 24, JESD204B frame format for LMFSHd = 41380Go
  • Changed Table 26, JESD204B frame format for LMFSHd = 41121Go
  • Added Table 27, JESD204B frame format for LMFSHd = 41121Go
  • Changed Table 38Go
  • Changed register field programming values for LMFSHd=24410, 41380, 41121 and 24310 in the Register Programming for JESD and Interpolation Mode tableGo
  • Changed the bit positions of N_M1 register field From: 12-8 To: 4-0 in the Table 42 tableGo
  • Changed the bit positions of N_M1’ (NPRIME_M1) register field From: 4-0 To: 12-0 in the Table 42 tableGo
  • Changed the description of DAC PLL alarm in Alarm MonitoringGo
  • Changed from BIST_ENA to Reserved in Table 61Go
  • Changed from BIST_ZERO to Reserved in Table 61Go
  • Changed the description of OUTSUM_SEL field in Table 69Go
  • Changed the Description of Bit 11 From "dummy data generation" to "distortion enhancement" in Table 116Go
  • Changed the junction temp and loop filter voltage range for PLL tuning in Figure 142Go

Changes from * Revision (February 2017) to A Revision

  • Corrected the NSD values for -9dBFS in Electrical Characteristics - AC Specifications table Go
  • Added PLL/VCO characteristics table to PLL/VCO Electrical CharacteristicsGo
  • Added JESD204B clock phase register setting to Table 41Go
  • Removed descriptions for CLKJESD_DIV register from Table 41Go
  • Added JESD204B clock phase register setting to Table 42Go
  • Added information about the DAC output total current for various full scale current settings in DAC Fullscale Output CurrentGo
  • Changed Bit 0 of Table 128 From: Enables the GSM PLL To: ReservedGo
  • Changed Table 130Go
  • Changed description of SERDES_REFCLK_DIV register field in Table 131Go
  • Changed Bit 12:11, 6:5 and 4:2 of Table 134Go

5 Device Comparison Table

PART NUMBER ANALOG OUTPUT TYPE VCO0 CENTER FREQUENCY VCO1 CENTER FREQUENCY
DAC38RF82 Differential 5.9 GHz 8.9 GHz
DAC38RF89 Differential 5 GHz 7.5 GHz

6 Pin Configuration and Functions

AAV Package
144-Pin (FCBGA)
Top View

Pin Functions

PIN I/O DESCRIPTION
NO. NAME
C11, C12, D11, E11, F12, J12, K11, L11, M11, M12 AGND – Analog ground.
K8 ALARM O CMOS output for ALARM condition. Default polarity is active low, but can be changed to active high via RESET_CONFIG alm_out_pol control bit..
G3 AMUX0 O Analog test pin for SerDes, Lane 0 to Lane 3. Can be left floating.
F3 AMUX1 O Analog test pin for SerDes, Lane 4 to Lane 7. Can be left floating.
C8 ATEST O Analog test pin for DAC, references and PLL. Can be left floating.
A7 CLKTX+ O Divided output clock, internal 100 Ω differential termination, self-biased, positive terminal.
A6 CLKTX- O Divided output clock, internal 100 Ω differential termination, self-biased, negative terminal.
A10 DACCLK+ I Device clock, internal 100 Ω differential termination, self-biased, positive terminal.
A9 DACCLK- I Device clock, internal 100 Ω differential termination, self-biased, negative terminal.
A12 DACCLKSE I Single ended device clock optional input. Can be left floating if not used, internal 50 Ω termination.
A2, B2, C2, D2, D6, E2, E7, F2, F6, G2, G7, H6, J7, K2, L2, L3, L4, L5, M6 DGND - Digital ground.
C10 EXTIO I/O Requires a 0.1 μF decoupling capacitor to AGND.
K7 GPI0 - Factory use only. User should GND.
M7 GPI1 - Factory use only. User should GND.
L7 GPO0 O Used for CMOS SYNC0\ signal.
L6 GPO1 O Used for CMOS SYNC1\ signal.
D3 IFORCE O Test pin for on chip parametrics. Can be left floating.
C9 RBIAS O Full-scale output current bias. Change the full-scale output current through DACFS in register DACFS (8.5.72). Expected to be 3.6 kΩ to GND for 40 mA full scale output.
K9 RESET I Active low input for chip RESET, which resets all the programming registers to their default state. Internal pull-up.
J1 RX0+ I CML SerDes interface lane 0 input, positive
K1 RX0- I CML SerDes interface lane 0 input, negative
M1 RX1+ I CML SerDes interface lane 1 input, positive
L1 RX1- I CML SerDes interface lane 1 input, negative
M2 RX2+ I CML SerDes interface lane 2 input, positive
M3 RX2- I CML SerDes interface lane 2 input, negative
M5 RX3+ I CML SerDes interface lane 3 input, positive
M4 RX3- I CML SerDes interface lane 3 input, negative
H1 RX4+ I CML SerDes interface lane 4 input, positive
G1 RX4- I CML SerDes interface lane 4 input, negative
E1 RX5+ I CML SerDes interface lane 5 input, positive
F1 RX5- I CML SerDes interface lane 5 input, negative
D1 RX6+ I CML SerDes interface lane 6 input, positive
C1 RX6- I CML SerDes interface lane 6 input, negative
A1 RX7+ I CML SerDes interface lane 7 input, positive
B1 RX7- I CML SerDes interface lane 7 input, negative
L9 SCLK I Serial interface clock. Internal pull-down.
M8 SDEN I Active low serial data enable, always an input to the DAC38RFxx. Internal pull-up.
M10 SDIO I/O Serial interface data. Bi-directional in 3-pin mode (default) and uni-directional input 4-pin mode. Internal pull-down.
M9 SDO O Uni-directional serial interface data output in 4-pin mode. The SDO pin is tri-stated in 3-pin interface mode (default).
L8 SLEEP I Active high asynchronous hardware power-down input. Internal pull-down.
C4 SYNC0+ O Synchronization request to transmitter for JESD204B link 0, LVDS positive output.
C3 SYNC0- O Synchronization request to transmitter for JESD204B link 0, LVDS negative output.
C7 SYNC1+ O Synchronization request to transmitter for JESD204B link 1, LVDS positive output.
C6 SYNC1- O Synchronization request to transmitter for JESD204B link 1, LVDS negative output.
A3 SYSREF+ I LVPECL SYSREF positive input, internal 100 Ω differential termination, self biased. This positive/negative pair is captured with the rising edge of DACCLKP/N. It is used for multiple DAC synchronization.
A4 SYSREF- I LVPECL SYSREF negative input, self biased, internal 100 Ω differential termination. (See the SYSREF+ description)
K4 TCLK I JTAG test clock. Internal pull-down
H4 TDI I JTAG test data in. Internal pull-up
J4 TDO O JTAG test data out. Internal pull-up
K3 TESTMODE - This pin is used for factory testing.
Recommended to connect to ground for normal operation.
K5 TMS I JTAG test mode select. Internal pull-up
J5 TRST I JTAG test reset. Internal pull-up. Must be connected to ground if not used
K6 TXENABLE I Transmit enable active high input. Internal pull-down.
This pin is ORed with spi_txenable bit in JESD_FIFO register to enable analog output data transmission.
To enable analog output data transmission, pull CMOS TXENABLE pin to high.
To disable analog output, pull CMOS TXENABLE pin to low. The DAC output is forced to midscale.
F11, J11 VDDA1 I Analog 1 V supply voltage. Must be separated from VDDDIG1 supply for best performance.
G11, H11 VDDA18 I Analog 1.8 V supply voltage. (1.8 V)
D8, E8 VDDPLL1 I Analog 1 V supply for PLL.
B9, B10 VDDAPLL18 I PLL analog supply voltage. (1.8 V)
D9, E9 VDDAVCO18 I Analog supply voltage for VCO (1.8 V)
G9, H9 VDDCLK1 I Internal clock buffer supply voltage (1 V).
It is recommended to isolate this supply from VDDDIG1 and VDDA1.
G8, H8 VDDL1_1 I DAC core supply voltage. (1 V)
G10, H10 VDDL2_1 I DAC core supply voltage. (1 V)
A5, B5, C5, D5, D7, E3, E4, E5, E6, F4, F5, G4, G5 VDDDIG1 I Digital supply voltage. (1 V).
It is recommended to isolate this supply from VDDCLK1 and VDDA1.
F7, H7, G6, J6 VDDE1 I Digital Encoder supply voltage (1 V).
Must be separated from VDDDIG1 supply
H5 VDDIO18 I Supply voltage for all digital I/O and CMOS I/O. (1.8 V)
G12, H12 VDDOUT18 I DAC output supply. (1.8 V)
H2, J2 VDDR18 I Supply voltage for SerDes. (1.8 V)
B3, B4 VDDS18 I Supply voltage for LVDS SYNC0+/- and SYNC1+/- (1.8 V)
H3, J3 VDDT1 I Supply voltage for SerDes termination. (1 V)
B6 VDDTX1 I Supply voltage for divided clock output. (1 V)
B7 VDDTX18 I Supply voltage for divided clock output . (1.8 V)
D10, E10, K10, L10 VEE18N I Analog supply voltage. (-1.8 V)
L12 VOUT1+ O DAC channel 1 output.
K12 VOUT1- O DAC channel 1 complementary output.
D12 VOUT2+ O DAC channel 2 output.
E12 VOUT2- O DAC channel 2 complementary output.
D4 VSENSE O Test pin for on chip parametrics. Can be left floating.
A8, A11, B8, B11, B12, F8, F9, F10, J8, J9, J10 VSSCLK - Clock ground.

7 Specifications

 
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