CDCLVP2106 12-LVPECL Output, High-Performance Clock Buffer
- SCAS887B September 2009 – January 2016 CDCLVP2106
  
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DATA SHEET

CDCLVP2106 12-LVPECL Output, High-Performance Clock Buffer

1 Features

Dual 1:6 Differential Buffer
Two Clock Inputs
Universal Inputs Can Accept LVPECL, LVDS, LVCMOS/LVTTL
12 LVPECL Outputs
Maximum Clock Frequency: 2 GHz
Maximum Core Current Consumption: 92 mA
Very Low Additive Jitter: <100 fs, RMS in 10-kHz to 20-MHz Offset Range
2.375-V to 3.6-V Device Power Supply
Maximum Propagation Delay: 550 ps
Maximum Within Bank Output Skew: 20 ps
LVPECL Reference Voltage, V_{AC_REF}, Available for Capacitive-Coupled Inputs
Industrial Temperature Range: –40°C to +85°C
Supports 105°C PCB Temperature (Measured with a Thermal Pad)
Available in 6-mm × 6-mm, 40-Pin VQFN (RHA) Package
ESD Protection Exceeds 2000 V (HBM)

2 Applications

Wireless Communications
Telecommunications/Networking
Medical Imaging
Test and Measurement Equipment

3 Description

The CDCLVP2106 is a highly versatile, low additive jitter buffer that can generate 12 copies of LVPECL clock outputs from two LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. Each buffer block consists of one input that feeds two LVPECL outputs. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 20 ps, making the device a perfect choice for use in demanding applications.

The CDCLVP2106 clock buffer distributes two clock inputs (IN0, IN1) to 12 pairs of differential LVPECL clock outputs (OUT0, OUT11) with minimum skew for clock distribution. Each buffer block consists of one input that feeds two LVPECL clock outputs. The inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.

The CDCLVP2106 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (V_{AC_REF}) should be applied to the unused negative input pin. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended.

The CDCLVP2106 is characterized for operation from –40°C to +85°C and is available in a 6-mm × 6-mm, VQFN-40 package.

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE (NOM)
CDCLVP2106	VQFN (40)	6.00 mm × 6.00 mm

For all available packages, see the orderable addendum at the end of the data sheet.

Simplified Schematic

4 Revision History

Changes from A Revision (August 2011) to B Revision

Added ESD Ratings table, Typical Characteristics section, Detailed Description section, Device Functional Modes section, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information sectionGo
Added support for 105ºC thermal pad temperature Go
Deleted Device Comparison table; information in POA Go
Changed order of Pin Functions table to alphabetical by pin name Go
Added V_OH specification for T_PCB≤ 105ºC in Electrical Characteristics: LVPECL Output, at V_CC = 2.375 V to 2.625 V Go
Added V_OL specification for T_PCB≤ 105ºC in Electrical Characteristics: LVPECL Output, at V_CC = 2.375 V to 2.625 V Go
Added I_EE specification for T_PCB≤ 105ºC in Electrical Characteristics: LVPECL Output, at V_CC = 2.375 V to 2.625 V Go
Added I_CC specification for T_PCB≤ 105ºC in Electrical Characteristics: LVPECL Output, at V_CC = 2.375 V to 2.625 V Go
Added V_OH specification for T_PCB≤ 105ºC in Electrical Characteristics: LVPECL Output, at V_CC = 3 V to 3.6 V Go
Added V_OL specification for T_PCB≤ 105ºC in Electrical Characteristics: LVPECL Output, at V_CC = 3 V to 3.6 V Go
Added I_EE specification for T_PCB≤ 105ºC in Electrical Characteristics: LVPECL Output, at V_CC = 3 V to 3.6 V Go
Added I_CC specification for T_PCB≤ 105ºC in Electrical Characteristics: LVPECL Output, at V_CC = 3 V to 3.6 V Go
Added Footnote "100 MHz Wenzel oscillator, Input slew rate = 0.9 V/ns (single-ended)."Go
Added t_RJIT for f _OUT = 100 MHz, Input AC coupled, V_ICM = V_{AC_REF}, 12 kHz to 20 MHz Go
Added t_RJIT for f_OUT = 122.88 MHz, Input AC coupled, V_ICM = V_{AC_REF}, 12 kHz to 20 MHz Go
Added t_RJIT for f_OUT = 156.25 MHz, Input AC coupled, V_ICM = V_{AC_REF}, 12 kHz to 20 MHz Go
Added t_RJIT for f_OUT = 312.5 MHz, Input AC coupled, V_ICM = V_{AC_REF}, 12 kHz to 20 MHz Go

Changes from * Revision (September 2009) to A Revision

Revised descriptions of pins 7 and 4Go
Corrected V_IL parameter description in Electrical Characteristics table for LVCMOS inputGo
Added footnote (2) to Electrical Characteristics table for LVPECL Output, V_CC = 2.375 V to 2.625 VGo
Changed recommended resistor values in Figure 12(a)Go
Changed recommended resistor values in Figure 16Go

5 Pin Configuration and Functions

RHA Package

40-Pin VQFN

Top View

1. Thermal pad must be soldered to ground.

Pin Functions

PIN		I/O	DESCRIPTION
NAME	NO.	I/O	DESCRIPTION
GND1, GND2	21, 30	Ground	Device grounds
INP0, INN0	9, 8	Input	Differential input pair or single-ended input no. 0
INP1, INN1	2, 3	Input	Differential input pair or single-ended input no. 1
OUTP0 OUTN0	12, 13	Output	Differential LVPECL output pair no. 0
OUTP1, OUTN1	14, 15	Output	Differential LVPECL output pair no. 1
OUTP2, OUTN2	16, 17	Output	Differential LVPECL output pair no. 2
OUTP3, OUTN3	18, 19	Output	Differential LVPECL output pair no. 3
OUTP4, OUTN4	22, 23	Output	Differential LVPECL output pair no. 4
OUTP5, OUTN5	24, 25	Output	Differential LVPECL output pair no. 5
OUTP6, OUTN6	26, 27	Output	Differential LVPECL output pair no. 6
OUTP7, OUTN7	28, 29	Output	Differential LVPECL output pair no. 7
OUTP8, OUTN8	32, 33	Output	Differential LVPECL output pair no. 8
OUTP9, OUTN9	34, 35	Output	Differential LVPECL output pair no. 9
OUTP10, OUTN10	36, 37	Output	Differential LVPECL output pair no. 10
OUTP11, OUTN11	38, 39	Output	Differential LVPECL output pair no. 11
V_{AC_REF0}	7	Output	Bias voltage output for capacitive coupled input pair no. 0. Do not use V_{AC_REF} at V_CC < 3 V. If used, TI recommends a 0.1-μF capacitor to GND on this pin. The output current is limited to 2 mA.
V_{AC_REF1}	4	Output	Bias voltage output for capacitive coupled input pair no. 1. Do not use V_{AC_REF} at V_CC < 3 V. If used, TI recommends using a 0.1-μF capacitor to GND on this pin. The output current is limited to 2 mA.
V_CC	5, 6, 11, 20, 31, 40	Power	2.5-V or 3.3-V supplies for the device
NC	1, 10	—	Do not connect

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
V_CC	Supply voltage⁽²⁾	–0.5	4.6	V
V_IN	Input voltage⁽³⁾	–0.5	V_CC+ 0.5	V
V_OUT	Output voltage⁽³⁾	–0.5	V_CC + 0.5	V
I_IN	Input current		20	mA
I_OUT	Output current		50	mA
T_A	Specified free-air temperature (no airflow)	–40	85	°C
T_J	Maximum junction temperature		125	°C
T_stg	Storage temperature	–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All supply voltages must be supplied simultaneously.

(3) The input and output negative voltage ratings may be exceeded if the input clamp-current and output clamp-current ratings are observed.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	1000	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted).

		MIN	NOM	MAX	UNIT
V_CC	Supply voltage	2.375	2.5/3.3	3.60	V
T_A	Ambient temperature	–40		85	°C
T_PCB	PCB temperature (measured at thermal pad)			105	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾⁽²⁾⁽³⁾			CDCLVP2106	UNIT
			(RHA) VQFN
			40 PINS
R_θJA	Junction-to-ambient thermal resistance⁽⁴⁾	0 LFM	34.7	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance		23.7	°C/W
R_θJB	Junction-to-board thermal resistance		10.1	°C/W
ψ_JT	Junction-to-top characterization parameter		0.5	°C/W
ψ_JB	Junction-to-board characterization parameter		10.0	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance		3.8	°C/W
R_θJP	Junction-to-pad thermal resistance⁽⁵⁾		3.58	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report (SPRA953).

(2) The package thermal resistance is calculated in accordance with JESD 51 and JEDEC 2S2P (high-K board).

(3) Connected to GND with 16 thermal vias (0.3-mm diameter).

(4) 4 × 4 vias on pad

(5) R_θJP (junction-to-pad) is used for the VQFN package, because the primary heat flow is from the junction to the GND pad of the VQFN package.

6.5 Electrical Characteristics: LVCMOS Input, at V_CC = 2.375 V to 3.6 V

at T_A = –40°C to +85°C and T_PCB ≤ 105°C (unless otherwise noted) ⁽¹⁾

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
f_IN	Input frequency				200	MHz
V_th	Input threshold voltage	External threshold voltage applied to complementary input	1.1		1.8	V
V_IH	Input high voltage		V_th + 0.1		V_CC	V
V_IL	Input low voltage		0		V_th – 0.1	V
I_IH	Input high current	V_CC= 3.6 V, V_IH = 3.6 V			40	μA
I_IL	Input low current	V_CC= 3.6 V, V_IL = 0 V			–40	μA
ΔV/ΔT	Input edge rate	20% to 80%	1.5			V/ns
I_CAP	Input capacitance			5		pF

(1) Figure 5 and Figure 6 show DC test setup.

6.6 Electrical Characteristics: Differential Input, at V_CC = 2.375 V to 3.6 V

at T_A = –40°C to +85°C and T_PCB ≤ 105°C (unless otherwise noted) ⁽¹⁾

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
f_IN	Input frequency	Clock input			2000	MHz
V_{IN, DIFF, PP}	Differential input peak-peak voltage	f_IN ≤ 1.5 GHz	0.1		1.5	V
V_{IN, DIFF, PP}	Differential input peak-peak voltage	1.5 GHz ≤ f_IN ≤ 2 GHz	0.2		1.5	V
V_ICM	Input common-mode level		1		V_CC – 0.3	V
I_IH	Input high current	V_CC= 3.6 V, V_IH = 3.6 V			40	μA
I_IL	Input low current	V_CC= 3.6 V, V_IL = 0 V			–40	μA
ΔV/ΔT	Input edge rate	20% to 80%	1.5			V/ns
I_CAP	Input capacitance			5		pF

(1) Figure 7 and Figure 8 show DC test setup. Figure 9 shows AC test setup.

6.7 Electrical Characteristics: LVPECL Output, at V_CC = 2.375 V to 2.625 V

at T_A = –40°C to +85°C and T_PCB ≤ 105°C (unless otherwise noted)⁽¹⁾

PARAMETER		TEST CONDITIONS	MIN	MAX	UNIT
V_OH	Output high voltage	T_A ≤ 85°C	V_CC – 1.26	V_CC – 0.9	V
V_OH	Output high voltage	T_PCB ≤105°C	V_CC – 1.26	V_CC – 0.83	V
V_OL	Output low voltage	T_A ≤ 85°C	V_CC – 1.7	V_CC – 1.3	V
V_OL	Output low voltage	T_PCB ≤105°C	V_CC – 1.7	V_CC – 1.25	V
V_{OUT, DIFF, PP}	Differential output peak-peak voltage	f_IN ≤ 2 GHz	0.5	1.35	V
V_{AC_REF}	Input bias voltage⁽²⁾	I_{AC_REF} = 2 mA	V_CC – 1.6	V_CC – 1.1	V
I_EE	Supply internal current	Outputs unterminated, T_A ≤ 85°C		92	mA
I_EE	Supply internal current	Outputs unterminated, T_PCB ≤105°C		93	mA
I_CC	Output and internal supply current	All outputs terminated, 50 Ω to V_CC – 2 T_A ≤ 85°C		477	mA
I_CC	Output and internal supply current	All outputs terminated, 50 Ω to V_CC – 2 T_PCB ≤105°C		526	mA

(1) Figure 10 and Figure 11 show DC and AC test setup.

(2) Internally generated bias voltage (V_{AC_REF}) is for 3.3-V operation only. TI recommends applying externally generated bias voltage for V_CC < 3 V.

6.8 Electrical Characteristics: LVPECL Output, at V_CC = 3 V to 3.6 V⁽¹⁾

at T_A = –40°C to +85°C (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	MAX	UNIT
V_OH	Output high voltage	T_A ≤ 85°C	V_CC – 1.26	V_CC – 0.9	V
V_OH	Output high voltage	T_PCB ≤105°C	V_CC – 1.26	V_CC – 0.85	V
V_OL	Output low voltage	T_A ≤ 85°C	V_CC – 1.7	V_CC – 1.3	V
V_OL	Output low voltage	T_PCB ≤105°C	V_CC – 1.7	V_CC – 1.3	V
V_{OUT, DIFF, PP}	Differential output peak-peak voltage	f_IN ≤ 2 GHz	0.65	1.35	V
V_{AC_REF}	Input bias voltage	I_{AC_REF} = 2 mA	V_CC – 1.6	V_CC – 1.1	V
I_EE	Supply internal current	Outputs unterminated, T_A ≤ 85°C		92	mA
I_EE	Supply internal current	Outputs unterminated, T_PCB ≤105°C		93	mA
I_CC	Output and internal supply current	All outputs terminated, 50 Ω to V_CC – 2 T_A ≤ 85°C		477	mA
I_CC	Output and internal supply current	All outputs terminated, 50 Ω to V_CC – 2 T_PCB ≤105°C		526	mA

(1) Figure 10 and Figure 11 show DC and AC test setup.

(2) 100-MHz Wenzel oscillator, Input slew rate = 0.9 V/ns (single-ended)

(3) 100-MHz Wenzel oscillator, Input slew rate = 3.4 V/ns (differential)

(4) 122.88-MHz Rohde & Schwarz SMA100A, Input slew rate = 3.7 V/ns (differential)

(5) 156.25-MHz Crystek CPRO33 oscillator, Input slew rate = 2.9 V/ns (differential)

(6) 312.5-MHz Rohde & Schwarz SMA100A, Input slew rate = 4 V/ns (differential)

6.9 Timing Requirements, at V_CC = 2.375 V to 2.625 V

Refer to Figure 1 and Figure 2.

			MIN	NOM	MAX	UNIT
t_PD	Propagation delay	V_{IN, DIFF, PP} = 0.1V			550	ps
t_PD	Propagation delay	V_{IN, DIFF, PP} = 0.3V			550	ps
t_SK,PP	Part-to-part skew				150	ps
t_{SK,O_WB}	Within bank output skew				20	ps
t_{SK,O_BB}	Bank-to-bank output skew	Both inputs have equal skew			25	ps
t_SK,P	Pulse skew (with 50% duty cycle input)	Crossing-point-to-crossing-point distortion, f_OUT = 100 MHz	–50		50	ps
t_RJIT	Random additive jitter (with 50% duty cycle input)	f_OUT = 100 MHz, V_IN,SE = V_CC, V_th = 1.25 V, 10 kHz to 20 MHz		0.124		ps, RMS
		f_OUT = 100 MHz, V_IN,SE = 0.9 V, V_th = 1.1 V, 10 kHz to 20 MHz		0.178		ps, RMS
		f_OUT = 2 GHz, V_IN,DIFF,PP = 0.2 V, V_ICM = 1 V, 10 kHz to 20 MHz		0.061		ps, RMS
		f_OUT = 100 MHz, V_IN,DIFF,PP = 0.15 V, V_ICM = 1 V, 10 kHz to 20 MHz		0.119		ps, RMS
		f_OUT = 100 MHz, V_IN,DIFF,PP = 1 V, V_ICM = 1 V, 10 kHz to 20 MHz		0.104		ps, RMS
		f_OUT,8 = 500 MHz, V_IN,DIFF,PP,0 = 0.15 V, V_{ICM, 0} = 1 V, f_{OUT, 7} = 62.5 MHz, V_IN,SE,1 = V_CC, V_{th, 1} = V_CC/2		–45.5		dBc
P_SPUR	Coupling on differential OUT6 from OUT5 in the frequency spectrum of f_{OUT, 8} ±(f_{OUT, 8}/2) with synchronous inputs	f_OUT,8 = 500 MHz, V_IN,DIFF,PP,0 = 0.15 V, V_{ICM, 0} = 1 V, f_{OUT, 7} = 62.5 MHz, V_IN,DIFF,PP,1 = 1 V, V_{ICM, 1} = 1 V		–47.9		dBc
		f_OUT,8 = 500 MHz, V_IN,DIFF,PP,0 = 0.15 V, V_{ICM, 0} = 1 V, f_{OUT, 7} = 15.625 MHz, V_IN,SE,1 = V_CC, V_{th, 1} = V_CC/2		–57.8
		f_OUT,8 = 500 MHz, V_IN,DIFF,PP,0 = 0.15 V, V_{ICM, 0} = 1 V, f_{OUT, 7} = 15.625 MHz, V_IN,DIFF,PP,1 = 1 V, V_{ICM, 1} = 1 V		–63.4
t_R/t_F	Output rise/fall time	20% to 80%			200	ps

6.10 Timing Requirements, at V_CC = 3 V to 3.6 V

Refer to Figure 1 and Figure 2.

			MIN	NOM	MAX	UNIT
t_PD	Propagation delay	V_{IN, DIFF, PP} = 0.1V			550	ps
t_PD	Propagation delay	V_{IN, DIFF, PP} = 0.3V			550	ps
t_SK,PP	Part-to-part skew				150	ps
t_{SK,O_WB}	Within bank output skew				20	ps
t_{SK,O_BB}	Bank-to-bank output skew	Both inputs have equal skew			25	ps
t_SK,P	Pulse skew (with 50% duty cycle input)	Crossing-point-to-crossing-point distortion, f_OUT = 100 MHz	–50		50	ps
t_RJIT	Random additive jitter (with 50% duty cycle input)	f_OUT = 100 MHz,⁽²⁾ V_IN,SE = V_CC, V_th = 1.65 V, 10 kHz to 20 MHz		0.121		ps, RMS
		f_OUT = 100 MHz,⁽²⁾ V_IN,SE = 0.9 V, V_th = 1.1 V, 10 kHz to 20 MHz		0.185		ps, RMS
		f_OUT = 2 GHz, V_IN,DIFF,PP = 0.2 V, V_ICM = 1 V, 10 kHz to 20 MHz		0.077		ps, RMS
		f_OUT = 100 MHz,⁽²⁾ V_IN,DIFF,PP = 0.15 V, V_ICM = 1 V, 10 kHz to 20 MHz		0.122		ps, RMS
		f_OUT = 100 MHz,⁽²⁾ V_IN,DIFF,PP = 1 V, V_ICM = 1 V, 10 kHz to 20 MHz		0.105		ps, RMS
		f_OUT,8 = 500 MHz, V_IN,DIFF,PP,0 = 0.15 V, V_{ICM, 0} = 1 V, f_{OUT, 7} = 62.5 MHz, V_IN,SE,1 = V_CC, V_{th, 1} = V_CC/2		–48.4		dBc
		f_OUT = 100 MHz⁽³⁾, Input AC coupled, V_ICM = V_{AC_REF}, 12 kHz to 20 MHz		0.068		ps, RMS
		f_OUT = 122.88 MHz⁽⁴⁾, Input AC coupled, V_ICM = V_{AC_REF}, 12 kHz to 20 MHz		0.056		ps, RMS
		f_OUT = 156.25 MHz⁽⁵⁾, Input AC coupled, V_ICM = V_{AC_REF}, 12 kHz to 20 MHz		0.047		ps, RMS
		f_OUT = 312.5 MHz⁽⁶⁾, Input AC coupled, V_ICM = V_{AC_REF}, 12 kHz to 20 MHz		0.026		ps, RMS
P_SPUR	Coupling on differential OUT6 from OUT5 in the frequency spectrum of f_{OUT, 8} ±(f_{OUT, 8}/2) with synchronous inputs	f_OUT,8 = 500 MHz, V_IN,DIFF,PP,0 = 0.15 V, V_{ICM, 0} = 1 V, f_{OUT, 7} = 62.5 MHz, V_IN,SIFF,PP,1 = 1 V, V_{ICM, 1} = 1 V		–52.6		dBc
		f_OUT,8 = 500 MHz, V_IN,DIFF,PP,0 = 0.15 V, V_{ICM, 0} = 1 V, f_{OUT, 7} = 15.625 MHz, V_IN,SE,1 = V_CC, V_{th, 1} = V_CC/2		–65.4
		f_OUT,8 = 500 MHz, V_IN,DIFF,PP,0 = 0.15 V, V_{ICM, 0} = 1 V, f_{OUT, 7} = 15.625 MHz, V_IN,DIFF,PP,1 = 1 V, V_{ICM, 1} = 1 V		–67.1
t_R/t_F	Output rise/fall time	20% to 80%			200	ps

Figure 1 shows the output voltage and rise/fall time. Output and part-to-part skew are shown in Figure 2.

Figure 1. Output Voltage and Rise/Fall Time

1. Output skew is calculated as the greater of the following: As the difference between the fastest and the slowest t_PLHn (n = 0, 1, 2....11), or as the difference between the fastest and the slowest t_PHLn (n = 0, 1, 2....11).

2. Part-to-part skew is calculated as the greater of the following: As the difference between the fastest and the slowest t_PLHn (n = 0, 1, 2....11) across multiple devices, or the difference between the fastest and the slowest t_PHLn (n = 0, 1, 2....11) across multiple devices.

Figure 2. Output and Part-to-Part Skew

6.11 Typical Characteristics

at T_A = –40°C to +85°C (unless otherwise noted)

CDCLVP2106 tc_fqcy_diff_vout_swing01_cas878.gif

Figure 3. Differential Output Peak-to-Peak Voltage vs Frequency

CDCLVP2106 tc_fqcy_diff_vout_swing02_cas878.gif

Figure 4. Differential Output Peak-to-Peak Voltage vs Frequency

7 Parameter Measurement Information

7.1 Test Configurations

Figure 5 through Figure 11 show how the device should be set up for a variety of test configurations.

CDCLVP2106 ai_test_lvcmos_dc_in_cas878.gif

Figure 5. DC-Coupled LVCMOS Input During Device Test

CDCLVP2106 ai_vth_var_lvcmos_in_cas878.gif

Figure 6. V_th Variation over LVCMOS Levels

CDCLVP2106 ai_test_lvpecl_dc_in_cas887.gif

Figure 7. DC-Coupled LVPECL Input During Device Test

CDCLVP2106 ai_test_lvds_dc_in_cas887.gif

Figure 8. DC-Coupled LVDS Input During Device Test

CDCLVP2106 ai_test_diff_ac_in_cas887.gif

Figure 9. AC-Coupled Differential Input to Device

CDCLVP2106 ai_test_lvpecl_dc_out_cas878.gif

Figure 10. LVPECL Output DC Configuration During Device Test

CDCLVP2106 ai_test_lvpecl_ac_out_cas878.gif

Figure 11. LVPECL Output AC Configuration During Device Test

8 Detailed Description

8.1 Overview

The CDCLVP2106 is an open emitter for LVPECL outputs. Therefore, proper biasing and termination are required to ensure correct operation of the device and to minimize signal integrity. The proper termination for LVPECL outputs is a 50 Ω to (V_CC – 2) V, but this direct-coupled (DC) voltage is not readily available on PCB. Therefore, a Thevenin equivalent circuit is worked out for the LVPECL termination in both DC- and AC-coupled configurations. These configurations are shown in Figure 12 (a and b) for V_CC=2.5 V and Figure 13 (a and b) for V_CC=3.3 V, respectively. TI recommends placing all resistive components close to either the driver end or the receiver end. If the supply voltage for the driver and receiver is different, AC coupling is required.

8.2 Functional Block Diagram

8.3 Feature Description

The CDCLVP2106 is a low-additive jitter universal to LVPECL fan-out buffer with two independent inputs. The small package, low output skew, and low-additive jitter make for a flexible device in demanding applications.

8.4 Device Functional Modes

The two independent inputs of the CDCLVP2106 distribute the input clock to six outputs each. Unused inputs and outputs can be left floating to reduce overall component cost. Both AC- and DC coupling schemes can be used with the CDCLVP2106 to provide greater system flexibility.

8.4.1 LVPECL Output Termination

The CDCLVP2106 is an open emitter for LVPECL outputs. Therefore, proper biasing and termination are required to ensure correct operation of the device and to minimize signal integrity. The proper termination for LVPECL outputs is a 50 Ω to (V_CC –2) V, but this DC voltage is not readily available on PCB. Therefore, a Thevenin equivalent circuit is worked out for the LVPECL termination in both direct-coupled (DC) and AC-coupled configurations. These configurations are shown in Figure 12 a and b for V_CC = 2.5 V and Figure 13 a and b for V_CC = 3.3 V, respectively. TI recommends placing all resistive components close to either the driver end or the receiver end. If the supply voltage for the driver and receiver is different, AC coupling is required.

CDCLVP2106 ai_lvpecl_dc_ac_out_25_cas887.gif

Figure 12. LVPECL Output DC and AC Termination for V_CC = 2.5 V

CDCLVP2106 ai_lvpecl_dc_ac_out_33_cas887.gif

Figure 13. LVPECL Output DC and AC Termination for V_CC = 3.3 V

8.4.2 Input Termination

The CDCLVP2106 inputs can be interfaced with LVPECL, LVDS, or LVCMOS drivers. Figure 14 shows how to DC-couple an LVCMOS input to the CDCLVP2106. The series resistance (R_S) should be placed close to the LVCMOS driver; its value is calculated as the difference between the transmission line impedance and the driver output impedance.

Figure 14. DC-Coupled LVCMOS Input to CDCLVP2106

Figure 15 shows how to DC couple LVDS inputs to the CDCLVP2106. Figure 16 and Figure 17 describe the method of DC coupling LVPECL inputs to the CDCLVP2106 for V_CC = 2.5 V and V_CC = 3.3 V, respectively.

Figure 15. DC-Coupled LVDS Inputs to CDCLVP2106

CDCLVP2106 ai_dc_lvpecl_in_25v_cas887.gif

Figure 16. DC-Coupled LVPECL Inputs to CDCLVP2106 (V_CC = 2.5 V)

CDCLVP2106 ai_dc_lvpecl_in_33v_cas887.gif

Figure 17. DC-Coupled LVPECL Inputs to CDCLVP2106 (V_CC = 3.3 V)

Figure 18 and Figure 19 show the technique of AC coupling differential inputs to the CDCLVP2106 for
V_CC = 2.5 V and V_CC = 3.3 V, respectively. TI recommends placing all resistive components close to either the driver end or the receiver end. If the supply voltages of the driver and receiver are different, AC coupling is required.

Figure 18. AC-Coupled Differential Inputs to CDCLVP2106 (V_CC = 2.5 V)

Figure 19. AC-Coupled Differential Inputs to CDCLVP2106 (V_CC = 3.3 V)

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

The CDCLVP2106 is a low additive jitter LVPECL fan-out buffer that can generate two copies each of two independent LVPECL, LVDS, or LVCMOS inputs. The CDCLVP2106 can accept reference clock frequencies up to 2 GHz while providing low output skew.

9.2 Typical Application

Figure 20 shows a fan-out buffer for line-card application.

Figure 20. CDCLVP2106 Typical Application

9.2.1 Design Requirements

The CDCLVP2106 shown in Figure 20 is configured to be able to select two inputs: a 156.25-MHz LVPECL clock from the backplane, or a secondary 156.25-MHz LVCMOS 2.5-V oscillator. Either signal can be then fanned out to desired devices, as shown.

The configuration example is driving 4 LVPECL receivers in a line-card application with the following properties:

The PHY device has internal AC coupling and appropriate termination and biasing. The CDCLVP2106 must be provided with 86-Ω emitter resistors near the driver for proper operation.
The ASIC is capable of DC coupling with a 2.5-V LVPECL driver such as the CDCLVP2106. This ASIC features internal termination so no additional components are needed.
The FPGA requires external AC coupling but has internal termination. Again, 86-Ω emitter resistors are placed near the CDCLVP2106, and 0.1 μF are placed to provide AC coupling. Similarly, the CPU is internally terminated and requires external AC coupling capacitors.

9.2.2 Detailed Design Procedure

Refer to Input Termination for proper input terminations, dependent on single ended or differential inputs.

Refer to LVPECL Output Termination for output termination schemes depending on the receiver application.

Unused outputs can be left floating.

In Figure 20, the PHY, ASIC, and FPGA/CPU require different schemes. Power supply filtering and bypassing is critical for low-noise applications.

See Power Supply Recommendations for recommended filtering techniques. A reference layout is provided on the CDCLVP2106 Evaluation Module, Low Additive Phase Noise Clock Buffer Evaluation Board User's Guide (SCAU037).

9.2.3 Application Curves

Reference signal is low-noise Crystek XO CPRO33.156.25
32 fs, RMS	10 kHz to 20 MHz

Figure 21. CDCLVP21xx Reference Phase Noise


57 fs, RMS	10 kHz to 20 MHz

Figure 22. CDCLVP21xx Output Phase Noise

The low additive noise of the CDCLVP2106 can be shown in this line-card application. The low-noise, 156.25-MHz XO with 32-fs, RMS jitter drives the CDCLVP2106, resulting in 57 fs, RMS when integrated from 10 kHz to 20 MHz. The resultant additive jitter is a low 47 fs, RMS for this configuration.