The CDCLVP2106 is a highly versatile, low additive jitter buffer that can generate 12 copies of LVPECL clock outputs from two LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. Each buffer block consists of one input that feeds two LVPECL outputs. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 20 ps, making the device a perfect choice for use in demanding applications.
The CDCLVP2106 clock buffer distributes two clock inputs (IN0, IN1) to 12 pairs of differential LVPECL clock outputs (OUT0, OUT11) with minimum skew for clock distribution. Each buffer block consists of one input that feeds two LVPECL clock outputs. The inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.
The CDCLVP2106 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (VAC_REF) should be applied to the unused negative input pin. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended.
The CDCLVP2106 is characterized for operation from –40°C to +85°C and is available in a 6-mm × 6-mm, VQFN-40 package.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
CDCLVP2106 | VQFN (40) | 6.00 mm × 6.00 mm |
Changes from A Revision (August 2011) to B Revision
Changes from * Revision (September 2009) to A Revision
MIN | MAX | UNIT | ||
---|---|---|---|---|
VCC | Supply voltage(2) | –0.5 | 4.6 | V |
VIN | Input voltage(3) | –0.5 | VCC + 0.5 | V |
VOUT | Output voltage(3) | –0.5 | VCC + 0.5 | V |
IIN | Input current | 20 | mA | |
IOUT | Output current | 50 | mA | |
TA | Specified free-air temperature (no airflow) | –40 | 85 | °C |
TJ | Maximum junction temperature | 125 | °C | |
Tstg | Storage temperature | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | 2000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | 1000 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
VCC | Supply voltage | 2.375 | 2.5/3.3 | 3.60 | V |
TA | Ambient temperature | –40 | 85 | °C | |
TPCB | PCB temperature (measured at thermal pad) | 105 | °C |
THERMAL METRIC(1)(2)(3) | CDCLVP2106 | UNIT | ||
---|---|---|---|---|
(RHA) VQFN | ||||
40 PINS | ||||
RθJA | Junction-to-ambient thermal resistance(4) | 0 LFM | 34.7 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 23.7 | °C/W | |
RθJB | Junction-to-board thermal resistance | 10.1 | °C/W | |
ψJT | Junction-to-top characterization parameter | 0.5 | °C/W | |
ψJB | Junction-to-board characterization parameter | 10.0 | °C/W | |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 3.8 | °C/W | |
RθJP | Junction-to-pad thermal resistance(5) | 3.58 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
fIN | Input frequency | Clock input | 2000 | MHz | ||
VIN, DIFF, PP | Differential input peak-peak voltage | fIN ≤ 1.5 GHz | 0.1 | 1.5 | V | |
1.5 GHz ≤ fIN ≤ 2 GHz | 0.2 | 1.5 | V | |||
VICM | Input common-mode level | 1 | VCC – 0.3 | V | ||
IIH | Input high current | VCC = 3.6 V, VIH = 3.6 V | 40 | μA | ||
IIL | Input low current | VCC = 3.6 V, VIL = 0 V | –40 | μA | ||
ΔV/ΔT | Input edge rate | 20% to 80% | 1.5 | V/ns | ||
ICAP | Input capacitance | 5 | pF |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
VOH | Output high voltage | TA ≤ 85°C | VCC – 1.26 | VCC – 0.9 | V | ||
TPCB ≤105°C | VCC – 1.26 | VCC – 0.83 | |||||
VOL | Output low voltage | TA ≤ 85°C | VCC – 1.7 | VCC – 1.3 | V | ||
TPCB ≤105°C | VCC – 1.7 | VCC – 1.25 | |||||
VOUT, DIFF, PP | Differential output peak-peak voltage | fIN ≤ 2 GHz | 0.5 | 1.35 | V | ||
VAC_REF | Input bias voltage(2) | IAC_REF = 2 mA | VCC – 1.6 | VCC – 1.1 | V | ||
IEE | Supply internal current | Outputs unterminated, TA ≤ 85°C |
92 | mA | |||
Outputs unterminated, TPCB ≤105°C |
93 | ||||||
ICC | Output and internal supply current | All outputs terminated, 50 Ω to VCC – 2 TA ≤ 85°C |
477 | mA | |||
All outputs terminated, 50 Ω to VCC – 2 TPCB ≤105°C |
526 |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
tPD | Propagation delay | VIN, DIFF, PP = 0.1V | 550 | ps | ||
VIN, DIFF, PP = 0.3V | 550 | |||||
tSK,PP | Part-to-part skew | 150 | ps | |||
tSK,O_WB | Within bank output skew | 20 | ps | |||
tSK,O_BB | Bank-to-bank output skew | Both inputs have equal skew | 25 | ps | ||
tSK,P | Pulse skew (with 50% duty cycle input) | Crossing-point-to-crossing-point distortion, fOUT = 100 MHz | –50 | 50 | ps | |
tRJIT | Random additive jitter (with 50% duty cycle input) | fOUT = 100 MHz, VIN,SE = VCC, Vth = 1.25 V, 10 kHz to 20 MHz |
0.124 | ps, RMS | ||
fOUT = 100 MHz, VIN,SE = 0.9 V, Vth = 1.1 V, 10 kHz to 20 MHz |
0.178 | ps, RMS | ||||
fOUT = 2 GHz, VIN,DIFF,PP = 0.2 V, VICM = 1 V, 10 kHz to 20 MHz |
0.061 | ps, RMS | ||||
fOUT = 100 MHz, VIN,DIFF,PP = 0.15 V, VICM = 1 V, 10 kHz to 20 MHz |
0.119 | ps, RMS | ||||
fOUT = 100 MHz, VIN,DIFF,PP = 1 V, VICM = 1 V, 10 kHz to 20 MHz |
0.104 | ps, RMS | ||||
fOUT,8 = 500 MHz, VIN,DIFF,PP,0 = 0.15 V, VICM, 0 = 1 V, fOUT, 7 = 62.5 MHz, VIN,SE,1 = VCC, Vth, 1 = VCC/2 |
–45.5 | dBc | ||||
PSPUR | Coupling on differential OUT6 from OUT5 in the frequency spectrum of fOUT, 8 ±(fOUT, 8/2) with synchronous inputs |
fOUT,8 = 500 MHz, VIN,DIFF,PP,0 = 0.15 V, VICM, 0 = 1 V, fOUT, 7 = 62.5 MHz, VIN,DIFF,PP,1 = 1 V, VICM, 1 = 1 V |
–47.9 | dBc | ||
fOUT,8 = 500 MHz, VIN,DIFF,PP,0 = 0.15 V, VICM, 0 = 1 V, fOUT, 7 = 15.625 MHz, VIN,SE,1 = VCC, Vth, 1 = VCC/2 |
–57.8 | |||||
fOUT,8 = 500 MHz, VIN,DIFF,PP,0 = 0.15 V, VICM, 0 = 1 V, fOUT, 7 = 15.625 MHz, VIN,DIFF,PP,1 = 1 V, VICM, 1 = 1 V |
–63.4 | |||||
tR/tF | Output rise/fall time | 20% to 80% | 200 | ps |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
tPD | Propagation delay | VIN, DIFF, PP = 0.1V | 550 | ps | ||
VIN, DIFF, PP = 0.3V | 550 | |||||
tSK,PP | Part-to-part skew | 150 | ps | |||
tSK,O_WB | Within bank output skew | 20 | ps | |||
tSK,O_BB | Bank-to-bank output skew | Both inputs have equal skew | 25 | ps | ||
tSK,P | Pulse skew (with 50% duty cycle input) | Crossing-point-to-crossing-point distortion, fOUT = 100 MHz | –50 | 50 | ps | |
tRJIT | Random additive jitter (with 50% duty cycle input) | fOUT = 100 MHz,(2) VIN,SE = VCC, Vth = 1.65 V, 10 kHz to 20 MHz |
0.121 | ps, RMS | ||
fOUT = 100 MHz,(2) VIN,SE = 0.9 V, Vth = 1.1 V, 10 kHz to 20 MHz |
0.185 | ps, RMS | ||||
fOUT = 2 GHz, VIN,DIFF,PP = 0.2 V, VICM = 1 V, 10 kHz to 20 MHz |
0.077 | ps, RMS | ||||
fOUT = 100 MHz,(2) VIN,DIFF,PP = 0.15 V, VICM = 1 V, 10 kHz to 20 MHz |
0.122 | ps, RMS | ||||
fOUT = 100 MHz,(2) VIN,DIFF,PP = 1 V, VICM = 1 V, 10 kHz to 20 MHz |
0.105 | ps, RMS | ||||
fOUT,8 = 500 MHz, VIN,DIFF,PP,0 = 0.15 V, VICM, 0 = 1 V, fOUT, 7 = 62.5 MHz, VIN,SE,1 = VCC, Vth, 1 = VCC/2 |
–48.4 | dBc | ||||
fOUT = 100 MHz(3), Input AC coupled, VICM = VAC_REF, 12 kHz to 20 MHz |
0.068 | ps, RMS | ||||
fOUT = 122.88 MHz(4), Input AC coupled, VICM = VAC_REF, 12 kHz to 20 MHz |
0.056 | ps, RMS | ||||
fOUT = 156.25 MHz(5), Input AC coupled, VICM = VAC_REF, 12 kHz to 20 MHz |
0.047 | ps, RMS | ||||
fOUT = 312.5 MHz(6), Input AC coupled, VICM = VAC_REF, 12 kHz to 20 MHz |
0.026 | ps, RMS | ||||
PSPUR | Coupling on differential OUT6 from OUT5 in the frequency spectrum of fOUT, 8 ±(fOUT, 8/2) with synchronous inputs |
fOUT,8 = 500 MHz, VIN,DIFF,PP,0 = 0.15 V, VICM, 0 = 1 V, fOUT, 7 = 62.5 MHz, VIN,SIFF,PP,1 = 1 V, VICM, 1 = 1 V |
–52.6 | dBc | ||
fOUT,8 = 500 MHz, VIN,DIFF,PP,0 = 0.15 V, VICM, 0 = 1 V, fOUT, 7 = 15.625 MHz, VIN,SE,1 = VCC, Vth, 1 = VCC/2 |
–65.4 | |||||
fOUT,8 = 500 MHz, VIN,DIFF,PP,0 = 0.15 V, VICM, 0 = 1 V, fOUT, 7 = 15.625 MHz, VIN,DIFF,PP,1 = 1 V, VICM, 1 = 1 V |
–67.1 | |||||
tR/tF | Output rise/fall time | 20% to 80% | 200 | ps |
Figure 1 shows the output voltage and rise/fall time. Output and part-to-part skew are shown in Figure 2.
Figure 5 through Figure 11 show how the device should be set up for a variety of test configurations.
The CDCLVP2106 is an open emitter for LVPECL outputs. Therefore, proper biasing and termination are required to ensure correct operation of the device and to minimize signal integrity. The proper termination for LVPECL outputs is a 50 Ω to (VCC – 2) V, but this direct-coupled (DC) voltage is not readily available on PCB. Therefore, a Thevenin equivalent circuit is worked out for the LVPECL termination in both DC- and AC-coupled configurations. These configurations are shown in Figure 12 (a and b) for VCC=2.5 V and Figure 13 (a and b) for VCC=3.3 V, respectively. TI recommends placing all resistive components close to either the driver end or the receiver end. If the supply voltage for the driver and receiver is different, AC coupling is required.
The CDCLVP2106 is a low-additive jitter universal to LVPECL fan-out buffer with two independent inputs. The small package, low output skew, and low-additive jitter make for a flexible device in demanding applications.
The two independent inputs of the CDCLVP2106 distribute the input clock to six outputs each. Unused inputs and outputs can be left floating to reduce overall component cost. Both AC- and DC coupling schemes can be used with the CDCLVP2106 to provide greater system flexibility.
The CDCLVP2106 is an open emitter for LVPECL outputs. Therefore, proper biasing and termination are required to ensure correct operation of the device and to minimize signal integrity. The proper termination for LVPECL outputs is a 50 Ω to (VCC –2) V, but this DC voltage is not readily available on PCB. Therefore, a Thevenin equivalent circuit is worked out for the LVPECL termination in both direct-coupled (DC) and AC-coupled configurations. These configurations are shown in Figure 12 a and b for VCC = 2.5 V and Figure 13 a and b for VCC = 3.3 V, respectively. TI recommends placing all resistive components close to either the driver end or the receiver end. If the supply voltage for the driver and receiver is different, AC coupling is required.
The CDCLVP2106 inputs can be interfaced with LVPECL, LVDS, or LVCMOS drivers. Figure 14 shows how to DC-couple an LVCMOS input to the CDCLVP2106. The series resistance (RS) should be placed close to the LVCMOS driver; its value is calculated as the difference between the transmission line impedance and the driver output impedance.
Figure 15 shows how to DC couple LVDS inputs to the CDCLVP2106. Figure 16 and Figure 17 describe the method of DC coupling LVPECL inputs to the CDCLVP2106 for VCC = 2.5 V and VCC = 3.3 V, respectively.
Figure 18 and Figure 19 show the technique of AC coupling differential inputs to the CDCLVP2106 for
VCC = 2.5 V and VCC = 3.3 V, respectively. TI recommends placing all resistive components close to either the driver end or the receiver end. If the supply voltages of the driver and receiver are different, AC coupling is required.