The UCC28070A incorporates two identical and independent transconductance-type current-error amplifiers (one for each phase) with which to control the shaping of the PFC input current waveform. The current-error amplifier (CA) forms the heart of the embedded current control loop of the boost PFC preregulator, and is compensated for loop stability using familiar principles [7, 8]. The output of the CA for phase-A is CAOA, and that for phase-B is CAOB. Because the design considerations are the same for both, they are collectively referred to as CAOx, where x is A or B.

In a boost PFC preregulator, the current control loop comprises the boost power plant stage, the current sensing circuitry, the wave-shape reference, the PWM stage, and the CA with compensation components. The CA compares the average boost inductor current sensed with the wave-shape reference from the multiplier stage and generates an output current proportional to the difference.

This CA output current flows through the impedance of the compensation network generating an output voltage, V_CAO, which is then compared with a periodic voltage ramp to generate the PWM signal necessary to achieve PFC.

For frequencies above boost LC resonance and below f_PWM, the small-signal model of the boost stage, which includes current sensing, can be simplified to:

where:

• L_B = mid-value boost inductance
• R_S = CT sense resistor
• N_CT = CT turns ratio
• V_OUT = average output voltage of the PFC converter
• ∆V_RMP = 4V_pk-pk amplitude of the PWM voltage ramp
• k_SYNC = ramp reduction factor due to external synchronization frequency: k_SYNC = (15000 / R_RT(kΩ)) / f_SYNC, where R_RT(kΩ) is from Equation 8. When external synchronization is not used, k_SYNC = 1.
• s = Laplace complex variable

An R_ZC-C_ZC network is introduced on CAOx to obtain high gain for the low-frequency content of the inductor current signal, but reduced flat gain above the zero frequency out to f_PWM to attenuate the high-frequency switching ripple content of the signal (thus averaging it).

The switching ripple voltage on the CAOx outputs must be attenuated to less than 1/10 of the ΔV_RMP amplitude so as to be considered negligible ripple.

Thus, CAOx gain at f_PWM is:

where:

• ∆I_LB is the maximum peak-to-peak ripple current in the boost inductor
• g_mc is the transconductance of the CA, 100μS

The current-loop cross-over frequency is then found by equating the open-loop gain to 1 and solving for f_CXO:

C_ZC is then determined by setting f_ZC = f_CXO = 1 / (2π × R_ZC × C_ZC) and solving for C_ZC. At f_ZC = f_CXO, a phase margin of 45° is obtained at f_CXO. Greater phase margin may be had by placing f_ZC < f_CXO (increase C_ZC).

An additional high-frequency pole is generally added at f_PWM or f_PWM/2 to further attenuate ripple and noise at f_PWM and higher. This is done by adding a lower-value capacitor, C_PC, across the R_ZCC_ZCnetwork.

The procedure above is valid for fixed-value inductors.