8.3.1 Principles of Operation

The UCC28063 contains the control circuits for two parallel-connected boost pulse-width modulated (PWM) power converters. The boost PWM power converters ramp current in the boost inductors for a time period proportional to the voltage on the error amplifier output. Each power converter then turns off the power MOSFET until current in the boost inductor decays to zero, as sensed on the zero current detection inputs (ZCDA and ZCDB). Once the inductor is demagnetized, the power converter starts another cycle. This on/off cycling produces a triangle wave of current, with peak current set by the on-time and instantaneous power mains input voltage, V_IN(t), as shown in Equation 1.

Equation 1.

The average line current is exactly equal to half of the peak line current, as shown in Equation 2.

Equation 2.

With T_ON and L being essentially constant during an AC-line period, the resulting triangular current waveform during each switching cycle will have an average value proportional to the instantaneous value of the rectified AC-line voltage. This architecture results in a resistive input impedance characteristic at the line frequency and a near-unity power factor.

8.3.2 Natural Interleaving

Under normal operating conditions, the UCC28063 regulates the relative phasing of the channel A and channel B inductor currents to be very close to 180°. This greatly reduces the switching-frequency ripple currents seen at the line-filter and output capacitors, compared to the ripple current of each individual converter. This design allows a reduction in the size and cost of input and output filtering. The phase-control function differentially modulates the on-times of the A and B channels based on their phase and frequency relationship. The Natural Interleaving method allows the converter to achieve 180° phase-shift and transition-mode operation for both phases without tight requirements on boost inductor tolerance.

Ideally, the best current-sharing is achieved when both inductors are exactly the same value. Typically the inductances are not the same, so the current-sharing of the A and B channels is proportional to the inductor tolerance. Also, switching delays and resonances of each channel typically differ slightly, and the controller allows some necessary phase-error deviation from 180° to maintain equal switching frequencies. Optimal phase balance occurs if the individual power stages and the on-times are well matched. Mismatches in inductor values do not affect the phase relationship.

8.3.3 On-Time Control, Maximum Frequency Limiting, and Restart Timer

Gate-drive on-time varies proportionately with the error-amplifier output voltage by a factor called K_T (in units of μs/V), as shown in Equation 3.

Equation 3.

Where:

• V_COMP is the output voltage of the error amplifier and 125 mV is a modulator offset voltage.

The maximum output of the error amplifier is limited to 4.95 V. This value, minus the 125-mV modulator offset, limits maximum on-time as determined by Equation 4.

Equation 4.

This on-time limit sets the maximum power that can be delivered by the converter at a given input voltage.

At lower power, one boost channel (phase) may be turned off to achieve efficiency benefits (see Phase Management section, below). To provide a smooth transition between two-phase and single-phase operation, K_T increases by a factor of two in single-phase mode:

Equation 5.

The maximum switching frequency of each phase is limited by minimum-period timers. If inductor current decays to zero before the minimum-period timer elapses, the next turn-on will be delayed, resulting in discontinuous phase current.

A restart timer ensures starting under all circumstances by restarting both phases if the ZCD input of either phase has not transitioned from high-to-low within approximately 200 µs. To prevent the circuit from operating in continuous conduction mode (CCM), the restart timer does not trigger turn-on until both phase-currents return to zero.

The on-time factors (K_T, K_TS) and the minimum switching period, T_(MIN), are proportional to the time-setting resistor R_TSET (the resistor from the TSET pin to ground), and these factors can be calculated by Equation 5, Equation 6 and Equation 7:

Equation 6.

Equation 7.

The proper value of R_TSET will result in the clamped maximum on-time, T_ON(max), required by the converter operating at the minimum input line voltage and maximum load.

8.3.4 Distortion Reduction

Due to the parasitic resonance between the drain-source capacitance of the switching MOSFET and the boost inductor, conventional transition-mode PFC circuits may not be able to absorb power from the input line when the input voltage is near zero. This limitation increases total harmonic distortion as a result of ac-line current waveform distortion in the form of flat spots. To help reduce line-current distortion, the UCC28063 increases switching MOSFET on-time when the input voltage is near 0 V to improve the power absorption capability and compensate for this effect.

Figure 12 in the Typical Characteristics section shows the increase in on-time with respect to VINAC voltage. Excessive filtering of the VINAC signal will nullify this function.

8.3.5 Zero-Current Detection and Valley Switching

In transition-mode PFC circuits, the MOSFET turns on when the boost inductor current reaches zero. Because of the resonance between the boost inductor and the parasitic capacitance at the MOSFET drain node, part of the energy stored in the MOSFET junction capacitor can be recovered, reducing switching losses. Furthermore, when the rectified input voltage is less than half of the output voltage, all the energy stored in the MOSFET junction capacitor can be recovered and zero-voltage switching (ZVS) can be realized. By adding an appropriate delay, the MOSFET can be turned on at the valley of its resonating drain voltage (valley-switching). In this way, the energy recovery can be maximized and switching loss is minimized.

The optimal time delay is generally derived empirically, but a good starting point is a value equal to 25% of the resonant period of the drain circuit. The delay can be realized by a simple RC filter, as shown in Figure 25, but the delay time increases slightly as the input voltage nears the output voltage. Because the ZCD pin is internally clamped, a more accurate delay can also be realized by using the circuit shown in Figure 26.

Figure 25. Simple RC Delay Circuit

Figure 26. More Accurate Time Delay Circuit

8.3.6 Phase Management and Light-Load Operation

Under light-load conditions, switching losses may dominate over conduction losses and efficiency may be improved if one phase (channel) is turned off. At a certain power level, the reduction of switching losses is greater than the increase in conduction losses. Turning off one phase at light load is especially valuable for meeting light-load efficiency standards. This is one of the major benefits of interleaved PFC and it is especially valuable for meeting 80+ design requirements.

The PHB input can be used to force the UCC28063 to operate in single-phase mode. When PHB is driven below 0.8 V, channel B will stop switching and channel A on-time will automatically double to compensate. The device will resume dual-phase mode when PHB is raised above 1.0 V. For customized phase management, an external circuit can detect the conditions for switching to single-phase operation and drive PHB accordingly. To operate continuously in two-phase mode (normal mode) when phase management is not desired, simply connect PHB to VREF.

As load current decreases, the error amplifier commands less ac-line input current by lowering COMP voltage. In applications where the ac-line is limited to the low-voltage range only, it may be advantageous to connect PHB directly to COMP to allow automatic selection of single-phase operation without additional external circuitry.

8.3.7 External Disable

The UCC28063 can be externally disabled by purposefully grounding the VSENSE pin with an open-drain or open-collector driver. When disabled, the device supply current drops significantly and COMP is actively pulled low. This disable method forces the device into standby mode and minimizes its power consumption. This is particularly useful when standby power is a key design aspect. When VSENSE is released, the device enters soft-start mode.

8.3.8 Improved Error Amplifier

The voltage-error amplifier is a transconductance amplifier. Voltage-loop compensation is connected from the error amplifier output, COMP, to analog ground, AGND. The recommended Type-II compensation network is shown in Figure 27. For loop-stability purposes, the compensation network values are calculated based on small-signal perturbations of the output voltage using the nominal transconductance (gain) of 55 μS.

Figure 27. Transconductance Error Amplifier With Typical Compensation Network

To improve the transient response to large perturbations, the error amplifier gain increases by a factor of ~5X when the error amp input deviates more than ±5% from the nominal regulation voltage, VSENSEreg. This increase allows faster charging and discharging of the compensation components following sudden load-current increases or decreases (also refer to Figure 5 in the Typical Characteristics).

Basic voltage-error amplifier transconductance curve showing small-signal and large-signal gain sections, with maximum current limitations.

Figure 28. Basic Voltage-Error Amplifier Transconductance Curve

8.3.9 Soft Start

Soft-start is a process for boosting the output voltage of the PFC converter from the peak of the ac-line input voltage to the desired regulation voltage under controlled conditions. Instead of a dedicated soft-start pin, the UCC28063 uses the voltage error amplifier as a controlled current source to increase the PWM duty-cycle by way of increasing the COMP voltage. To avoid excessive start-up time-delay when the ac-line voltage is low, a higher current is applied until VSENSE exceeds 3 V at which point the current is reduced to minimize the tendency for excess COMP voltage at no-load start-up.

The PWM gradually ramps from zero on-time to normal on-time as the compensation capacitor from COMP to AGND charges from zero to near its final value. This process implements a soft-start, with timing set by the output current of the error amplifier and the value of the compensation capacitors. In the event of a HVSEN FailSafe OVP, brownout, external-disable, UVLO fault, or other protection faults, COMP is actively discharged and the UCC28063 will soft-start after the triggering event is cleared. Even if a fault event happens very briefly, the fault is latched into the soft-start state and soft-start is delayed until COMP is fully discharged to 20 mV and the fault is cleared. See Figure 29 for details on the COMP current. See Figure 30 which illustrates an example of typical system behavior during soft-start.

Expanded COMP output current curve including voltage-error amplifier transconductance and modifications applicable to soft-start and overvoltage conditions.

Figure 29. Expanded Comp Output Current Curve

Figure 30. Soft-Start Timing With Illustrative System Behavior

8.3.10 Brownout Protection

As the power line RMS voltage decreases, RMS input current must increase to maintain a constant output voltage for a specific load. Brownout protection helps prevent excess system thermal stress (due to the higher RMS input current) from exceeding a safe operating level. Power-line voltage is sensed at VINAC. When the VINAC fails to exceed the brownout threshold for the brownout filter time, a brownout condition is detected and both gate drive outputs are turned off. During brownout, COMP is actively pulled low and a soft-start condition is initiated. Hysteresis is built into the brownout detection circuit to avoid chatter around the threshold. When VINAC rises above the brownout threshold, the power stage soft-starts as COMP rises with controlled current.

The brownout detection threshold and its hysteresis are set by the voltage-divider ratio and resistor values. Brownout protection is based on VINAC peak voltage; the threshold and hysteresis are also based on the line peak voltage. Major hysteresis is provided by a 2-μA current-sink (I_BOHYS) enabled whenever VINAC falls below the brownout detection threshold. Minor hysteresis is also present in the form of a 50-mV offset (V_BOHYS) between the VINAC detection and clear thresholds. The peak VINAC voltage can be easily translated into an RMS value. Example resistor values for the voltage divider are 8.61 MΩ ±1% from the rectified input voltage to VINAC and 133 kΩ ±1% from VINAC to ground. These resistors set the typical thresholds for RMS line voltages, as shown in Table 1.

Equation 8 and Equation 9 can be used to calculate the VINAC divider-resistor values based on desired brownout detection and brownout clear voltage levels. V_{AC_OK} is the desired RMS turn-on voltage, V_{AC_BO} is the desired RMS turn-off brownout voltage, and V_LOSS is total series voltage drop due to wiring, EMI-filter, and bridge-rectifier impedances at V_{AC_BO}. V_BODET, V_BOHYS and I_BOHYS are found in the data-tables of this datasheet.

Equation 8.

Equation 9.

Once standard values for the VINAC divider-resistors R_A and R_B are selected, the actual turn-on and brownout threshold RMS voltages for the ac-line can be back-calculated with Equation 10 and Equation 11:

Equation 10.

Equation 11.

An example of the timing for the brownout function is illustrated in Figure 31.

For a quick estimation of the turn-on and brownout voltages, simplify the foregoing equations by setting the V_LOSS and V_BOHYS terms to zero.

8.3.11 Dropout Detection

It is often the case that the ac-line voltage momentarily drops to zero or nearly zero, due to transient abnormal events affecting the local ac power distribution network. Referred to as ac-line dropouts (or sometimes as line-dips) the duration of such events usually extends to only 1 or 2 line cycles. During a dropout, the down-stream power conversion stages depend on sufficient energy storage in the PFC output capacitance, which is sized to provide the ride-through energy for a specified hold-up time. Typically while the PFC output voltage is falling, the voltage-loop error amplifier output rises in an attempt to maintain regulation. As a consequence, excess duty-cycle is commanded when the ac-line voltage returns and high peak current surges may saturate the boost inductors with possible overstress and audible noise.

The UCC28063 incorporates a dropout detection feature which suspends the action of the error amplifier for the duration of the dropout. If the VINAC voltage falls below 0.35 V for longer than 5 ms, a dropout condition is detected and the error amplifier output is turned off. In addition, a 4-μA pull-down current is applied to COMP to gently discharge the compensation network capacitors. In this way, when the ac-line voltage returns, the COMP voltage (and corresponding duty-cycle setting) remains very near or even slightly below the level it was before the dropout occurred. Current surges due to excess duty-cycle, and their undesired attendant effects, are avoided. The dropout condition is cancelled and the error amplifier resumes normal operation when VINAC rises above 0.71 V.

Based on the VINAC divider-resistor values calculated for brownout in the previous section, the input RMS voltage thresholds for dropout detection V_{AC_DO} and dropout clearing V_{DO_CLR} can be determined using Equation 12 and Equation 13, below.

Equation 12.

Equation 13.

Avoid excessive filtering of the VINAC signal, or dropout detection may be delayed or defeated. An RC time-constant of ≤ 100-μs should provide good performance. An example of the timing for the dropout function is illustrated in Figure 32.

Figure 31. AC-Line Brownout Timing With Illustrative System Behavior

Figure 32. AC-Line Dropout Timing With Illustrative System Behavior

8.3.12 VREF

VREF is an output which supplies a well-regulated reference voltage to circuits within the device as well as serving as a limited source for external circuits. This output must be bypassed to GND with a low-impedance 0.1-μF or larger capacitor placed as close to the VREF and GND pins as possible. Current draw by external circuits should not exceed a few milli-amperes and should not be pulsing.

The VREF output is disabled under the following conditions: when VCC is in UVLO, or when VSENSE is below the Enable threshold. This output can only source current and is unable to accept current into the pin.

8.3.13 VCC

VCC is usually connected to a bias supply of between 13 V and 21 V. To minimize switching ripple voltage on VCC, it should be by-passed with a low-impedance capacitor as close to the VCC and GND pins as possible. The capacitance should be sized to adequately decouple the peak currents due to gate-drive switching at the highest operating frequency. When powered from a poorly-regulated low-impedance supply, an external zener diode is recommended to prevent excessive current into VCC.

The undervoltage-lockout (UVLO) condition is when VCC voltage has not yet reached the turn-on threshold or has fallen below the turn-off threshold, having already been turned on. While in UVLO, the VREF output and most circuits within the device are disabled and VCC current falls significantly below the normal operating level. The same situation applies when VSENSE is below its Enable threshold. This helps minimize power loss during pre-powerup and standby conditions.

8.3.14 Control of Downstream Converter

In the UCC28063, the PWMCNTL pin can be used to coordinate the PFC stage with a downstream converter. Through the HVSEN pin, the PFC output voltage is monitored. A 12-μA current source (I_{HV_HYS}) is enabled as long as the output voltage remains below a programmed threshold. When the output voltage exceeds that threshold, PWMCNTL pin is pulled to ground internally and can be used to enable a downstream converter. At the same time the current source is disabled, providing hysteresis for a lower threshold at which the downstream converter should be turned off. The enable/disable hysteresis is adjusted through the HVSEN voltage-divider ratio and resistor values. The HVSEN pin is also used for the FailSafe over-voltage protection (OVP). When designing the voltage divider, make sure this FailSafe OVP level is set above normal VSENSE OVP levels.

Because there are two thresholds associated with the HVSEN input detected through a single resistor divider, the PWMCNTL turn-off voltage, V_PWM-OFF, is linked to the FailSafe OVP voltage, V_{FLSF_OV}, as shown by Equation 14:

Equation 14.

Choosing either one first arbitrarily determines the other, so a trade-off may be necessary. The PWMCNTL turn-on voltage, V_PWM-ON, is programmed by choosing the upper divider resistor value in consideration with the HVSEN hysteresis current, as shown in Equation 15 and Equation 16. The lower divider resistor is then calculated as shown in Equation 17.

Equation 15.

Equation 16.

Equation 17.

8.3.15 System Level Protections

8.3.15.9 Fault Logic Diagram

Figure 33 depicts the fault-handling logic involving VSENSE, COMP, and several internal states.

Figure 33. Fault Logic With VSENSE Detections and Error Amplifier Control