SGLS121D December   2002  – June 2020 UCC2800-Q1 , UCC2801-Q1 , UCC2802-Q1 , UCC2803-Q1 , UCC2804-Q1 , UCC2805-Q1

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Simplified Application Diagram
  4. Revision History
  5. Description (continued)
  6. Device Comparison Table
  7. Pin Configuration and Functions
    1.     Pin Functions
  8. Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Detailed Pin Description
        1. 9.3.1.1 COMP
        2. 9.3.1.2 FB
        3. 9.3.1.3 CS
        4. 9.3.1.4 RC
        5. 9.3.1.5 GND
        6. 9.3.1.6 OUT
        7. 9.3.1.7 VCC
        8. 9.3.1.8 Pin 8 (REF)
      2. 9.3.2  Undervoltage Lockout (UVLO)
      3. 9.3.3  Self-Biasing, Active Low Output
      4. 9.3.4  Reference Voltage
      5. 9.3.5  Oscillator
      6. 9.3.6  Synchronization
      7. 9.3.7  PWM Generator
      8. 9.3.8  Minimum Off-Time Setting (Dead-Time Control)
      9. 9.3.9  Leading Edge Blanking
      10. 9.3.10 Minimum Pulse Width
      11. 9.3.11 Current Limiting
      12. 9.3.12 Overcurrent Protection and Full Cycle Restart
      13. 9.3.13 Soft Start
      14. 9.3.14 Slope Compensation
    4. 9.4 Device Functional Modes
      1. 9.4.1 Normal Operation
      2. 9.4.2 UVLO Mode
      3. 9.4.3 Soft Start Mode
      4. 9.4.4 Fault Mode
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Current Sensing Network
        2. 10.2.2.2 Gate Drive Resistor
        3. 10.2.2.3 Vref Capacitor
        4. 10.2.2.4 RTCT
        5. 10.2.2.5 Start-Up Circuit
        6. 10.2.2.6 Voltage Feedback Compensation
          1. 10.2.2.6.1 Power Stage Gain, Zeroes, and Poles
          2. 10.2.2.6.2 Compensation Loop
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Community Resources
    2. 13.2 Trademarks
    3. 13.3 Related Links
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • D|8
散热焊盘机械数据 (封装 | 引脚)
订购信息

Power Stage Gain, Zeroes, and Poles

The first step in compensating a fixed frequency flyback is to verify if the converter is continuous conduction mode (CCM) or discontinuous conduction mode (DCM).  If the primary inductance, LP, is greater than the inductance for DCM, CCM boundary mode operation, called the critical inductance, or LPcrit, then the converter operates in CCM calculated with Equation 20.

Equation 20. UCC2800-Q1 UCC2801-Q1 UCC2802-Q1 UCC2803-Q1 UCC2804-Q1 UCC2805-Q1 Equation_19_SLUS270.gif

For the entire input voltage range, the selected inductor has value larger than the critical inductor. Therefore, the converter operates in CCM and the compensation loop requires design based on CCM flyback equations.

The current-to-voltage conversion is done externally with the ground-referenced current sense resistor, RCS, and the internal resistor divider sets up the internal current sense gain, ACS = 1.65.  The IC technology allows the tight control of the resistor divider ratio, regardless of the actual resistor value variations.

The DC open-loop gain, GO, of the fixed-frequency voltage control loop of a peak current mode control CCM flyback converter shown in Figure 33 is approximated by first using the output load, ROUT, the primary to secondary turns ratio, NPS, the maximum duty cycle, D, calculated in Equation 21.

Equation 21. UCC2800-Q1 UCC2801-Q1 UCC2802-Q1 UCC2803-Q1 UCC2804-Q1 UCC2805-Q1 Equation_20_SLUS270.gif

In Equation 21, D is calculated with Equation 22, τL is calculated with Equation 23, and M is calculated with Equation 24.

Equation 22. UCC2800-Q1 UCC2801-Q1 UCC2802-Q1 UCC2803-Q1 UCC2804-Q1 UCC2805-Q1 Equation_21_SLUS270.gif
Equation 23. UCC2800-Q1 UCC2801-Q1 UCC2802-Q1 UCC2803-Q1 UCC2804-Q1 UCC2805-Q1 Equation_22_SLUS270.gif
Equation 24. UCC2800-Q1 UCC2801-Q1 UCC2802-Q1 UCC2803-Q1 UCC2804-Q1 UCC2805-Q1 Equation_23_SLUS270.gif

For this design, a converter with an output voltage VOUT of 12 V, and 48 W relates to an output load, ROUT, equal to 3 Ω at full load.

At minimum input voltage of 75 V DC, the duty cycle reaches it maximum value of 0.615. The current sense resistance, RCS, is 0.75 Ω, and a primary to secondary turns-ratio, NPS is 10. The open-loop gain calculates to 14.95 dB.

A CCM flyback has two zeroes that are of interest. The ESR and the output capacitance contribute a left-half plane zero to the power stage, and the frequency of this zero, fESRz, are calculated with Equation 25.

Equation 25. UCC2800-Q1 UCC2801-Q1 UCC2802-Q1 UCC2803-Q1 UCC2804-Q1 UCC2805-Q1 Equation_24_SLUS270E.gif

The fESRz zero for a capacitance bank of three 680-µF capacitors for a total output capacitance of 2040 µF and a total ESR of 13 mΩ is placed at 6 kHz.

CCM flyback converters have a zero in the right-half plane, RHP, in their transfer function. RHP zero has the same 20 dB/decade rising gain magnitude with increasing frequency just like a left-half plane zero, but it adds phase lag instead of lead. This phase lag tends to limit the overall loop bandwidth. The frequency location, fRHPz in Equation 26, is a function of the output load, the duty cycle, the primary inductance, LP, and the primary to secondary side turns ratio, NPS.

Equation 26. UCC2800-Q1 UCC2801-Q1 UCC2802-Q1 UCC2803-Q1 UCC2804-Q1 UCC2805-Q1 Equation_27_SLUS270.gif

Right half plane zero frequency increases with higher input voltage and lighter load. Generally, the design requires consideration of the worst case of the lowest right half plane zero frequency and the converter must be compensated at the minimum input and maximum load condition. With a primary inductance of 1.5 mH, at 75-V DC input, the RHP zero frequency, fRHPz, is equal to 7.65 kHz at maximum duty cycle, full load.

The power stage has one dominate pole, ωP1, which is in the region of interest, placed at a lower frequency, fP1, which is related to the duty cycle, D, the output load, and the output capacitance. There is also a double pole placed at half the switching frequency of the converter, fP2 calculated with Equation 27 and Equation 28.

Equation 27. UCC2800-Q1 UCC2801-Q1 UCC2802-Q1 UCC2803-Q1 UCC2804-Q1 UCC2805-Q1 Equation_28_SLUS270.gif
Equation 28. UCC2800-Q1 UCC2801-Q1 UCC2802-Q1 UCC2803-Q1 UCC2804-Q1 UCC2805-Q1 Equation_31_SLUS270.gif

Slope compensation is the large signal sub-harmonic instability that can occur with duty cycles that extends beyond 50%. The subharmonic oscillation increases the output voltage ripple and sometimes it even limits the power handling capability of the converter.

The target of slope compensation is to achieve idea quality coefficient, Qp , at half of the switching frequency to be 1. The Qp is calculated with Equation 29.

Equation 29. UCC2800-Q1 UCC2801-Q1 UCC2802-Q1 UCC2803-Q1 UCC2804-Q1 UCC2805-Q1 Equation_32_SLUS270.gif

In Equation 29, D is the primary side switch duty cycle and MC is the slope compensation factor, which is defined with Equation 30.

Equation 30. UCC2800-Q1 UCC2801-Q1 UCC2802-Q1 UCC2803-Q1 UCC2804-Q1 UCC2805-Q1 Equation_32a_SLUS270.gif

In Equation 30, Se is the compensation ramp slope and the Sn is the inductor rise slope. The optimal goal of the slope compensation is to achieve QP equal to 1, which mean MC  must be 2.128 when D reaches it maximum value of 0.615.

The inductor rise slop on CS pin is calculated with Equation 31.

Equation 31. UCC2800-Q1 UCC2801-Q1 UCC2802-Q1 UCC2803-Q1 UCC2804-Q1 UCC2805-Q1 EqSn.gif

The compensation slope is calculated with Equation 32.

Equation 32. UCC2800-Q1 UCC2801-Q1 UCC2802-Q1 UCC2803-Q1 UCC2804-Q1 UCC2805-Q1 Equation_32c_SLUS270.gif

The compensation slope is added into the system through RRAMP and RCSF. The CRAMP is selected to approximate high frequency short circuit. Choose CRAMP as 10 nF as the starting point, and make adjustments if required. The RRAMP and RCSF forms a voltage divider from the RC pin ramp voltage and inject the slope compensation into CS pin. Choose RRAMP much larger than the RT resistor  so that it won’t affect much the frequency setting.  In this design, RRAMP is selected as 24.9 kΩ. The RC pin ramp slope is calculated with Equation 33.

Equation 33. UCC2800-Q1 UCC2801-Q1 UCC2802-Q1 UCC2803-Q1 UCC2804-Q1 UCC2805-Q1 Equation_32d_SLUS270.gif

To achieve 46.3 mV/µs compensation slope, RCSF resistor is calculated with Equation 34.

Equation 34. UCC2800-Q1 UCC2801-Q1 UCC2802-Q1 UCC2803-Q1 UCC2804-Q1 UCC2805-Q1 Equation_32e_SLUS270.gif

The power stage open-loop gain and phase can be plotted as a function of frequency. The total gain, as a function of frequency can be characterized with Equation 35.

Equation 35. UCC2800-Q1 UCC2801-Q1 UCC2802-Q1 UCC2803-Q1 UCC2804-Q1 UCC2805-Q1 Equation_33_SLUS270.gif

The bode is plotted accordingly (see Figure 34 and Figure 35).

UCC2800-Q1 UCC2801-Q1 UCC2802-Q1 UCC2803-Q1 UCC2804-Q1 UCC2805-Q1 Figure_35A_SLUS270E.gifFigure 34. Converter Open Loop Bode Plot - Gain
UCC2800-Q1 UCC2801-Q1 UCC2802-Q1 UCC2803-Q1 UCC2804-Q1 UCC2805-Q1 Figure_35B_SLUS270E.gifFigure 35. Converter Open Loop Bode Plot - Phase