SGLS121D December   2002  – June 2020 UCC2800-Q1 , UCC2801-Q1 , UCC2802-Q1 , UCC2803-Q1 , UCC2804-Q1 , UCC2805-Q1

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Simplified Application Diagram
  4. Revision History
  5. Description (continued)
  6. Device Comparison Table
  7. Pin Configuration and Functions
    1.     Pin Functions
  8. Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Detailed Pin Description
        1. 9.3.1.1 COMP
        2. 9.3.1.2 FB
        3. 9.3.1.3 CS
        4. 9.3.1.4 RC
        5. 9.3.1.5 GND
        6. 9.3.1.6 OUT
        7. 9.3.1.7 VCC
        8. 9.3.1.8 Pin 8 (REF)
      2. 9.3.2  Undervoltage Lockout (UVLO)
      3. 9.3.3  Self-Biasing, Active Low Output
      4. 9.3.4  Reference Voltage
      5. 9.3.5  Oscillator
      6. 9.3.6  Synchronization
      7. 9.3.7  PWM Generator
      8. 9.3.8  Minimum Off-Time Setting (Dead-Time Control)
      9. 9.3.9  Leading Edge Blanking
      10. 9.3.10 Minimum Pulse Width
      11. 9.3.11 Current Limiting
      12. 9.3.12 Overcurrent Protection and Full Cycle Restart
      13. 9.3.13 Soft Start
      14. 9.3.14 Slope Compensation
    4. 9.4 Device Functional Modes
      1. 9.4.1 Normal Operation
      2. 9.4.2 UVLO Mode
      3. 9.4.3 Soft Start Mode
      4. 9.4.4 Fault Mode
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Current Sensing Network
        2. 10.2.2.2 Gate Drive Resistor
        3. 10.2.2.3 Vref Capacitor
        4. 10.2.2.4 RTCT
        5. 10.2.2.5 Start-Up Circuit
        6. 10.2.2.6 Voltage Feedback Compensation
          1. 10.2.2.6.1 Power Stage Gain, Zeroes, and Poles
          2. 10.2.2.6.2 Compensation Loop
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Community Resources
    2. 13.2 Trademarks
    3. 13.3 Related Links
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • D|8
散热焊盘机械数据 (封装 | 引脚)
订购信息

Pin Configuration and Functions

UCC280x-Q1 D Package
8-Pin SOIC
Top View

Pin Functions

PIN I/O DESCRIPTION
NAME SOIC
COMP 1 O

COMP is the output of the error amplifier and the input of the PWM comparator.

The error amplifier in the UCC280x-Q1 family is a true, low output impedance, 2-MHz operational amplifier. As such, the COMP terminal can both source and sink current. However, the error amplifier is internally current-limited, so the user can command zero duty cycle by externally forcing COMP to GND.

The UCC280x-Q1 family features built-in full-cycle soft start. Soft start is implemented as a clamp on the maximum COMP voltage.

CS 3 I

CS is the input to the current sense comparators. The UCC280x-Q1 family has two different current sense comparators: the PWM comparator and an overcurrent comparator.

The UCC280x-Q1 family contains digital current sense filtering, which disconnects the CS terminal from the current sense comparator during the 100-ns interval immediately following the rising edge of the OUT pin. This digital filtering, also called leading-edge blanking, means that in most applications, no analog filtering (RC filter) is required on CS. Compared to an external RC filter technique, the leading-edge blanking provides a smaller effective CS to OUT propagation delay. Note, however, that the minimum non-zero On-time of the OUT signal is directly affected by the leading-edge-blanking and the CS to OUT propagation delay.

The overcurrent comparator is only intended for fault sensing, and exceeding the overcurrent threshold causes a soft-start cycle.

FB 2 I FB is the inverting input of the error amplifier. For best stability, keep FB lead length as short as possible and FB stray capacitance as small as possible.
GND 5 GND is reference ground and power ground for all functions on this part.
NC No connection pins
OUT 6 O

OUT is the output of a high-current power driver capable of driving the gate of a power MOSFET with peak currents exceeding ±750 mA. OUT is actively held low when VCC is below the UVLO threshold.

The high-current power driver consists of FET output devices, which can switch all of the way to GND and all of the way to VCC. The output stage also provides a very low impedance to overshoot and undershoot. This means that in many cases, external schottky clamp diodes are not required.

PWR GND Power ground of the IC
RC 4 I

RC is the oscillator timing pin. For fixed frequency operation, set timing capacitor charging current by connecting a resistor from REF to RC. Set frequency by connecting a timing capacitor from RC to GND. For best performance, keep the timing capacitor lead to GND as short and direct as possible. If possible, use separate ground traces for the timing capacitor and all other functions.

The frequency of oscillation can be estimated with the following equations:

Equation 1. UCC2800-Q1 UCC2801-Q1 UCC2802-Q1 UCC2803-Q1 UCC2804-Q1 UCC2805-Q1 Equation_01_SLUS270E.gif
Equation 2. UCC2800-Q1 UCC2801-Q1 UCC2802-Q1 UCC2803-Q1 UCC2804-Q1 UCC2805-Q1 Equation_02_SLUS270E.gif

where

  • frequency is in Hz
  • resistance is in Ω
  • capacitance is in farads

The recommended range of timing resistors is between 10 k and 200 k, and timing capacitor is 100 pF to 1000 pF. Never use a timing resistor less than 10 k.

REF 8 O

REF is the voltage reference for the error amplifier, and also for many other functions on the IC. REF is also used as the logic power supply for high-speed switching logic on the IC.

When VCC is greater than 1 V and less than the UVLO threshold, REF is pulled to ground through a 5-kΩ resistor. This means that REF can be used as a logic output indicating power system status. It is important for reference stability that REF is bypassed to GND with a ceramic capacitor as close to the pin as possible. An electrolytic capacitor may also be used in addition to the ceramic capacitor. A minimum of 0.1-μF ceramic is required. Additional REF bypassing is required for external loads greater than 2.5 mA on the reference.

To prevent noise problems with high speed switching transients, bypass REF to ground with a ceramic capacitor very close to the IC package.

VCC 7 I

VCC is the power input connection for this device. In normal operation, VCC is powered through a current limiting resistor. Although quiescent VCC current is very low, total supply current is higher depending on OUT current. Total VCC current is the sum of quiescent VCC current and the average OUT current. Knowing the operating frequency and the MOSFET gate charge (Qg), average OUT current can be calculated from:

Equation 3. UCC2800-Q1 UCC2801-Q1 UCC2802-Q1 UCC2803-Q1 UCC2804-Q1 UCC2805-Q1 Equation_03_SLUS270E.gif

To prevent noise problems, bypass VCC to GND with a ceramic capacitor as close to the VCC pin as possible. An electrolytic capacitor may also be used in addition to the ceramic capacitor. There must be a minimum of 1 µF in parallel with a 0.1-µF ceramic capacitor from VCC to ground placed close to the device.