ZHCS501F November   2011  – December 2014 UCC27210 , UCC27211

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 说明 （续）
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Switching Characteristics: Propagation Delays
    7. 7.7  Switching Characteristics: Delay Matching
    8. 7.8  Switching Characteristics: Output Rise and Fall Time
    9. 7.9  Switching Characteristics: Miscellaneous
    10. 7.10 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Stages
      2. 8.3.2 Undervoltage Lockout (UVLO)
      3. 8.3.3 Level Shift
      4. 8.3.4 Boot Diode
      5. 8.3.5 Output Stages
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Input Threshold Type
        2. 9.2.2.2 VDD Bias Supply Voltage
        3. 9.2.2.3 Peak Source and Sink Currents
        4. 9.2.2.4 Propagation Delay
        5. 9.2.2.5 Power Dissipation
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12器件和文档支持
    1. 12.1 文档支持
      1. 12.1.1 相关文档　
    2. 12.2 相关链接
    3. 12.3 商标
    4. 12.4 静电放电警告
    5. 12.5 Glossary
  13. 13机械、封装和可订购信息

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • D|8
  • DRM|8
  • DPR|10
  • DDA|8
散热焊盘机械数据 (封装 | 引脚)
订购信息

7 Specifications

7.1 Absolute Maximum Ratings(1)

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Supply voltage range, VDD(2), VHB - VHS –0.3 20 V
Input voltages on LI and HI, VLI, VHI –10 20
Output voltage on LO, VLO DC –0.3 VDD + 0.3
Repetitive pulse <100 ns(3) –2 VDD + 0.3
Output voltage on HO, VHO DC VHS – 0.3 VHB + 0.3
Repetitive pulse <100 ns(3) VHS – 2 VHB + 0.3
Voltage on HS, VHS DC –1 115
Repetitive pulse <100 ns(3) –(24 V-VDD) 115
Voltage on HB, VHB –0.3 120
Operating virtual junction temperature, TJ –40 150 °C
Lead temperature (soldering, 10 sec.) 300
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to VSS unless otherwise noted. Currents are positive into, negative out of the specified terminal.
(3) Verified at bench characterization. VDD is the value used in an application design.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

all voltages are with respect to VSS; currents are positive into and negative out of the specified terminal. –40°C < TJ = TA < 140°C (unless otherwise noted)
MIN TYP MAX UNIT
Supply voltage range, VDD, VHB-VHS 8 12 17 V
Voltage on HS, VHS –1 105
Voltage on HS, VHS (repetitive pulse <100 ns) –(24V-VDD) 110
Voltage on HB, VHB VHS +8,
VDD –1		 VHS +17,
115
Voltage slew rate on HS 50 V/ns
Operating junction temperature range –40 140 °C

7.4 Thermal Information

THERMAL METRIC UCC27210, UCC27211 UNIT
D DDA DRM DPR
8 PINS 8 PINS 8 PINS 10 PINS
θJA Junction-to-ambient thermal resistance(1) 111.8 37.7 33.9 36.8 °C/W
θJCtop Junction-to-case (top) thermal resistance(2) 56.9 47.2 33.2 36.0
θJB Junction-to-board thermal resistance(3) 53.0 9.6 11.4 14.0
ψJT Junction-to-top characterization parameter(4) 7.8 2.8 0.4 0.3
ψJB Junction-to-board characterization parameter(5) 52.3 9.4 11.7 14.2
θJCbot Junction-to-case (bottom) thermal resistance(6) n/a 3.6 2.3 3.4
(1) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a.
(2) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8.
(4) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
(5) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer

7.5 Electrical Characteristics

VDD = VHB = 12 V, VHS = VSS = 0 V, no load on LO or HO, TA = TJ = –40°C to 140°C, (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENTS
IDD VDD quiescent current V(LI) = V(HI) = 0 V 0.05 0.085 0.17 mA
IDDO VDD operating current UCC27210 f = 500 kHz, CLOAD = 0 2.6 5.2
UCC27211 2.5 5.2
IHB Boot voltage quiescent current V(LI) = V(HI) = 0 V 0.015 0.065 0.1
IHBO Boot voltage operating current f = 500 kHz, CLOAD = 0 2.5 5.0
IHBS HB to VSS quiescent current V(HS) = V(HB) = 115 V 0.0005 1.0 µA
IHBSO HB to VSS operating current f = 500 kHz, CLOAD = 0 0.07 1.2 mA
INPUT
VHIT Input voltage threshold UCC27210 4.2 5.0 5.8 V
UCC27210 (DDA only) 4.2 5.0 5.9
VLIT Input voltage threshold UCC27210 2.4 3.2 4.0
UCC27210 (DDA only) 2.4 3.2 4.0
VIHYS Input voltage hysteresis UCC27210 1.8
RIN Input pulldown resistance 102 kΩ
VHIT Input voltage threshold UCC27211 1.9 2.3 2.7 V
UCC27211 (DDA only) 1.9 2.3 2.8
VLIT Input voltage threshold UCC27211 1.3 1.6 1.9
UCC27211 (DDA only) 1.3 1.6 2.1
VIHYS Input voltage hysteresis UCC27211 700 mV
RIN Input pulldown resistance 68 kΩ
UNDERVOLTAGE LOCKOUT (UVLO)
VDDR VDD turnon threshold 6.2 7.0 7.8 V
DDA only 5.8 7.0 8.1
VDDHYS Hysteresis 0.5
VHBR VHB turnon threshold 5.6 6.7 7.9
DDA only 5.3 6.7 8.0
VHBHYS Hysteresis 1.1
BOOTSTRAP DIODE
VF Low-current forward voltage IVDD-HB = 100 µA 0.65 0.8 V
VFI High-current forward voltage IVDD-HB = 100 mA 0.85 0.95
RD Dynamic resistance, ΔVF/ΔI IVDD-HB = 100 mA and 80 mA 0.3 0.5 0.85 Ω
LO GATE DRIVER
VLOL Low-level output voltage ILO = 100 mA 0.05 0.09 0.19 V
VLOH High level output voltage ILO = -100 mA, VLOH = VDD - VLO 0.1 0.16 0.29
Peak pull-up current(3) VLO = 0 V 3.7 A
Peak pull-down current(3) VLO = 12 V 4.5
HO GATE DRIVER
VHOL Low-level output voltage IHO = 100 mA 0.05 0.09 0.19 V
VHOH High-level output voltage IHO = -100 mA, VHOH = VHB - VHO 0.1 0.16 0.29
Peak pull-up current(3) VHO = 0 V 3.7 A
Peak pull-down current(3) VHO = 12 V 4.5
(1) Typical values for TA = 25°C.
(2) IF: Forward current applied to bootstrap diode, IREV: Reverse current applied to bootstrap diode.
(3) Ensured by design.

7.6 Switching Characteristics: Propagation Delays

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TDLFF VLI falling to VLO falling UCC27210, CLOAD = 0 15 21 37 ns
TDHFF VHI falling to VHO falling 15 21 37
TDLRR VLI rising to VLO rising 15 24 46
TDHRR VHI rising to VHO rising 15 24 46
TDLFF VLI falling to VLO falling UCC27211, CLOAD = 0 10 17 30
TDHFF VHI falling to VHO falling 10 17 30
TDLRR VLI rising to VLO rising 10 18 40
TDHRR VHI rising to VHO rising 10 18 40

7.7 Switching Characteristics: Delay Matching

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TMON From HO OFF to LO ON UCC27210 TJ = 25°C 3 11 ns
TJ = –40°C to 140°C 3 14
TMOFF From LO OFF to HO ON TJ = 25°C 3 11 ns
TJ = –40°C to 140°C 3 14
TMON From HO OFF to LO ON UCC27211 TJ = 25°C 2 9.5 ns
TJ = –40°C to 140°C 2 14
TMOFF From LO OFF to HO ON TJ = 25°C 2 9.5 ns
TJ = –40°C to 140°C 2 14

7.8 Switching Characteristics: Output Rise and Fall Time

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tR LO rise time CLOAD = 1000 pF, from 10% to 90% 7.2 ns
tR HO rise time 7.2
tF LO fall time CLOAD = 1000 pF, from 90% to 10% 5.5
tF HO fall time 5.5
tR LO, HO CLOAD = 0.1 µF, (3 V to 9 V) 0.36 0.6 µs
tF LO, HO CLOAD = 0.1 µF, (9 V to 3 V) 0.15 0.4

7.9 Switching Characteristics: Miscellaneous

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Minimum input pulse width that changes the output 50 ns
Bootstrap diode turnoff time(3)(2) IF = 20 mA, IREV = 0.5 A(1) 20
UCC27210 UCC27211 fig22_lus746.gif Figure 1. Timing Diagrams

7.10 Typical Characteristics

UCC27210 UCC27211 0001_IDD_IHB_vs_VDD_VHB_lusat7.png
Figure 2. Quiescent Current vs Supply Voltage
UCC27210 UCC27211 0003_UCC27211_IDDO_vs_Freq_lusat7.png
Figure 4. UCC27211 IDD Operating Current vs Frequency
UCC27210 UCC27211 0005_VIHL_vs_VDD_lusat7.png
Figure 6. UCC27210 and UCC27211 Input Threshold vs Supply Voltage
UCC27210 UCC27211 0007_VOH_vs_Temp_lusat7.png
Figure 8. LO and HO High Level Output Voltage vs Temperature
UCC27210 UCC27211 0009_UVLO_vs_Temp_lusat7.png
Figure 10. Undervoltage Lockout Threshold vs Temperature
UCC27210 UCC27211 0011_UCC27210_Delay_vs_Temp_lusat7.png
Figure 12. UCC27210 Propagation Delays vs Temperature
UCC27210 UCC27211 0013_UCC27210_Delay_vs_VDD_lusat7.png
Figure 14. UCC27210 Propagation Delays vs Supply Voltage
UCC27210 UCC27211 0015_DelayMatching_vs_Temp_lusat7.png
Figure 16. Delay Matching vs Temperature
UCC27210 UCC27211 0017_DiodeCurrent_vs_DiodeVoltage_lusat7.png
Figure 18. Diode Current vs Diode Voltage
UCC27210 UCC27211 0002_UCC27210_IDDO_vs_Freq_lusat7.png
Figure 3. UCC27210 IDD Operating Current vs Frequency
UCC27210 UCC27211 0004_IHBO_vs_Freq_lusat7.png
Figure 5. Boot Voltage Operating Current vs Frequency (HB to HS)
UCC27210 UCC27211 0006_VIHL_vs_Temp_lusat7.png
Figure 7. UCC27210 and UCC27211 Input Thresholds vs Temperature
UCC27210 UCC27211 0008_VOL_vs_Temp_lusat7.png
Figure 9. LO and HO Low Level Output Voltage vs Temperature
UCC27210 UCC27211 0010_UVLO_HYS_vs_Temp_lusat7.png
Figure 11. Undervoltage Lockout Threshold Hysteresis vs Temperature
UCC27210 UCC27211 0012_UCC27211_Delay_vs_Temp_lusat7.png
Figure 13. UCC27211 Propagation Delays vs Temperature
UCC27210 UCC27211 0014_UCC27211_Delay_vs_VDD_lusat7.png
Figure 15. UCC27211 Propagation Delays vs Supply Voltage
UCC27210 UCC27211 out_new_lusay7.png
Figure 17. Output Current vs Output Voltage