Table 2. UCC27201 Design Requirements

8.2.2.1 Switching the MOSFETs

Achieving optimum drive performance at high frequency efficiently requires special attention to layout and minimizing parasitic inductances. Take care at the driver die and package level as well as the PCB layout to reduce parasitic inductances as much as possible. Figure 23 shows the main parasitic inductance elements and current flow paths during the turn ON and OFF of the MOSFET by charging and discharging its CGS capacitance.

Figure 23. MOSFET Drive Paths and Circuit Parasitics

The I_SOURCE current charges the C_GS gate capacitor and the I_SINK current discharges it. The rise and fall time of the voltage across the gate to source defines how quickly the MOSFET can be switched. Based on actual measurements, the analytical curves in Figure 24 and Figure 25 indicate the output voltage and current of the drivers during the discharge of the load capacitor. Figure 24 shows voltage and current as a function of time. Figure 25 indicates the relationship of voltage and current during fast switching. These figures demonstrate the actual switching process and limitations due to parasitic inductances.

Figure 24. Turnoff Voltage and Current vs Time

Figure 25. Turnoff Voltage and Current Switching Diagram

Turning off the MOSFET must be achieved as fast as possible to minimize switching losses. For this reason the UCC2720x drivers are designed for high peak currents and low output resistance. The sink capability is specified as 0.18 V at 100-mA DC current implying 1.8-Ω R_DS(on). With 12-V drive voltage, no parasitic inductance and a linear resistance, one would expect initial sink current amplitude of 6.7 A for both high-side and low-side drivers. Assuming a pure R-C discharge circuit of the gate capacitor, one would expect the voltage and current waveforms to be exponential. Due to the parasitic inductances and non-linear resistance of the driver MOSFET’S, the actual waveforms have some ringing and the peak-sink current of the drivers is approximately 3.3 A as shown in Figure 19. The overall parasitic inductance of the drive circuit is estimated at 4 nH. The internal parasitic inductance of the 8-pin SOIC package is estimated to be 2 nH including bond wires and leads. The 8-pin VSON package reduces the internal parasitic inductances by more than 50%.

Actual measured waveforms are shown in Figure 26 and Figure 27. As shown, the typical rise time of 8 ns and fall time of 7 ns is conservatively rated.

Figure 26. V_LO and V_HO Rise Time, 1-nF Load, 5 ns/Div

Figure 27. V_LO and V_HO Fall Time, 1-nF Load, 5-ns/Div

8.2.2.2 Dynamic Switching of the MOSFETs

The true behavior of MOSFETS presents a dynamic capacitive load primarily at the gate to source threshold voltage. Using the turnoff case as the example, when the gate to source threshold voltage is reached the drain voltage starts rising, the drain to gate parasitic capacitance couples charge into the gate resulting in the turnoff plateau. The relatively low threshold voltages of many MOSFETS and the increased charge that has to be removed (Miller charge) makes good driver performance necessary for efficient switching. An open-loop half bridge power converter was used to evaluate performance in actual applications. The schematic of the half-bridge converter is shown in Figure 22. The turnoff waveforms of the UCC27200 driving two MOSFETs in parallel is shown in Figure 28 and Figure 29.

Figure 28. V_LO Fall Time in Half-Bridge Converter

Figure 29. V_HO Fall Time in Half-Bridge Converter

8.2.2.2.1 Delay Matching and Narrow Pulse Widths

The total delays encountered in the PWM, driver and power stage must be considered for a number of reasons, primarily delay in current limit response. Also to be considered are differences in delays between the drivers which can lead to various concerns depending on the topology. The sync-buck topology switching requires careful selection of dead time between the high-side and low-side switches to avoid cross conduction and excessive body diode conduction. Bridge topologies can be affected by a resulting V/s imbalance on the transformer if there is imbalance in the high and low-side pulse widths in a steady state condition.

Narrow pulse width performance is an important consideration when transient and short circuit conditions are encountered. Although there may be relatively long steady state PWM output-driver-MOSFET signals, very narrow pulses may be encountered in soft start, large load transients, and short-circuit conditions.

The UCC2720x driver family offers excellent performance regarding high and low-side driver delay matching and narrow pulse width performance. The delay matching waveforms are shown in Figure 30 and Figure 31. The UCC2720x driver narrow pulse performance is shown in Figure 32 and Figure 33.

Figure 30. V_LO and V_HO Rising Edge Delay Matching

Figure 32. 20-ns Input Pulse Delay Matching

Figure 31. V_LO and V_HO Falling Edge Delay Matching

Figure 33. 10-ns Input Pulse Delay Matching

8.2.2.3 Boot Diode Performance

The UCC2720x family of drivers incorporates the bootstrap diode necessary to generate the high-side bias internally. The characteristics of this diode are important to achieve efficient, reliable operation. The DC characteristics to consider are V_F and dynamic resistance. A low V_F and high dynamic resistance results in a high forward voltage during charging of the bootstrap capacitor. The UCC2720x has a boot diode rated at 0.65-V V_F and dynamic resistance of 0.6 Ω for reliable charge transfer to the bootstrap capacitor. The dynamic characteristics to consider are diode recovery time and stored charge. Diode recovery times that are specified with no conditions can be misleading. Diode recovery times at no forward current (I_F) can be noticeably less than with forward current applied. The UCC2720x boot diode recovery is specified at 20 ns at I_F = 20 mA, I_REV = 0.5 A. At 0-mA I_F the reverse recovery time is 15 ns.

Another less obvious consideration is how the stored charge of the diode is affected by applied voltage. On every switching transition when the HS node transitions from low to high, charge is removed from the boot capacitor to charge the capacitance of the reverse biased diode. This is a portion of the driver power losses and reduces the voltage on the HB capacitor. At higher applied voltages, the stored charge of the UCC2720x PN diode is often less than a comparable Schottky diode.