ZHCSJ20C August 2018 – March 2019 UCC21530-Q1
Figure 44shows a 2-layer PCB layout example with the signals and key components labeled.
There are no PCB traces or copper between the primary and secondary side, which ensures isolation performance.
PCB traces between the high-side and low-side gate drivers in the output stage are increased to maximize the creepage distance for high-voltage operation, which will also minimize cross-talk between the switching node VSSA (SW), where high dv/dt may exist, and the low-side gate drive due to the parasitic capacitance coupling.
The location of the PCB cutout between the primary side and secondary sides, which ensures isolation performance.