SLUSDU7
March 2020
UCC21320-Q1
PRODUCTION DATA.
1
Features
2
Applications
3
Description
Functional Block Diagram
4
Revision History
5
Pin Configuration and Functions
Pin Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Power Ratings
6.6
Insulation Specifications
6.7
Safety-Related Certifications
6.8
Safety-Limiting Values
6.9
Electrical Characteristics
6.10
Switching Characteristics
6.11
Insulation Characteristics Curves
6.12
Typical Characteristics
7
Parameter Measurement Information
7.1
Propagation Delay and Pulse Width Distortion
7.2
Rising and Falling Time
7.3
Input and Disable Response Time
7.4
Programable Dead Time
7.5
Power-up UVLO Delay to OUTPUT
7.6
CMTI Testing
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
VDD, VCCI, and Under Voltage Lock Out (UVLO)
8.3.2
Input and Output Logic Table
8.3.3
Input Stage
8.3.4
Output Stage
8.3.5
Diode Structure in the UCC21320-Q1
8.4
Device Functional Modes
8.4.1
Disable Pin
8.4.2
Programmable Dead Time (DT) Pin
8.4.2.1
Tying the DT Pin to VCC
8.4.2.2
DT Pin Connected to a Programming Resistor between DT and GND Pins
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.2.1
Designing INA/INB Input Filter
9.2.2.2
Select External Bootstrap Diode and its Series Resistor
9.2.2.3
Gate Driver Output Resistor
9.2.2.4
Gate to Source Resistor Selection
9.2.2.5
Estimate Gate Driver Power Loss
9.2.2.6
Estimating Junction Temperature
9.2.2.7
Selecting VCCI, VDDA/B Capacitor
9.2.2.7.1
Selecting a VCCI Capacitor
9.2.2.7.2
Selecting a VDDA (Bootstrap) Capacitor
9.2.2.7.3
Select a VDDB Capacitor
9.2.2.8
Dead Time Setting Guidelines
9.2.2.9
Application Circuits with Output Stage Negative Bias
9.2.3
Application Curves
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
Device and Documentation Support
12.1
Documentation Support
12.1.1
Related Documentation
12.2
Receiving Notification of Documentation Updates
12.3
Community Resources
12.4
Trademarks
12.5
Electrostatic Discharge Caution
12.6
Glossary
13
Mechanical, Packaging, and Orderable Information
封装选项
机械数据 (封装 | 引脚)
DWK|14
MPCS001
散热焊盘机械数据 (封装 | 引脚)
订购信息
slusdu7_oa
1
Features
4-A peak source, 6-A peak sink output
3-V to 18-V input VCCI range to interface with both digital and analog controllers
Up to 25-V VDD output drive supply
Switching parameters:
19-ns typical propagation delay
10-ns minimum pulse width
5-ns maximum delay matching
6
-ns maximum pulse-width distortion
Common-mode transient immunity (CMTI) greater than 100 V/ns
Universal: dual low-side, dual high-side or half-bridge driver
Programmable overlap and dead time
Wide Body SOIC-14 (DWK) Package
3.3mm spacing between driver channels
Operating temperature range –40 to +125°C
Surge immunity up to 12.8 kV
Isolation barrier life >40 years
TTL and CMOS compatible inputs
Rejects input pulses and noise transients shorter than 5 ns
Fast disable for power sequencing
Qualified for automotive applications
AEC-Q100 qualified with the following results
Device temperature grade 1
Device HBM ESD classification level H2
Device CDM ESD classification level C6