ZHCSI11A August   2009  – April 2018 TXB0106-Q1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      典型工作电路
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements – VCCA = 1.2 V, TA = 25°C
    7. 6.7  Timing Requirements – VCCA = 1.5 V ± 0.1 V
    8. 6.8  Timing Requirements – VCCA = 1.8 V ± 0.15 V
    9. 6.9  Timing Requirements – VCCA = 2.5 V ± 0.2 V
    10. 6.10 Timing Requirements – VCCA = 3.3 V ± 0.3 V
    11. 6.11 Switching Characteristics –VCCA = 1.2 V, TA = 25°C
    12. 6.12 Switching Characteristics – VCCA = 1.5 V ± 0.1 V
    13. 6.13 Switching Characteristics – VCCA = 1.8 V ± 0.15 V
    14. 6.14 Switching Characteristics – VCCA = 2.5 V ± 0.2 V
    15. 6.15 Switching Characteristics – VCCA = 3.3 V ± 0.3 V
    16. 6.16 Operating Characteristics
    17. 6.17 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Architecture
      2. 8.3.2 Input Driver Requirements
      3. 8.3.3 Power Up
      4. 8.3.4 Output Load Considerations
      5. 8.3.5 Enable and Disable
      6. 8.3.6 Pullup or Pulldown Resistors on I/O Lines
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 接收文档更新通知
    2. 12.2 社区资源
    3. 12.3 商标
    4. 12.4 静电放电警告
    5. 12.5 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

8.3.4 Output Load Considerations

TI recommends careful PCB layout practices with short PCB trace lengths to avoid excessive capacitive loading and to ensure that proper one-shot (O.S.) triggering takes place. PCB signal trace-lengths should be kept short enough such that the round trip delay of any reflection is less than the O.S. duration. This improves signal integrity by ensuring that any reflection sees a low impedance at the driver. The O.S. circuits have been designed to stay on for approximately 10 ns. The maximum capacitance of the lumped load that can be driven also depends directly on the O.S. duration. With very heavy capacitive loads, the O.S. can time out before the signal is driven fully to the positive rail. The O.S. duration has been set to best optimize trade-offs between dynamic ICC, load driving capability, and maximum bit-rate considerations. Both PCB trace length and connectors add to the capacitance that the TXB0106-Q1 output sees, so it is recommended that this lumped-load capacitance be considered to avoid O.S. retriggering, bus contention, output signal oscillations, or other adverse system-level affects.