ZHCS761F December 2011 – May 2017 TRF7962A
PRODUCTION DATA.
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
IPD1 | Supply current in power down mode 1 | All building blocks disabled, including supply-voltage regulators; measured after 500-ms settling time (EN = 0, EN2 = 0) | <0.5 | 5 | µA | |
IPD2 | Supply current in power down mode 2 (sleep mode) | The SYS_CLK generator and VDD_X remain active to support external circuitry, measured after 100-ms settling time (EN = 0, EN2 = 1) | 120 | 200 | µA | |
ISTBY | Supply current in standby mode | Oscillator running, supply-voltage regulators in low-consumption mode (EN = 1, EN2 = x) | 1.9 | 3.5 | mA | |
ION1 | Supply current without antenna driver current | Oscillator, regulators, RX, and AGC are active, TX is off | 10.5 | 14 | mA | |
ION2 | Supply current in TX (half power) | Oscillator, regulators, RX, AGC, and TX active, POUT = 100 mW | 70 | 78 | mA | |
ION3 | Supply current in TX (full power) | Oscillator, regulators, RX, AGC, and TX active, POUT = 200 mW | 130 | 170 | mA | |
VPOR | Power-on reset voltage | Input voltage at VIN | 1.4 | 2 | 2.6 | V |
VBG | Bandgap voltage (pin 11) | Internal analog reference voltage | 1.5 | 1.6 | 1.7 | V |
VDD_A | Regulated output voltage for analog circuitry (pin 1) | VIN = 5 V | 3.1 | 3.5 | 3.8 | V |
VDD_X | Regulated supply for external circuitry | Output voltage pin 32, VIN = 5 V | 3.1 | 3.4 | 3.8 | V |
IVDD_Xmax | Maximum output current of VDD_X | Output current pin 32, VIN = 5 V | 20 | mA | ||
RRFOUT | Antenna driver output resistance(4) | Half-power mode, VIN = 2.7 V to 5.5 V | 8 | 12 | Ω | |
Full-power mode, VIN = 2.7 V to 5.5 V | 4 | 6 | ||||
RRFIN | RX_IN1 and RX_IN2 input resistance | 4 | 10 | 20 | kΩ | |
VRF_INmax | Maximum RF input voltage at RX_IN1 or RX_IN2 | VRF_INmax should not exceed VIN | 3.5 | Vpp | ||
VRF_INmin | Minimum RF input voltage at RX_IN1 or RX_IN2 (input sensitivity)(2) | fSUBCARRIER = 424 kHz | 1.4 | 2.5 | mVpp | |
fSUBCARRIER = 848 kHz | 2.1 | 3 | ||||
fSYS_CLK | SYS_CLK frequency | In power mode 2, EN = 0, EN2 = 1 | 25 | 60 | 120 | kHz |
fC | Carrier frequency | Defined by external crystal | 13.56 | MHz | ||
tCRYSTAL | Crystal run-in time | Time until oscillator stable bit is set (register 0x0F) (3) | 5 | ms | ||
fD_CLKmax | Maximum DATA_CLK frequency(1) | Depends on capacitive load on the I/O lines, recommendation is 2 MHz(1) | 2 | 4 | 10 | MHz |
VIL | Input voltage, logic low | I/O lines, IRQ, SYS_CLK, DATA_CLK, EN, EN2 | 0.2 × VDD_I/O | V | ||
VIH | Input voltage threshold, logic high | I/O lines, IRQ, SYS_CLK, DATA_CLK, EN, EN2 | 0.8 × VDD_I/O | V | ||
ROUT | Output resistance, I/O_0 to I/O_7 | 500 | 800 | Ω | ||
RSYS_CLK | Output resistance RSYS_CLK | 200 | 400 | Ω |