ZHCSQM0 December 2022 TPSM82816
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
SUPPLY | ||||||
IQ | Quiescent current | EN = High, no load, device not switching, MODE/SYNC = GND, VOUT = 0.6 V | 18 | 36 | μA | |
ISD | Shutdown current | EN = GND | 0.15 | 90 | μA | |
VUVLO | Undervoltage lock out threshold | VIN rising | 2.45 | 2.6 | 2.7 | V |
VIN falling | 2.1 | 2.5 | 2.6 | V | ||
TJSD | Thermal shutdown threshold | TJ rising | 180 | °C | ||
Thermal shutdown hysteresis | TJ falling | 15 | °C | |||
CONTROL and INTERFACE | ||||||
VIH,EN | Input threshold voltage | EN rising |
1.05 | 1.1 | 1.15 | V |
VIL,EN | Input threshold voltage | EN falling |
0.96 | 1.0 | 1.05 | V |
IIH,EN | Input leakage current into EN | EN = VIN or GND | 125 | nA | ||
VIH | Input-threshold voltage at MODE/SYNC | 1.1 | V | |||
VIL | Input-threshold voltage at MODE/SYNC | 0.3 | V | |||
IIH | Input leakage current into MODE/SYNC | 250 | nA | |||
fSW | PWM Switching frequency range | MODE/SYNC = high | 1.8 | 2.25 | 4 | MHz |
fSW | PWM Switching frequency | COMP/FSET = GND or VIN | 2.08 | 2.25 | 2.4 | MHz |
fSW | PWM Switching frequency tolerance | using a resistor from COMP/FSET to GND | –12 % | 12 % | ||
fSYNC | Frequency range on MODE/SYNC pin for synchronization | 1.8 | 4 | MHz | ||
tSync_lock | Time to lock to external frequency | 50 | µs | |||
Duty cycle of synchronization signal at MODE/SYNC | 20 % | 80 % | ||||
tDelay | Enable delay time | Time from EN high to device starts switching; VIN applied already | 135 | 270 | 520 | µs |
tRamp | Output voltage ramp time, SS/TR pin open | IOUT = 0 mA, time from device starts switching to power good; device not in current limit | 90 | 150 | 220 | µs |
ISS/TR | SS/TR source current | 8 | 10 | 12 | µA | |
RDIS,SS/TR | Internal discharge resistance on SS/TR | EN = low | 0.7 | 1.1 | 1.5 | kΩ |
Tracking gain | VFB / VSS/TR | 1 | ||||
Tracking offset | VFB when VSS/TR = 0 V | ±1 | mV | |||
VTH_PG | UVP power good threshold voltage; dc level | VOUT rising (%VFB) | 92 % | 95 % | 98 % | |
VTH_PG | UVP power good threshold voltage; dc level | VOUT falling (%VFB) | 87 % | 90 % | 93 % | |
VTH_PG | OVP power good threshold voltage; dc level | VOUT rising (%VFB) | 107 % | 110 % | 113 % | |
OVP power good threshold voltage; dc level | VOUT falling (%VFB) | 104 % | 107 % | 111 % | ||
VOL,PG | Low-level output voltage at PG | ISINK_PG = 2 mA | 0.01 | 0.3 | V | |
IIH,PG | Input leakage current into PG | VPG = 5 V | 100 | nA | ||
tPG,DLY | PG deglitch time | for a high level to low level transition on the power good output | 40 | µs | ||
OUTPUT | ||||||
VFB | Feedback voltage | 0.6 | V | |||
VFB | Feedback voltage accuracy | PWM mode, VIN ≥ VOUT + 1 V | –1 % | 1 % | ||
VFB | Feedback voltage accuracy | PFM mode, VIN ≥ VOUT + 1 V, VOUT ≥ 1.5 V, Co,eff ≥ 47 µF | –1 % | 2 % | ||
VFB | Feedback voltage accuracy | PFM mode, VIN ≥ VOUT + 1 V, VOUT < 1.5 V, Co,eff ≥ 68 µF |
–1 % | 2.5 % | ||
VFB | Feedback voltage accuracy with voltage tracking | VIN ≥ VOUT + 1 V, VSS/TR = 0.3 V, PWM mode | –5 % | 5 % | ||
IIH,FB | Input leakage current into FB | VFB = 0.6 V | 1 | 70 | nA | |
Load regulation | PWM mode | 0.05 | %/A | |||
RDIS | Output discharge resistance | 30 | 50 | Ω | ||
ton,min | Minimum on-time of high-side FET | VIN ≥ 3.3 V | 45 | 67 | ns | |
RDP | Dropout Resistance | 100% mode | 27 | mΩ | ||
ILIMH | High-side FET switch current limit | DC value, VIN = 3 V to 6 V | 7.3 | 9.2 | 10.4 | A |
ILIMNEG | Low-side FET negative current limit | DC value, MODE/SYNC = high | –3 | A |