ZHCSIF5F December   2015  – April 2019 TPS99000-Q1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     典型的独立系统
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions - Initialization, Clock, and Diagnostics
    2.     Pin Functions - Power and Ground
    3.     Pin Functions - Power Supply Management
    4.     Pin Functions - Illumination Control
    5.     Pin Functions - Serial Peripheral Interfaces
    6.     Pin Functions - Analog to Digital Converter
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Transimpedance Amplifier Parameters
    6. 6.6  Electrical Characteristics - Digital to Analog Converters
    7. 6.7  Electrical Characteristics - Analog to Digital Converter
    8. 6.8  Electrical Characteristics - FET Gate Drivers
    9. 6.9  Electrical Characteristics - Photo Comparator
    10. 6.10 Electrical Characteristics - Voltage Regulators
    11. 6.11 Electrical Characteristics - Temperature and Voltage Monitors
    12. 6.12 Electrical Characteristics - Current Consumption
    13. 6.13 Power-Up Timing Requirements
    14. 6.14 Power-Down Timing Requirements
    15. 6.15 Timing Requirements - Sequencer Clock
    16. 6.16 Timing Requirements - Host / Diagnostic Port SPI Interface
    17. 6.17 Timing Requirements - ADC Interface
    18. 6.18 Switching Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Illumination Control
        1. 7.3.1.1 Illumination System High Dynamic Range Dimming Overview
        2. 7.3.1.2 Illumination Control Loop
        3. 7.3.1.3 Continuous Mode Operation
          1. 7.3.1.3.1 Output Capacitance in Continuous Mode
          2. 7.3.1.3.2 Continuous Mode Driver Distortion and Blanking Current
          3. 7.3.1.3.3 Continuous Mode S_EN2 Dissipative Load Shunt Options
          4. 7.3.1.3.4 Continuous Mode Constant OFF Time
          5. 7.3.1.3.5 Continuous Mode Current Limit
        4. 7.3.1.4 Discontinuous Mode Operation
          1. 7.3.1.4.1 Discontinuous Mode Pulse Width Limit
          2. 7.3.1.4.2 COMPOUT_LOW Timer in Discontinuous Operation
          3. 7.3.1.4.3 Dimming Within Discontinuous Operation Range
          4. 7.3.1.4.4 Multiple Pulse Heights to Increase Bit Depth
          5. 7.3.1.4.5 TIA Gain Adjustment
          6. 7.3.1.4.6 Current Limit in Discontinuous Mode
          7. 7.3.1.4.7 CMODE Big Cap Mode in Discontinuous Operation
      2. 7.3.2 Over-Brightness Detection
        1. 7.3.2.1 Photo Feedback Monitor BIST
        2. 7.3.2.2 Excessive Brightness BIST
      3. 7.3.3 Analog to Digital Converter
        1. 7.3.3.1 Analog to Digital Converter Input Table
      4. 7.3.4 Power Sequencing and Monitoring
        1. 7.3.4.1 Power Monitoring
      5. 7.3.5 DMD Mirror Voltage Regulator
      6. 7.3.6 Low Dropout Regulators
      7. 7.3.7 System Monitoring Features
        1. 7.3.7.1 Windowed Watchdog Circuits
        2. 7.3.7.2 Die Temperature Monitors
        3. 7.3.7.3 External Clock Ratio Monitor
      8. 7.3.8 Communication Ports
        1. 7.3.8.1 Serial Peripheral Interface (SPI)
    4. 7.4 Device Functional Modes
      1. 7.4.1 OFF
      2. 7.4.2 STANDBY
      3. 7.4.3 POWERING_DMD
      4. 7.4.4 DISPLAY_RDY
      5. 7.4.5 DISPLAY_ON
      6. 7.4.6 PARKING
      7. 7.4.7 SHUTDOWN
    5. 7.5 Register Maps
      1. 7.5.1 System Status Registers
      2. 7.5.2 ADC Control
      3. 7.5.3 General Fault Status
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 HUD
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Application Design Considerations
          1. 8.2.1.2.1 Photodiode Considerations
          2. 8.2.1.2.2 LED Current Measurement
          3. 8.2.1.2.3 Setting the Current Limit
          4. 8.2.1.2.4 Input Voltage Variation Impact
          5. 8.2.1.2.5 Discontinuous Mode Photo Feedback Considerations
          6. 8.2.1.2.6 Transimpedance Amplifiers (TIAs, Usage, Offset, Dark Current, Ranges, RGB Trim)
      2. 8.2.2 Headlight
        1. 8.2.2.1 Design Requirements
  9. 9 Power Supply Recommendations
    1. 9.1 TPS99000-Q1 Power Supply Architecture
    2. 9.2 TPS99000-Q1 Power Outputs
    3. 9.3 Power Supply Architecture
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Power/High Current Signals
      2. 10.1.2 Sensitive Analog Signals
      3. 10.1.3 High Speed Digital Signals
      4. 10.1.4 High Power Current Loops
      5. 10.1.5 Kelvin Sensing Connections
      6. 10.1.6 Ground Separation
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 第三方产品免责声明
    2. 11.2 商标
    3. 11.3 静电放电警告
    4. 11.4 术语表
  12. 12机械、封装和可订购信息
    1. 12.1 Package Option Addendum
      1. 12.1.1 Tape and Reel Information
      2. 12.1.2 Mechanical Drawings

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.3.4.1 Power Monitoring

Main asynchronous digital logic reset (DVDD_RSTZ) – Monitor of the main power of the 3.3 V power supply input to the TPS99000-Q1. This monitor output is used as an asynchronous reset for all of the digital logic inside TPS99000-Q1.

TPS99000-Q1 internal_DVDD_monitor_3.gifFigure 33. Internal DVDD Monitor

The PROJ_ON pin is the main on/off switch for DLP subsystem. 1 is ON, 0 is OFF. Once DVDD_ARSTZ is released, TPS99000-Q1 will begin sampling the PROJ_ON pin. If it is low, system stays in the OFF state. If it goes high, TPS99000-Q1 begins to progress through the power-on process.

The TPS99000-Q1 includes a VMAIN brown out monitor function. A voltage monitor observes the voltage on the VMAIN input pin, as shown in Figure 34. The Zener may be necessary for over voltage protection of the pin, in case the voltage being monitored has the potential to go high, such as a battery input.

Either PROJ_ON or VMAIN may be used to turn the system on and off, and doing so will remove power to the DLPC230-Q1. For fast control of turning the display on and off without removing power to the DLPC230-Q1, change the operating mode of the DLPC230-Q1 embedded software between 'Standby' and 'Display'.

TPS99000-Q1 VMAIN_brown-out_monitor_DLPS039.gifFigure 34. VMAIN Brown Out Monitor

This monitor is used to provide the DLP subsystem with an early warning that power to the unit is going away. The system will park the DMD mirrors and proceed to a ready for power-off state if the VMAIN input voltage falls below a fixed threshold. External resistors should be used to divide the input power rail. Once a VMAIN brown out occurs, the main power rails to the TPS99000-Q1 must remain within their operating ranges until the TPS99000-Q1 power-down is complete.

The main power rails to the chipset (6 V, 3.3 V, 1.8 V and 1.1 V) are monitored with real time power monitors as well. Each of these monitors is logically 'OR'ed together to produce the pwrgood2 signal in Figure 35.

TPS99000-Q1 real_time_power_rail_monitors3.gifFigure 35. Real-Time Power Rail Monitors

Additionally, all power within the TPS99000-Q1 can be monitored by the ADC function. DLPC230-Q1 software configures the ADC block to collect all voltage information in the system each frame. Any gross out of specification issues are captured and reported as system errors in the DLPC230-Q1 system status.