ZHCSIF5F December   2015  – April 2019 TPS99000-Q1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     典型的独立系统
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions - Initialization, Clock, and Diagnostics
    2.     Pin Functions - Power and Ground
    3.     Pin Functions - Power Supply Management
    4.     Pin Functions - Illumination Control
    5.     Pin Functions - Serial Peripheral Interfaces
    6.     Pin Functions - Analog to Digital Converter
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Transimpedance Amplifier Parameters
    6. 6.6  Electrical Characteristics - Digital to Analog Converters
    7. 6.7  Electrical Characteristics - Analog to Digital Converter
    8. 6.8  Electrical Characteristics - FET Gate Drivers
    9. 6.9  Electrical Characteristics - Photo Comparator
    10. 6.10 Electrical Characteristics - Voltage Regulators
    11. 6.11 Electrical Characteristics - Temperature and Voltage Monitors
    12. 6.12 Electrical Characteristics - Current Consumption
    13. 6.13 Power-Up Timing Requirements
    14. 6.14 Power-Down Timing Requirements
    15. 6.15 Timing Requirements - Sequencer Clock
    16. 6.16 Timing Requirements - Host / Diagnostic Port SPI Interface
    17. 6.17 Timing Requirements - ADC Interface
    18. 6.18 Switching Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Illumination Control
        1. 7.3.1.1 Illumination System High Dynamic Range Dimming Overview
        2. 7.3.1.2 Illumination Control Loop
        3. 7.3.1.3 Continuous Mode Operation
          1. 7.3.1.3.1 Output Capacitance in Continuous Mode
          2. 7.3.1.3.2 Continuous Mode Driver Distortion and Blanking Current
          3. 7.3.1.3.3 Continuous Mode S_EN2 Dissipative Load Shunt Options
          4. 7.3.1.3.4 Continuous Mode Constant OFF Time
          5. 7.3.1.3.5 Continuous Mode Current Limit
        4. 7.3.1.4 Discontinuous Mode Operation
          1. 7.3.1.4.1 Discontinuous Mode Pulse Width Limit
          2. 7.3.1.4.2 COMPOUT_LOW Timer in Discontinuous Operation
          3. 7.3.1.4.3 Dimming Within Discontinuous Operation Range
          4. 7.3.1.4.4 Multiple Pulse Heights to Increase Bit Depth
          5. 7.3.1.4.5 TIA Gain Adjustment
          6. 7.3.1.4.6 Current Limit in Discontinuous Mode
          7. 7.3.1.4.7 CMODE Big Cap Mode in Discontinuous Operation
      2. 7.3.2 Over-Brightness Detection
        1. 7.3.2.1 Photo Feedback Monitor BIST
        2. 7.3.2.2 Excessive Brightness BIST
      3. 7.3.3 Analog to Digital Converter
        1. 7.3.3.1 Analog to Digital Converter Input Table
      4. 7.3.4 Power Sequencing and Monitoring
        1. 7.3.4.1 Power Monitoring
      5. 7.3.5 DMD Mirror Voltage Regulator
      6. 7.3.6 Low Dropout Regulators
      7. 7.3.7 System Monitoring Features
        1. 7.3.7.1 Windowed Watchdog Circuits
        2. 7.3.7.2 Die Temperature Monitors
        3. 7.3.7.3 External Clock Ratio Monitor
      8. 7.3.8 Communication Ports
        1. 7.3.8.1 Serial Peripheral Interface (SPI)
    4. 7.4 Device Functional Modes
      1. 7.4.1 OFF
      2. 7.4.2 STANDBY
      3. 7.4.3 POWERING_DMD
      4. 7.4.4 DISPLAY_RDY
      5. 7.4.5 DISPLAY_ON
      6. 7.4.6 PARKING
      7. 7.4.7 SHUTDOWN
    5. 7.5 Register Maps
      1. 7.5.1 System Status Registers
      2. 7.5.2 ADC Control
      3. 7.5.3 General Fault Status
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 HUD
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Application Design Considerations
          1. 8.2.1.2.1 Photodiode Considerations
          2. 8.2.1.2.2 LED Current Measurement
          3. 8.2.1.2.3 Setting the Current Limit
          4. 8.2.1.2.4 Input Voltage Variation Impact
          5. 8.2.1.2.5 Discontinuous Mode Photo Feedback Considerations
          6. 8.2.1.2.6 Transimpedance Amplifiers (TIAs, Usage, Offset, Dark Current, Ranges, RGB Trim)
      2. 8.2.2 Headlight
        1. 8.2.2.1 Design Requirements
  9. 9 Power Supply Recommendations
    1. 9.1 TPS99000-Q1 Power Supply Architecture
    2. 9.2 TPS99000-Q1 Power Outputs
    3. 9.3 Power Supply Architecture
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Power/High Current Signals
      2. 10.1.2 Sensitive Analog Signals
      3. 10.1.3 High Speed Digital Signals
      4. 10.1.4 High Power Current Loops
      5. 10.1.5 Kelvin Sensing Connections
      6. 10.1.6 Ground Separation
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 第三方产品免责声明
    2. 11.2 商标
    3. 11.3 静电放电警告
    4. 11.4 术语表
  12. 12机械、封装和可订购信息
    1. 12.1 Package Option Addendum
      1. 12.1.1 Tape and Reel Information
      2. 12.1.2 Mechanical Drawings

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.5 Electrical Characteristics - Transimpedance Amplifier Parameters

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TIA1 AND TIA2
IIN_TOT TIA1 and TIA2 Combined Input Current 0 7(3) mA
TRANSIMPEDANCE AMPLIFIER #1 (TIA1)
IIN TIA Input Current RGB trim <= 0.5x(1) 0 0.6 4.8 mA
CIN Total Input Capacitance(2) Allowable input capacitances from board, connectors, photo diode, and cables 10 50 140 pF
TRIMRGB RGB Trim, normal flux system 0.2 0.5 1 V/V
GAINTOLABS TIA Gain Tolerance (absolute) Tolerance to specified gain target per setting –20% 20%
GAINTOLREL TIA Gain Tolerance (relative) Tolerance as a ratio to other settings 3%
TIA1 SLEW RATE
TIASLEW1 Low Gain Slew Rate, Output Referred <= 96 kV/A gain 12 V/µs
TIASLEW2 High Gain Slew Rate, Output Referred > 96 kV/A gain 5 V/µs
TIADELAY TIA Pad to COMPOUT Pad Delay, DM min, Falling Edge max slew rate input, 20 pF load, 100 mV minimum over trip point 40 64 ns
TIADELAYCM TIA Pad to COMPOUT Delay. CM CM max current 100 ns
TIA1 EFFECTIVE GAIN
Gain Setting 0 Trim set to 1.0 0.6 0.75 0.9 kV/A
Gain Setting 1 Trim set to 1.0 1.2 1.5 1.8 kV/A
Gain Setting 2 Trim set to 1.0 2.4 3 3.6 kV/A
Gain Setting 3 Trim set to 1.0 4.8 6 7.2 kV/A
Gain Setting 4 Trim set to 1.0 7.2 9 10.8 kV/A
Gain Setting 5 Trim set to 1.0 9.6 12 14.4 kV/A
Gain Setting 6 Trim set to 1.0 14.4 18 21.6 kV/A
Gain Setting 7 Trim set to 1.0 19.2 24 28.8 kV/A
Gain Setting 8 Trim set to 1.0 28.8 36 43.2 kV/A
Gain Setting 9 Trim set to 1.0 38.4 48 57.6 kV/A
Gain Setting 10 Trim set to 1.0 57.6 72 86.4 kV/A
Gain Setting 11 Trim set to 1.0 76.8 96 115.2 kV/A
Gain Setting 12 Trim set to 1.0 115.2 144 172.8 kV/A
Gain Setting 13 Trim set to 1.0 230.4 288 345.6 kV/A
TRANSIMPEDANCE AMPLIFIER #2 (TIA2)
IIN TIA Input Current RGB trim <= 0.5x(1) 0 4.8 mA
TRIMRGB RGB Trim, normal flux system 0.2 1 V/V
TIA2 SLEW RATE
TIA2SLEW Slew Rate, Output Referred All gains 1 V/µs
TIA2 EFFECTIVE GAIN
Gain Setting 0 Trim set to 1.0 0.6 0.75 0.9 kV/A
Gain Setting 1 Trim set to 1.0 1.2 1.5 1.8 kV/A
Gain Setting 2 Trim set to 1.0 2.4 3 3.6 kV/A
Gain Setting 3 Trim set to 1.0 4.8 6 7.2 kV/A
Gain Setting 4 Trim set to 1.0 7.2 9 10.8 kV/A
Gain Setting 5 Trim set to 1.0 9.6 12 14.4 kV/A
Gain Setting 6 Trim set to 1.0 14.4 18 21.6 kV/A
Gain Setting 7 Trim set to 1.0 19.2 24 28.8 kV/A
Gain Setting 8 Trim set to 1.0 28.8 36 43.2 kV/A
Gain Setting 9 Trim set to 1.0 38.4 48 57.6 kV/A
Gain Setting 10 Trim set to 1.0 57.6 72 86.4 kV/A
Gain Setting 11 Trim set to 1.0 76.8 96 115.2 kV/A
Gain Setting 12 Trim set to 1.0 115.2 144 172.8 kV/A
Gain Setting 13 Trim set to 1.0 230.4 288 345.6 kV/A
(1) Maximum input current decreases linearly in proportion to the selected trim value, with a lower maximum value of 2.4 mA occurring when the trim is 1.0×.
(2) Large capacitive loads could impact system performance.
(3) For applications requiring greater than 7 mA combined TIA current, contact TI for details.