SLVS351P September   2002  – March 2015

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Shutdown
      2. 7.3.2 Start-Up
      3. 7.3.3 Undervoltage Lockout (UVLO)
      4. 7.3.4 Regulator Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
      3. 7.4.3 Disabled
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input and Output Capacitor Requirements
        2. 8.2.2.2 Output Noise
        3. 8.2.2.3 Dropout Voltage
        4. 8.2.2.4 Programming the TPS79601 Adjustable LDO Regulator
      3. 8.2.3 Application Curves
    3. 8.3 Do's and Don'ts
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Board Layout Recommendation to Improve PSRR and Noise Performance
      2. 10.1.2 Regulator Mounting
    2. 10.2 Layout Examples
    3. 10.3 Thermal Considerations
    4. 10.4 Estimating Junction Temperature
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Evaluation Modules
        2. 11.1.1.2 Spice Models
      2. 11.1.2 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Related Links
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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10 Layout

10.1 Layout Guidelines

10.1.1 Board Layout Recommendation to Improve PSRR and Noise Performance

To improve AC measurements like PSRR, output noise, and transient response, it is recommended that the board be designed with separate ground planes for VIN and VOUT, with each ground plane connected only at the ground pin of the device. In addition, the ground connection for the bypass capacitor should connect directly to the ground pin of the device.

10.1.2 Regulator Mounting

The tab of the SOT223-6 package is electrically connected to ground. For best thermal performance, the tab of the surface-mount version should be soldered directly to a circuit-board copper area. Increasing the copper area improves heat dissipation.

Solder pad footprint recommendations for the devices are presented in an application bulletin Solder Pad Recommendations for Surface-Mount Devices, SBFA015, available from the TI website (www.ti.com).

10.2 Layout Examples

TPS79601 TPS79613 TPS79618 TPS79625 TPS79628 TPS79630 TPS79633 TPS79650 ai_pcb_layout_adjust_lvs351.gifFigure 28. TPS79601 (Adjustable Voltage Version)—DRB Layout Example
TPS79601 TPS79613 TPS79618 TPS79625 TPS79628 TPS79630 TPS79633 TPS79650 ai_pcb_layout_fixed_lvs351.gifFigure 29. TPS796xx (Fixed Voltage Versions)—DRB Layout Example

10.3 Thermal Considerations

Knowing the device power dissipation and proper sizing of the thermal plane that is connected to the tab or pad is critical to avoiding thermal shutdown and ensuring reliable operation.

Power dissipation of the device depends on input voltage and load conditions and can be calculated using Equation 4:

Equation 4. TPS79601 TPS79613 TPS79618 TPS79625 TPS79628 TPS79630 TPS79633 TPS79650 q_pd_bvs064.gif

Power dissipation can be minimized and greater efficiency can be achieved by using the lowest possible input voltage necessary to achieve the required output voltage regulation.

On the VSON (DRB) package, the primary conduction path for heat is through the exposed pad to the printed circuit board (PCB). The pad can be connected to ground or be left floating; however, it should be attached to an appropriate amount of copper PCB area to ensure the device does not overheat. On both SOT-223 (DCQ) and TO-263 (KTT) packages, the primary conduction path for heat is through the tab to the PCB. That tab should be connected to ground. The maximum junction-to-ambient thermal resistance depends on the maximum ambient temperature, maximum device junction temperature, and power dissipation of the device and can be calculated using Equation 5:

Equation 5. TPS79601 TPS79613 TPS79618 TPS79625 TPS79628 TPS79630 TPS79633 TPS79650 q_rth_bvs064.gif '

Knowing the maximum RθJA, the minimum amount of PCB copper area needed for appropriate heatsinking can be estimated using Figure 30.

TPS79601 TPS79613 TPS79618 TPS79625 TPS79628 TPS79630 TPS79633 TPS79650 ai_theta_ja_lvs351.gif
θJA value at board size of 9in2 (that is, 3in × 3in) is a JEDEC standard.
Figure 30. ΘJA vs Board Size

Figure 30 shows the variation of θJA as a function of ground plane copper area in the board. It is intended only as a guideline to demonstrate the effects of heat spreading in the ground plane and should not be used to estimate actual thermal performance in real application environments.

NOTE

When the device is mounted on an application PCB, it is strongly recommended to use ΨJT and ΨJB, as explained in .

10.4 Estimating Junction Temperature

Using the thermal metrics ΨJT and ΨJB, as shown in Thermal Information, the junction temperature can be estimated with corresponding formulas (given in Equation 6). For backwards compatibility, an older θJC,Top parameter is listed as well.

Equation 6. TPS79601 TPS79613 TPS79618 TPS79625 TPS79628 TPS79630 TPS79633 TPS79650 q_new_metrics_bvs066.gif

where

  • PD is the power dissipation shown by Equation 5
  • TT is the temperature at the center-top of the IC package
  • TB is the PCB temperature measured 1mm away from the IC package on the PCB surface (as Figure 32 shows).

NOTE

Both TT and TB can be measured on actual application boards using a thermo‐gun (an infrared thermometer).

For more information about measuring TT and TB, see the application note SBVA025, Using New Thermal Metrics, available at www.ti.com.

By looking at Figure 31, the new thermal metrics (ΨJT and ΨJB) have very little dependency on board size. That is, using ΨJT or ΨJB with Equation 6 is a good way to estimate TJ by simply measuring TT or TB, regardless of the application board size.

TPS79601 TPS79613 TPS79618 TPS79625 TPS79628 TPS79630 TPS79633 TPS79650 ai_psi_jt_jb_lvs351.gifFigure 31. ΨJT And ΨJB vs Board Size

For a more detailed discussion of why TI does not recommend using θJC(top) to determine thermal characteristics, refer to application report SBVA025, Using New Thermal Metrics, available for download at www.ti.com. For further information, refer to application report SPRA953, IC Package Thermal Metrics, also available on the TI website.

TPS79601 TPS79613 TPS79618 TPS79625 TPS79628 TPS79630 TPS79633 TPS79650 ai_measuring_point_lvs351.gif
1. TT is measured at the center of both the X- and Y-dimensional axes.
2. TB is measured below the package lead on the PCB surface.
Figure 32. Measuring Points For TT and TB