ZHCSDM1 December   2014 TPS650830

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 说明（续）
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Voltage Regulator Assignment and Powergood Comparator Logic Assignment (External Voltage Regulator or Load Switch) for SkyLake Platform
      2. 8.3.2 Converters
        1. 8.3.2.1 Power Save Mode
        2. 8.3.2.2 Voltage Regulator Startup
        3. 8.3.2.3 Power Good
        4. 8.3.2.4 Current Limit
        5. 8.3.2.5 Output Discharge Feature
        6. 8.3.2.6 Output Voltage Control
        7. 8.3.2.7 Converter Low Power Mode Operation
        8. 8.3.2.8 Controller Low Power Mode Operation
        9. 8.3.2.9 Undervoltage Lockout
      3. 8.3.3 Coincell Selector
        1. 8.3.3.1 Functional Description of RTC Powerpath and LDO
      4. 8.3.4 I2C - Interface
        1. 8.3.4.1 F/S-Mode Protocol
    4. 8.4 Device Functional Modes
    5. 8.5 Register Map
      1. 8.5.1  OTP_SPARE2 Register (address = 0xF0) [reset = 00000000]
      2. 8.5.2  OTP_SPARE1 Register (address = 0xEF) [reset = 00000000]
      3. 8.5.3  VREN_PIN_OVR Register (address = 0xEE) [reset = 00000000]
      4. 8.5.4  TEMPHOT Register (address = 0xEC) [reset = 00000000]
      5. 8.5.5  TEMPCRIT Register (address = 0xEB) [reset = 00000000]
      6. 8.5.6  STDBY_CTRL Register (address = 0xEA) [reset = 11111110]
      7. 8.5.7  MISC_BITS Register (address = 0xE9) [reset = 00010000]
      8. 8.5.8  PGOOD_STAT2 Register (address = 0xE8) [reset = 00000000]
      9. 8.5.9  PGOOD_STAT1 Register (address = 0xE7) [reset = 00000000]
      10. 8.5.10 PWFAULT_MASK2 Register (address = 0xE6) [reset = 00000000]
      11. 8.5.11 PWFAULT_MASK1 Register (address = 0xE5) [reset = 00000000]
      12. 8.5.12 COMPH_REF Register (address = 0xE4) [reset = 00000000]
      13. 8.5.13 COMPG_REF Register (address = 0xE3) [reset = 00011110]
      14. 8.5.14 COMPF_REF Register (address = 0xE2) [reset = 00011110]
      15. 8.5.15 COMPE_REF Register (address = 0xE1) [reset = 00011110]
      16. 8.5.16 COMPD_REF Register (address = 0xE0) [reset = 00011110]
      17. 8.5.17 COMPC_REF Register (address = 0xDF) [reset = 00011110]
      18. 8.5.18 COMPB_REF Register (address = 0xDE) [reset = 00011110]
      19. 8.5.19 COMPA_REF Register (address = 0xDD) [reset = 00011110]
      20. 8.5.20 CLKCTRL1 Register (address = 0xD0) [reset = 00000000]
      21. 8.5.21 SPWRSRCINT Register (address = 0x6F) [reset = 00000000]
      22. 8.5.22 LOWBATTDET Register (address = 0x6A) [reset = 11111000]
      23. 8.5.23 ACOKDBDM Register (address = 0x69) [reset = 00001111]
      24. 8.5.24 VDLMTCRT Register (address = 0x51) [reset = 00000101]
      25. 8.5.25 SDWNCTRL Register (address = 0x49) [reset = 00000000]
      26. 8.5.26 RSTCTRL Register (address = 0x48) [reset = 00011100]
      27. 8.5.27 VRENPINMASK Register (address = 0x43) [reset = 00000000]
      28. 8.5.28 REGLOCK Register (address = 0x42) [reset = 00000000]
      29. 8.5.29 VREN Register (address = 0x41) [reset = 00000000]
      30. 8.5.30 PWRGDCNT1 Register (address = 0x40) [reset = 01011111]
      31. 8.5.31 DISCHCNT4 Register (address = 0x3F) [reset = 00000000]
      32. 8.5.32 DISCHCNT3 Register (address = 0x3E) [reset = 00000000]
      33. 8.5.33 DISCHCNT2 Register (address = 0x3D) [reset = 00000000]
      34. 8.5.34 DISCHCNT1 Register (address = 0x3C) [reset = 00000000]
      35. 8.5.35 VRMODECTRL Register (address = 0x3B) [reset = 00111111]
      36. 8.5.36 V085ACNT Register (address = 0x38) [reset = 00101010]
      37. 8.5.37 V100ACNT Register (address = 0x37) [reset = 00101010]
      38. 8.5.38 V1P2UCNT Register (address = 0x36) [reset = 00111010]
      39. 8.5.39 V18U25UCNT Register (address = 0x35) [reset = 00001010]
      40. 8.5.40 V18ACNT Register (address = 0x34) [reset = 00101010]
      41. 8.5.41 V33APCHCNT Register (address = 0x33) [reset = 00001010]
      42. 8.5.42 V33ADSWCNT Register (address = 0x32) [reset = 00101010]
      43. 8.5.43 V5ADS3CNT Register (address = 0x31) [reset = 00101010]
      44. 8.5.44 VCCIOCNT Register (address = 0x30) [reset = 00001010]
      45. 8.5.45 PGMASK2 Register (address = 0x19) [reset = 00000000]
      46. 8.5.46 PGMASK1 Register (address = 0x18) [reset = 00000000]
      47. 8.5.47 PWRSTAT2 Register (address = 0x17) [reset = 00000000]
      48. 8.5.48 PWRSTAT1 Register (address = 0x16) [reset = 00000000]
      49. 8.5.49 PBSTATUS Register (address = 0x15) [reset = 00000000]
      50. 8.5.50 PBCONFIG Register (address = 0x14) [reset = 00011111]
      51. 8.5.51 IRQLVL1msK Register (address = 0x13) [reset = 10100101]
      52. 8.5.52 RESETIRQ2MASK Register (address = 0x12) [reset = 00000010]
      53. 8.5.53 RESETIRQ1MASK Register (address = 0x11) [reset = 00110000]
      54. 8.5.54 MPWRSRCINT Register (address = 0x0C) [reset = 01111000]
      55. 8.5.55 MPMUINT Register (address = 0x0B) [reset = 00010100]
      56. 8.5.56 RESETIRQ2 Register (address = 0x09) [reset = 00000000]
      57. 8.5.57 RESETIRQ1 Register (address = 0x08) [reset = 00000000]
      58. 8.5.58 PMUINT Register (address = 0x05) [reset = 00000000]
      59. 8.5.59 PWRSRCINT Register (address = 0x04) [reset = 00000000]
      60. 8.5.60 IRQLVL1 Register (address = 0x02) [reset = 00000000]
      61. 8.5.61 REVID Register (address = 0x01) [reset = 00000000]
      62. 8.5.62 VENDORID Register (address = 0x00) [reset = 00100010]
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 General Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Controller Design Procedure
            1. 9.2.1.2.1.1 Selecting the Inductor
            2. 9.2.1.2.1.2 Selecting the Output Capacitors
            3. 9.2.1.2.1.3 Selecting the FETs
            4. 9.2.1.2.1.4 Setting the Current Limits
            5. 9.2.1.2.1.5 Selecting the Input Capacitors
          2. 9.2.1.2.2 Converter Design Procedure
            1. 9.2.1.2.2.1 Selecting the Inductor
            2. 9.2.1.2.2.2 Selecting the Output Capacitors
            3. 9.2.1.2.2.3 Selecting the Input Capacitors
          3. 9.2.1.2.3 LDO Design Procedure
          4. 9.2.1.2.4 Board Temperature Monitoring Design Procedure
          5. 9.2.1.2.5 Sequencing the Voltage Rails
          6. 9.2.1.2.6 Power Path Design Procedure
        3. 9.2.1.3 Application Performance Curves
      2. 9.2.2 Specific Application - TPS650830 Powering the Intel SkyLake Platform Volume Configuration
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Output Inductance and Capacitance
        3. 9.2.2.3 Application Performance Curves
    3. 9.3 System Examples
    4. 9.4 Do's and Don'ts
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Fanout for ZAJ using Type 4 Routing
      2. 11.1.2 Fanout for ZCG using Type 3 Routing
      3. 11.1.3 Layout Checklist
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12器件和文档支持
    1. 12.1 器件支持
      1. 12.1.1 第三方产品免责声明
      2. 12.1.2 开发支持
    2. 12.2 文档支持
      1. 12.2.1 相关文档
    3. 12.3 商标
    4. 12.4 静电放电警告
    5. 12.5 术语表
  13. 13机械、封装和可订购信息

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