ZHCSIN0E August   2018  – April 2020 TPS62810-Q1 , TPS62811-Q1 , TPS62812-Q1 , TPS62813-Q1

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
    1.     Device Images
      1.      简化原理图
      2.      效率与输出电流间的关系;VOUT = 3.3V;PWM/PFM;fS = 2.25MHz
  4. 修订历史记录
  5. Device Comparison Table
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Parameter Measurement Information
    1. 8.1 Schematic
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Precise Enable
      2. 9.3.2 COMP/FSET
      3. 9.3.3 MODE / SYNC
      4. 9.3.4 Spread Spectrum Clocking (SSC)
      5. 9.3.5 Undervoltage Lockout (UVLO)
      6. 9.3.6 Power Good Output (PG)
      7. 9.3.7 Thermal Shutdown
    4. 9.4 Device Functional Modes
      1. 9.4.1 Pulse Width Modulation (PWM) Operation
      2. 9.4.2 Power Save Mode Operation (PWM/PFM)
      3. 9.4.3 100% Duty-Cycle Operation
      4. 9.4.4 Current Limit and Short Circuit Protection
      5. 9.4.5 Foldback Current Limit and Short Circuit Protection
      6. 9.4.6 Output Discharge
      7. 9.4.7 Soft Start / Tracking (SS/TR)
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Programming the Output Voltage
      2. 10.1.2 External Component Selection
        1. 10.1.2.1 Inductor Selection
      3. 10.1.3 Capacitor Selection
        1. 10.1.3.1 Input Capacitor
        2. 10.1.3.2 Output Capacitor
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 System Examples
      1. 10.3.1 Fixed Output Voltage Versions
      2. 10.3.2 Voltage Tracking
      3. 10.3.3 Synchronizing to an External Clock
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13器件和文档支持
    1. 13.1 器件支持
      1. 13.1.1 第三方产品免责声明
    2. 13.2 文档支持
      1. 13.2.1 相关文档
    3. 13.3 相关链接
    4. 13.4 接收文档更新通知
    5. 13.5 支持资源
    6. 13.6 商标
    7. 13.7 静电放电警告
    8. 13.8 Glossary
  14. 14机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
  • RWY|9
散热焊盘机械数据 (封装 | 引脚)
订购信息

Voltage Tracking

The TPS6281x-Q1 follows the voltage applied to the SS/TR pin. A voltage ramp on SS/TR to 0.6 V ramps the output voltage according to the 0.6 V feedback voltage.

Tracking the 3.3 V of device 1, such that both rails reach their target voltage at the same time, requires a resistor divider on SS/TR of device 2 equal to the output voltage divider of device 1. The output current of 2.5 µA on the SS/TR pin causes an offset voltage on the resistor divider formed by R5 and R6. The equivalent resistance of R5 // R6, so it must be kept below 15 kΩ. The current from SS/TR causes a slightly higher voltage across R6 than 0.6 V, which is desired because device 2 switches to its internal reference as soon as the voltage at SS/TR is higher than 0.6 V.

In case both devices need to run in forced PWM mode, it is recommended to tie the MODE pin of device 2 to the output voltage or the power good signal of device 1, the master device. The TPS6281x-Q1 has a duty cycle limitation defined by the minimum on-time. For tracking down to low output voltages, device 2 cannot follow once the minimum duty cycle is reached. Enabling PFM mode while tracking is in progress allows you to ramp down the output voltage close to 0 V.

TPS62810-Q1 TPS62811-Q1 TPS62812-Q1 TPS62813-Q1 Orbea_typicalApp_tracking_3V3_1V8.gifFigure 62. Schematic for Output Voltage Tracking
TPS62810-Q1 TPS62811-Q1 TPS62812-Q1 TPS62813-Q1 TPS62810_PWM_tracking3V3_1V8_ds.gifFigure 63. Scope Plot for Output Voltage Tracking