ZHCSAC5D October   2012  – March 2017 TPS54340

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed Frequency PWM Control
      2. 7.3.2  Slope Compensation Output Current
      3. 7.3.3  Pulse Skip Eco-mode
      4. 7.3.4  Low Dropout Operation and Bootstrap Voltage (BOOT)
      5. 7.3.5  Error Amplifier
      6. 7.3.6  Adjusting the Output Voltage
      7. 7.3.7  Enable and Adjusting Undervoltage Lockout
      8. 7.3.8  Internal Soft-Start
      9. 7.3.9  Constant Switching Frequency and Timing Resistor (RT/CLK) Terminal)
      10. 7.3.10 Accurate Current Limit Operation and Maximum Switching Frequency
      11. 7.3.11 Synchronization to RT/CLKTerminal
      12. 7.3.12 Overvoltage Protection
      13. 7.3.13 Thermal Shutdown
      14. 7.3.14 Small Signal Model for Loop Response
      15. 7.3.15 Simple Small Signal Model for Peak Current Mode Control
      16. 7.3.16 Small Signal Model for Frequency Compensation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation with VIN < 4.5 V (Minimum VIN)
      2. 7.4.2 Operation with EN Control
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Buck Converter
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedures
          1. 8.2.1.2.1  Custom Design with WEBENCH Tools
          2. 8.2.1.2.2  Selecting the Switching Frequency
          3. 8.2.1.2.3  Output Inductor Selection (LO)
          4. 8.2.1.2.4  Output Capacitor
          5. 8.2.1.2.5  Catch Diode
          6. 8.2.1.2.6  Input Capacitor
          7. 8.2.1.2.7  Bootstrap Capacitor Selection
          8. 8.2.1.2.8  Undervoltage Lockout Set Point
          9. 8.2.1.2.9  Output Voltage and Feedback Resistors Selection
          10. 8.2.1.2.10 Minimum VIN
          11. 8.2.1.2.11 Compensation
          12. 8.2.1.2.12 Discontinuous Conduction Mode and Eco-mode Boundary
          13. 8.2.1.2.13 Power Dissipation
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Inverting Power
      3. 8.2.3 Split Rail Power Supply
    3. 8.3 WEBENCH Power Designer
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
      1. 10.2.1 Estimated Circuit Area
  11. 11器件和文档支持
    1. 11.1 文档支持
      1. 11.1.1 使用 WEBENCH 工具定制设计方案
      2. 11.1.2 接收文档更新通知
      3. 11.1.3 相关文档　
    2. 11.2 商标
    3. 11.3 社区资源
    4. 11.4 静电放电警告
    5. 11.5 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6 Specifications

6.1 Absolute Maximum Ratings(1)

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Input voltage VIN –0.3 45 V
EN –0.3 8.4
BOOT 53
FB –0.3 3
COMP –0.3 3
RT/CLK –0.3 3.6
Output voltage BOOT-SW 8 V
SW –0.6 45
SW, 10-ns Transient –2 45
Operating junction temperature –40 150 °C
Storage temperature, TSTG –65 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
VESD (1) Human Body Model (HBM) ESD Stress Voltage (2) ±2000 V
Charged Device Model (HBM) ESD Stress Voltage (3) ±500
(1) Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges into the device.
(2) Level listed above is the passing level per ANSI/ESDA/JEDEC JS-001. JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process. terminals listed as 1000V may actually have higher performance.
(3) Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process. terminals listed as 250V may actually have higher performance.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VIN Supply input voltage (1) VO + VDO 42 V
VO Output voltage 0.8 41.1 V
IO Output current 0 3.5 A
TJ Junction Temperature –40 150 °C
(1) See Equation 1

6.4 Thermal Information

THERMAL METRIC(1)(2) TPS54340 UNIT
DDA (8 PINS)
θJA Junction-to-ambient thermal resistance (standard board) 42.0 °C/W
ψJT Junction-to-top characterization parameter 5.9 °C/W
ψJB Junction-to-board characterization parameter 23.4 °C/W
θJCtop Junction-to-case(top) thermal resistance 45.8 °C/W
θJCbot Junction-to-case(bottom) thermal resistance 3.6 °C/W
θJB Junction-to-board thermal resistance 23.4 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
(2) Power rating at a specific ambient temperature TA should be determined with a junction temperature of 150°C. This is the point where distortion starts to substantially increase. See power dissipation estimate in application section of this data sheet for more information.

6.5 Electrical Characteristics

TJ = –40°C to 150°C, VIN = 4.5 V to 42 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE (VIN TERMINAL)
Operating input voltage 4.5 42 V
Internal undervoltage lockout threshold Rising 4.1 4.3 4.48 V
Internal undervoltage lockout threshold hysteresis 325 mV
Shutdown supply current EN = 0 V, 25°C, 4.5 V ≤ VIN ≤ 42 V 1.3 3.5 μA
Operating: nonswitching supply current FB = 0.9 V, TA = 25°C 146 175
ENABLE AND UVLO (EN TERMINAL)
Enable threshold voltage No voltage hysteresis, rising and falling 1.1 1.2 1.3 V
Input current Enable threshold +50 mV –4.6 μA
Enable threshold –50 mV –0.58 –1.2 -1.8
Hysteresis current –2.2 –3.4 -4.5 μA
VOLTAGE REFERENCE
Voltage reference 0.792 0.8 0.808 V
HIGH-SIDE MOSFET
On-resistance VIN = 12 V, BOOT-SW = 6 V 92 190 mΩ
ERROR AMPLIFIER
Input current 50 nA
Error amplifier transconductance (gM) –2 μA < ICOMP < 2 μA, VCOMP = 1 V 350 μS
Error amplifier transconductance (gM) during soft-start –2 μA < ICOMP < 2 μA, VCOMP = 1 V, VFB = 0.4 V 77 μS
Error amplifier dc gain VFB = 0.8 V 10,000 V/V
Min unity gain bandwidth 2500 kHz
Error amplifier source/sink V(COMP) = 1 V, 100 mV overdrive ±30 μA
COMP to SW current transconductance 12 A/V
CURRENT LIMIT
Current limit threshold All VIN and temperatures, Open Loop(1) 4.5 5.5 6.8 A
All temperatures, VIN = 12 V, Open Loop(1) 4.5 5.5 6.25
VIN = 12 V, TA = 25°C, Open Loop(1) 5.2 5.5 5.85
THERMAL SHUTDOWN
Thermal shutdown 176 °C
Thermal shutdown hysteresis 12 °C
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK TERMINAL)
Switching frequency range using RT mode 100 2500 kHz
fSW Switching frequency RT = 200 kΩ 450 500 550 kHz
Switching frequency range using CLK mode 160 2300 kHz
RT/CLK high threshold 1.55 2 V
RT/CLK low threshold 0.5 1.2 V
(1) Open Loop current limit measured directly at the SW terminal and is independent of the inductor value and slope compensation.

6.6 Timing Requirements

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ENABLE AND UVLO (EN TERMINAL)
Enable to COMP active VIN = 12 V , TA = 25°C 540 µs
INTERNAL SOFT-START TIME
Soft-Start Time fSW = 500 kHz, 10% to 90% 2.1 ms
Soft-Start Time fSW = 2.5 MHz, 10% to 90% 0.42 ms
HIGH-SIDE MOSFET
Minimum controllable on time VIN = 12 V, TA = 25°C 135 ns
CURRENT LIMIT
Current limit threshold delay 60 ns
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK TERMINAL)
Minimum CLK input pulse width 15 ns
RT/CLK falling edge to SW rising edge delay Measured at 500 kHz with RT resistor in series 55 ns
PLL lock in time Measured at 500 kHz 78 μs

6.7 Typical Characteristics

TPS54340 G001_SLVSBB4.png
VIN = 12V
Figure 1. On Resistance vs Junction Temperature
TPS54340 G003_SLVSBK0.png
VIN = 12 V
Figure 3. Switch Current Limit vs Junction Temperature
TPS54340 C026_SLVSBN0.png
VIN = 12 V
Figure 2. Voltage Reference vs Junction Temperature
TPS54340 G004_slvsBK0.gif
VIN = 12V
Figure 4. Switch Current Limit vs Input Voltage
TPS54340 C029_SLVSBN0.png
VIN = 12 V RT = 200 kΩ
Figure 5. Switching Frequency vs Junction Temperature
TPS54340 G007_SLVSBB4.png
VIN = 12V
Figure 7. Switching Frequency vs RT/CLK Resistance
High Frequency Range
TPS54340 C033_SLVSBN0.png
VIN = 12 V
Figure 9. EA Transconductance During Soft-Start vs Junction Temperature
TPS54340 C036_SLVSBN0.png
VIN = 5 V IEN = Threshold +50 mV
Figure 11. EN Terminal Current vs Junction Temperature
TPS54340 C037_SLVSBN0.png
VIN = 12 V
Figure 13. EN Terminal Current Hysteresis vs Junction Temperature
TPS54340 C039_SLVSBN0.png
VIN = 12 V
Figure 15. Shutdown Supply Current vs Junction Temperature
TPS54340 C041_SLVSBN0.png
VIN = 12 V
Figure 17. VIN Supply Current vs Junction Temperature
TPS54340 G018_SLVSBB4.png Figure 19. BOOT-SW UVLO vs Junction Temperature
TPS54340 C045_SLVSBN0.png
VIN = 12 V TJ = 25°C
Figure 21. Soft-Start Time vs Switching Frequency
TPS54340 C030_SLVSBN0.png
ƒsw (kHz) = 92417 x RT (kΩ) -0.991
RT (kΩ) = 101756 x ƒsw (kHz) -1.008
Figure 6. Switching Frequency vs RT/CLK Resistance
Low Frequency Range
TPS54340 C032_SLVSBN0.png
VIN = 12 V
Figure 8. EA Transconductance vs Junction Temperature
TPS54340 C034_SLVSBN0.png
VIN = 12 V
Figure 10. EN Terminal Voltage vs Junction Temperature
TPS54340 G012_SLVSBK0.gif
VIN = 12 V IEN = Threshold +50 mV
Figure 12. EN Terminal Current vs Junction Temperature
TPS54340 G013_SLVSBB4.png
VIN = 12V
Figure 14. Switching Frequency vs FB
TPS54340 C040_SLVSBN0.png
TJ = 25°C
Figure 16. Shutdown Supply Current vs Input Voltage (VIN)
TPS54340 G018_slvsBK0.gif
TJ = 25°C
Figure 18. VIN Supply Current vs Input Voltage
TPS54340 G019_SLVSBB4.png Figure 20. Input Voltage UVLO vs Junction Temperature