SLVS875C January   2009  – November 2014 TPS54332

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Simplified Schematic
      2.      Efficiency
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics: Characterization Curves
    8. 6.8 Typical Characteristics: Supplemental Application Curves
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed Frequency PWM Control
      2. 7.3.2  Voltage Reference (Vref)
      3. 7.3.3  Bootstrap Voltage (BOOT)
      4. 7.3.4  Enable and Adjustable Input Undervoltage Lockout (VIN UVLO)
      5. 7.3.5  Programmable Slow-Start Using SS Pin
      6. 7.3.6  Error Amplifier
      7. 7.3.7  Slope Compensation
      8. 7.3.8  Current Mode Compensation Design
      9. 7.3.9  Overcurrent Protection and Frequency Shift
      10. 7.3.10 Overvoltage Transient Protection
      11. 7.3.11 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation With VIN < 3.5 V
      2. 7.4.2 Operation With EN Control
      3. 7.4.3 Eco-Mode
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Switching Frequency
        2. 8.2.2.2  Output Voltage Set Point
        3. 8.2.2.3  Input Capacitors
        4. 8.2.2.4  Output Filter Components
        5. 8.2.2.5  Inductor Selection
        6. 8.2.2.6  Capacitor Selection
        7. 8.2.2.7  Compensation Components
        8. 8.2.2.8  Bootstrap Capacitor
        9. 8.2.2.9  Catch Diode
        10. 8.2.2.10 Output Voltage Limitations
        11. 8.2.2.11 Power Dissipation Estimate
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Estimated Circuit Area
    4. 10.4 Electromagnetic Interference (EMI) Considerations
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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Layout Guidelines

The VIN pin should be bypassed to ground with a low-ESR, ceramic bypass capacitor. Take care to minimize the loop area formed by the bypass capacitor connections, the VIN pin, and the anode of the catch diode. The typical recommended bypass capacitance is 10-μF ceramic with a X5R or X7R dielectric and the optimum placement is closest to the VIN pins and the source of the anode of the catch diode. See Figure 23 for a PCB layout example. The GND D pin should be tied to the PCB ground plane at the pin of the IC. The source of the low-side MOSFET should be connected directly to the top-side PCB ground area used to tie together the ground sides of the input and output capacitors, as well as the anode of the catch diode. The PH pin should be routed to the cathode of the catch diode and to the output inductor. Since the PH connection is the switching node, the catch diode and output inductor should be located very close to the PH pins, and the area of the PCB conductor minimized to prevent excessive capacitive coupling. For operation at full rated load, the top-side ground area must provide adequate heat dissipating area. The TPS54332 uses a fused lead frame so that the GND pin acts as a conductive path for heat dissipation from the die. Many applications have larger areas of internal or back side ground plane available, and the top-side ground area can be connected to these areas using multiple vias under or adjacent to the device to help dissipate heat. The additional external components can be placed approximately as shown. It may be possible to obtain acceptable performance with alternate layout schemes, however this layout has been shown to produce good results and is intended as a guideline.