A characteristic of peak current mode control results in a condition where the current control loop can exhibit instability. This results in alternating long and short pulses from the pulse width modulator. The voltage loop maintains regulation and does not oscillate, but the output ripple voltage increases. The condition occurs only when the converter is operating in continuous conduction mode and the duty cycle is 50% or greater. The cause of this condition is described in the Modeling, Analysis and Compensation of the Current-Mode Converter Application Report. The remedy for this condition is to apply a compensating ramp from the oscillator to the signal going to the pulse width modulator. In the TPS40210 and TPS40211, the oscillator ramp is applied in a fixed amount to the pulse width modulator. The slope of the ramp is given in Equation 17.
To ensure that the converter does not enter into subharmonic instability, the slope of the compensating ramp signal must be at least half of the down slope of the current ramp signal. Since the compensating ramp is fixed in the TPS40210 and TPS40211, this places a constraint on the selection of the current sense resistor.
The down slope of the current sense wave form at the pulse width modulator is described in Equation 18.
Since the slope compensation ramp must be at least half, and preferably equal to the down slope of the current sense waveform seen at the pulse width modulator, a maximum value is placed on the current sense resistor when operating in continuous mode at 50% duty cycle or greater. For design purposes, some margin should be applied to the actual value of the current sense resistor. As a starting point, the actual resistor chosen should be 80% or less that the value calculated in Equation 19. This equation calculates the resistor value that makes the slope compensation ramp equal to one half of the current ramp downslope. Values no more than 80% of this result would be acceptable.
It is possible to increase the voltage compensation ramp slope by connecting the VDD pin to the output voltage of the converter instead of the input voltage as shown in Figure 26. This can help in situations where the converter design calls for a large ripple current value in relation to the desired output current limit setting.
Connecting the VDD pin to the output voltage of the converter affects the start-up voltage of the converter since the controller undervoltage lockout (UVLO) circuit monitors the VDD pin and senses the input voltage less the diode drop before start-up. The effect is to increase the start-up voltage by the value of the diode voltage drop.
If an acceptable RISNS value is not available, the next higher value can be used and the signal from the resistor divided down to an acceptable level by placing another resistor in parallel with CIFLT.