SLVS933C July   2009  – April 2016 TPS23753A

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Product Information
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: Controller Section Only
    6. 7.6 Electrical Characteristics: PoE and Control
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Pin Description
        1. 8.3.1.1  APD
        2. 8.3.1.2  BLNK
        3. 8.3.1.3  CLS
        4. 8.3.1.4  CS
        5. 8.3.1.5  CTL
        6. 8.3.1.6  DEN
        7. 8.3.1.7  FRS
        8. 8.3.1.8  GATE
        9. 8.3.1.9  RTN
        10. 8.3.1.10 VB
        11. 8.3.1.11 VC
        12. 8.3.1.12 VDD
        13. 8.3.1.13 VDD1
        14. 8.3.1.14 VSS
    4. 8.4 Device Functional Modes
      1. 8.4.1  Threshold Voltages
      2. 8.4.2  PoE Start-Up Sequence
      3. 8.4.3  Detection
      4. 8.4.4  Hardware Classification
      5. 8.4.5  Maintain Power Signature (MPS)
      6. 8.4.6  TPS23753A Operation
        1. 8.4.6.1 Start-Up and Converter Operation
        2. 8.4.6.2 PD Self-Protection
        3. 8.4.6.3 Converter Controller Features
      7. 8.4.7  Special Switching MOSFET Considerations
      8. 8.4.8  Thermal Considerations
      9. 8.4.9  Blanking - RBLNK
      10. 8.4.10 Current Slope Compensation
      11. 8.4.11 FRS and Synchronization
      12. 8.4.12 Adapter ORing
      13. 8.4.13 Protection
      14. 8.4.14 Frequency Dithering for Conducted Emissions Control
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Community Resource
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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7 Specifications

7.1 Absolute Maximum Ratings

Voltage are with respect to VSS (unless otherwise noted)(1) per Figure 25 per Table 1
MIN MAX UNIT
VI Input voltage VDD, VDD1, DEN, RTN(2) –0.3 100 V
VDD1 to RTN –0.3 100
CLS(3) –0.3 6.5
[APD, BLNK(3), CTL, FRS(3), VB(3)] to RTN –0.3 6.5
CS to RTN –0.3 VB
VC to RTN –0.3 19
GATE(3) to RTN –0.3 VC + 0.3
Sourcing current VB Internally limited mA
Average sourcing or sinking current GATE 25 mARMS
TJ Operating junction temperature –40 to Internally Limited °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) IRTN = 0 for VRTN > 80 V.
(3) Do not apply voltage to these pins.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
IEC 61000-4-2 contact discharge(3) ±8000
IEC 61000-4-2 air-gap discharge(3) ±15000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(3) Surges per EN61000-4-2, 1999 applied between RJ-45 and output ground and between adapter input and output ground of the TPS23753AEVM-001 (HPA304-001) evaluation module (documentation available on the web). These were the test levels, not the failure threshold.

7.3 Recommended Operating Conditions

Voltage with respect to VSS (unless otherwise noted)
MIN NOM MAX UNIT
VI Input voltage, VDD, VDD1, RTN 0 57 V
Input voltage, VC to RTN 0 18
Input voltage, APD, CTL to RTN 0 VB
Input voltage, CS to RTN 0 2
RTN current (TJ ≤ 125°C) 350 mA
VB sourcing current 0 2.5 5 mA
VB capacitance 0.08 0.1 μF
RBLNK 0 350
Synchronization pulse width input (when used) 25 ns
TJ Operating junction temperature –40 125 °C

7.4 Thermal Information

THERMAL METRIC(1) TPS23753A UNIT
PW (TSSOP)
14 PINS
RθJA Junction-to-ambient thermal resistance 106.6 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 32.9 °C/W
RθJB Junction-to-board thermal resistance 49.1 °C/W
ψJT Junction-to-top characterization parameter 1.9 °C/W
ψJB Junction-to-board characterization parameter 48.4 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics: Controller Section Only

Unless otherwise noted: CS = APD = CTL = RTN, GATE open, RFRS = 60.4 kΩ, RBLNK = 249 kΩ, CVB = CVC = 0.1 μF, RDEN = 24.9 kΩ, RCLS open, VVDD-VSS = 48 V, VVDD1-RTN = 48 V, 8.5 V ≤ VVC-RTN ≤ 18 V, –40°C ≤ TJ ≤ 125°C [VSS = RTN and VDD = VDD1] or [VSS = RTN = VDD], all voltages referred to RTN. Typical specifications are at 25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VC
UVLO_1 Undervoltage lockout VC rising 8.65 9 9.3 V
UVLO_H Hysteresis(1) 3.3 3.5 3.7
Operating current VC = 12 V, CTL = VB 0.4 0.58 0.85 mA
tST Start-up time, CVC = 22 μF VDD1 = 10.2 V, VVC(0) = 0 V 50 85 175 V
VDD1 = 35 V, VVC(0) = 0 V 30 48 85
Start-up current source - IVC VDD1 = 10.2 V, VVC = 8.6 V 0.44 1.06 1.8 mA
VDD1 = 48 V, VVC = 0 V 2.5 4.3 6
VB
Voltage 6.5 V ≤ VC ≤ 18 V, 0 ≤ IVB ≤ 5 mA 4.75 5.1 5.25 V
FRS
Switching frequency CTL= VB, Measure GATE 223 248 273 kHz
RFRS = 60.4 kΩ
DMAX Duty cycle CTL= VB, Measure GATE 76% 78.5% 81%
VSYNC Synchronization Input threshold 2 2.2 2.4 V
CTL
VZDC 0% duty cycle threshold VCTL ↓ until GATE stops 1.3 1.5 1.7 V
Soft-start period Interval from switching start to VCSMAX 400 800 μs
Input resistance 70 100 145
BLNK
Blanking delay In addition to t1 35 52 75 ns
BLNK = RTN
RBLNK = 49.9 kΩ 41 52 63
CS
VCSMAX Maximum threshold voltage VCTL = VB, VCS ↑ until GATE duty cycle drops 0.5 0.55 0.6 V
t1 Turnoff delay VCS = 0.65 V 25 41 60 ns
VSLOPE Internal slope compensation voltage Peak voltage at maximum duty cycle, referred to CS 90 118 142 mV
ISL_EX Peak slope compensation current VCTL = VB, ICS at maximum duty cycle (ac component) 30 42 54 μA
Bias current (sourcing) Gate high, DC component of CS current 2 3 4.2 μA
GATE
Source current VCTL = VB, VC = 12 V, GATE high, Pulsed measurement 0.3 0.46 0.6 A
Sink current VCTL = VB, VC = 12 V, GATE low, Pulsed measurement 0.5 0.79 1.1 A
APD
VAPDEN Threshold voltage VAPD 1.42 1.5 1.58 V
VAPDH Hysteresis(1) 0.28 0.3 0.32
THERMAL SHUTDOWN
Turnoff temperature 135 145 155 °C
Hysteresis(2) 20 °C
(1) The hysteresis tolerance tracks the rising threshold for a given device.
(2) These parameters are provided for reference only, and do not constitute part of TI's published device specifications for purposes of TI's product warranty.

7.6 Electrical Characteristics: PoE and Control

Unless otherwise noted: CS = APD = CTL = RTN, GATE open, RFRS = 60.4 kΩ, RBLNK = 249 kΩ, CVB = CVC = 0.1 μF, RDEN = 24.9 kΩ, RCLS open, VVDD-VSS = 48 V, VVDD1-RTN = 48 V, 8.5 V ≤ VVC-RTN ≤ 18 V, –40°C ≤ TJ ≤ 125°C [VSS = RTN and VDD = VDD1] or [VSS = RTN = VDD], all voltages referred to RTN. [VDD = VDD1] or [VDD1 = RTN], VVC-RTN = 0 V, all voltages referred to VSS. Typical specifications are at 25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DEN (DETECTION) (VDD = VDD1 = RTN = VSUPPLY POSITIVE)
Detection current Measure ISUPPLY 62 64.3 66.5 μA
VDD = 1.6 V
VDD = 10 V 399 406 413
Detection bias current VDD = 10 V, DEN open, Measure ISUPPLY 5.2 12 μA
VPD_DIS Hotswap disable threshold 3 4 5 V
Ilkg DEN leakage current VDEN = VDD = 57 V, Float VDD1 and RTN, Measure IDEN 0.1 5 μA
CLS (CLASSIFICATION) (VDD = VDD1 = RTN = VSUPPLY POSITIVE)
ICLS Classification current 13 V ≤ VDD ≤ 21 V, Measure ISUPPLY 1.8 2.14 2.4 mA
RCLS = 1270 Ω 1.8 2.14 2.4
RCLS = 243 Ω 9.9 10.6 11.3
RCLS = 137 Ω 17.6 18.6 19.4
RCLS = 90.9 Ω 26.5 27.9 29.3
RCLS = 63.4 Ω 38 39.9 42
VCL_ON Classification regulator lower threshold Regulator turns on, VDD rising 10 11.7 13 V
VCL_HYS Hysteresis(1) 1.9 2.05 2.2
VCU_OFF Classification regulator upper threshold Regulator turns off, VDD rising 21 22 23 V
VCU_HYS Hysteresis(1) 0.5 0.77 1
Ilkg Leakage current VDD = 57 V, VCLS = 0 V, DEN = VSS, Measure ICLS 1 μA
RTN (PASS DEVICE) (VDD1 = RTN)
ON-resistance 0.7 1.2 Ω
Current limit VRTN = 1.5 V, VDD = 48 V, Pulsed Measurement 405 450 505 mA
Inrush limit VRTN = 2 V, VDD: 0 V → 48 V, Pulsed Measurement 100 140 180 mA
Foldback voltage threshold VDD rising 11 12.3 13.6 V
Ilkg Leakage current VDD = VRTN = 100 V, DEN = VSS 40 μA
UVLO
UVLO_R Undervoltage lockout threshold VDD rising 33.9 35 36.1 V
UVLO_H Hysteresis (1) 4.4 4.55 4.7
THERMAL SHUTDOWN
Turnoff temperature 135 145 155 °C
Hysteresis(2) 20 °C
(1) The hysteresis tolerance tracks the rising threshold for a given device.
(2) These parameters are provided for reference only.

7.7 Typical Characteristics

TPS23753A ivdd_vdd_lvs853.gif
Figure 1. Detection Bias Current vs Voltage
TPS23753A st_time_tj_lvs853.gif
Figure 3. Converter Start Time vs Temperature
TPS23753A ivc_tj_lvs853.gif
Figure 5. Controller Bias Current vs Temperature
TPS23753A swf_tj_lvs933.gif
Figure 7. Switching Frequency vs Temperature
TPS23753A mdc_tj_lvs853.gif
Figure 9. Maximum Duty Cycle vs Temperature
TPS23753A islope_tj_lvs853.gif
Figure 11. Current Slope Compensation Current vs Temperature
TPS23753A blank_rblnk_lvs853.gif
Figure 13. Blanking Period vs RBLNK
TPS23753A poe_tj_lvs853.gif
Figure 2. PoE Current Limit vs Temperature
TPS23753A icc_vdd_lvs853.gif
Figure 4. Converter Start-Up Source Current vs VVDD1
TPS23753A vca_vcv_lvs853.gif
Figure 6. Controller Bias Current vs Voltage
TPS23753A swf_pf_lvs853.gif
Figure 8. Switching Frequency vs Programmed Resistance
TPS23753A vslope_tj_lvs853.gif
Figure 10. Current Slope Compensation Voltage vs Temperature
TPS23753A blnk_tj_lvs933.gif
Figure 12. Blanking Period vs Temperature