SLVS933C July 2009 – April 2016 TPS23753A
The TPS23753A device has a PoE that contains all of the features needed to implement an IEEE802.3at Type 1 powered device (PD) such as detection, classification, and 140-mA inrush current mode DC-DC controller optimized specifically for isolated converters. The TPS23753A device integrates a low 0.7-Ω internal switch to allow for up to 405 mA of continuous current through the PD during normal operation. The TPS23753A device contains several protection features such as thermal shutdown, current limit foldback, and a robust 100-V internal switch.
See Figure 25 for component reference designators (RCS for example ), and Electrical Characteristics: Controller Section Only for values denoted by reference (VCSMAX for example). Electrical Characteristic values take precedence over any numerical values used in the following sections.
APD forces power to come from an external adapter connected from VDD1 to RTN by opening the hotswap switch. TI recommends using a resistor divider. The divider provides ESD protection, leakage discharge for the adapter ORing diode, and input voltage qualification. Voltage qualification assures the adapter can support the PD before the PoE current is cut off.
The CLS output is disabled when a voltage above VAPDEN is applied to the APD pin.
Place the APD pulldown resistor adjacent to the APD pin.
APD must be tied to RTN when not used.
Blanking provides an interval between the gate drive going high and the current comparator on CS actively monitoring the input. This delay allows the normal turnon current transient (spike) to subside before the comparator is active, preventing undesired short duty cycles and premature current limiting.
Connect BLNK to RTN to obtain the internally set blanking period. Connect a resistor from BLNK to RTN for a programmable blanking period. The relationship between the desired blanking period and the programming resistor is defined by Equation 3.
Place the resistor adjacent to the BLNK pin when it is used.
Connect a resistor from CLS to VSS to program the classification current per IEEE 802.3-at. The PD power ranges and corresponding resistor values are listed in Table 1. The power assigned must correspond to the maximum average power drawn by the PD during operation. The TPS23753A supports class 0 – 3 power levels.
The current-sense input for the DC-DC converter should be connected to the high side of the current-sense resistor of the switching MOSFET. The current-limit threshold, VCSMAX, defines the voltage on CS above which the GATE ON-time are terminated regardless of the voltage on CTL.
The TPS23753A provides internal slope compensation to stabilize the current mode control loop. If the provided slope is not sufficient, the effective slope may be increased by addition of RS per Figure 20.
Routing between the current-sense resistor and the CS pin must be short to minimize cross-talk from noisy traces such as the gate drive signal.
CTL is the voltage control loop input to the PWM (pulse width modulator). Pulling VCTL below VZDC causes GATE to stop switching. Increasing VCTL above VZDC raises the switching MOSFET programmed peak current. The maximum (peak) current is requested at approximately VZDC + (2 × VCSMAX). The AC gain from CTL to the PWM comparator is 0.5.
Use VB as a pullup source for CTL.
Connect a 24.9-kΩ resistor from DEN to VDD to provide the PoE detection signature. DEN goes to a high impedance state when not in the detection voltage range. Pulling DEN to VSS during powered operation causes the internal hotswap MOSFET and class regulator to turn off.
Connect a resistor from FRS to RTN to program the converter switching frequency. Select the resistor using Equation 4.
The converter may be synchronized to a frequency above its maximum free-running frequency by applying short AC-coupled pulses into the FRS pin. More information is provided in Application and Implementation.
The FRS pin is high impedance. Keep the connections short and apart from potential noise sources.
Gate drive output for the DC-DC converter switching MOSFET.
RTN is internally connected to the drain of the PoE hotswap MOSFET, and the DC-DC controller return. RTN must be treated as a local reference plane (ground plane) for the DC-DC controller and converter primary to maintain signal integrity.
VB is an internal 5-V control rail that must be bypassed by a 0.1-μF capacitor to RTN. VB should be used to bias the feedback optocoupler.
VC is the bias supply for the DC-DC controller. The MOSFET gate driver runs directly from VC. VB is regulated down from VC, and is the bias voltage for the rest of the converter control. A start-up current source from VDD1 to VC is controlled by a comparator with hysteresis to implement a bootstrap start-up of the converter. VC must be connected to a bias source, such as a converter auxiliary output, during normal operation.
A minimum 0.22-μF capacitor, located adjacent to the VC pin, must be connected from VC to RTN to bypass the gate driver. A larger total capacitance is required for start-up.
Positive input power rail for PoE control that is derived from the PoE. VDD should be bypassed to VSS with a
0.1-μF (X7R,10%) capacitor as required by the standard. A transient suppressor (Zener) diode, must be connected from VDD to VSS to protect against overvoltage transients.
Source of DC-DC converter start-up current. Connect to VDD for most applications. VDD1 may be isolated by a diode from VDD to support PoE-priority operation.
VSS is the PoE input-power return side. It is the reference for the PoE interface circuits, and has a current-limited hotswap switch that connects it to RTN. VSS is clamped to a diode drop above RTN by the hotswap switch. A local VSS reference plane should be used to connect the input components and the VSS pin.
The following text is intended as an aid in understanding the operation of the TPS23753A, but it is not a substitute for the actual IEEE 802.3at standard. The IEEE 802.3at standard is an update to IEEE 802.3-2008 clause 33 (PoE), adding high-power options and enhanced classification.
Generally speaking, a device compliant to IEEE 802.3-2008 is referred to as a type 1 device, and devices with high power or enhanced classification is referred to as type 2 devices. The TPS23753A is intended to power type 1 devices (up to 13 W), and is fully compliant to IEEE 802.3at for hardware classes 0 - 3. Standards change and must always be referenced when making design decisions.
The IEEE 802.3at standard defines a method of safely powering a PD (powered device) over a cable, and then removing power if a PD is disconnected. The process proceeds through an idle state and three operational states of detection, classification, and operation. The PSE leaves the cable unpowered (idle state) while it periodically looks to see if something has been plugged in; this is referred to as detection. The low power levels used during detection are unlikely to damage devices not designed for PoE. If a valid PD signature is present, the PSE may inquire how much power the PD requires; this is referred to as (hardware) classification. Only Type 2 PSEs are required to do hardware classification. The PD may return the default 13-W current-encoded class, or one of four other choices. The PSE may then power the PD if it has adequate capacity. Once started, the PD must present the maintain power signature (MPS) to assure the PSE that it is still present. The PSE monitors its output for a valid MPS, and turns the port off if it loses the MPS. Loss of the MPS returns the PSE to the idle state. Figure 14 shows the operational states as a function of PD input voltage.
The PD input is typically an RJ-45 eight-lead connector which is referred to as the power interface (PI). PD input requirements differ from PSE output requirements to account for voltage drops in the cable and operating margin. The IEEE 802.3at standard uses a cable resistance of 20 Ω for type 1 devices to derive the voltage limits at the PD based on the PSE output voltage requirements. Although the standard specifies an output power of 15.4 W at the PSE, only 13 W is available at the PI due to the worst-case power loss in the cable. The PSE can apply voltage either between the RX and TX pairs (pins 1–2 and 3–6 for 10baseT or 100baseT), or between the two spare pairs (4–5 and 7–8). The PSE may only apply voltage to one set of pairs at a time. The PD uses input diode bridges to accept power from any of the possible PSE configurations. The voltage drops associated with the input bridges create a difference between the standard limits at the PI and the TPS23753A specifications.
The PSE is permitted to disconnect a PD if it draws more than its maximum class power over a one second interval. A Type 1 PSE compliant to IEEE 802.3at is required to limit current to between 400 mA and 450 mA during powered operation, and it must disconnect the PD if it draws this current for more than 75 ms. Class 0 and 3 PDs may draw up to 400-mA peak currents for up to 50 ms. The PSE may set lower output current limits based on the declared power requirements of the PD.
The TPS23753A has a number of internal comparators with hysteresis for stable switching between the various states as shown in Figure 14. Figure 15 relates the parameters in Electrical Characteristics: Controller Section Only and Electrical Characteristics: PoE and Control to the PoE states. The mode labeled idle between classification and operation implies that the DEN, CLS, and RTN pins are all high impedance.
The waveforms of Figure 16 demonstrate detection, classification, and start-up from a Type 1 PSE. The key waveforms shown are VVDD-VSS, VRTN-VSS, and IPI. IEEE 802.3at requires a minimum of two detection levels; however, four levels are shown in this example. Four levels guard against misdetection of a device when plugged in during the detection sequence.
The TPS23753A is in detection mode whenever VVDD-VSS is below the lower classification threshold. When the input voltage rises above VCL_ON, the DEN pin goes to an open-drain condition to conserve power. While in detection, RTN is high impedance, almost all the internal circuits are disabled, and the DEN pin is pulled to VSS. An RDEN of 24.9 kΩ (1%), presents the correct signature. It may be a small, low-power resistor because it only sees a stress of about 5 mW. A valid PD detection signature is an incremental resistance between 23.75 kΩ and 26.25 kΩ at the PI.
The detection resistance seen by the PSE at the PI is the result of the input bridge resistance in series with the parallel combination of RDEN and the TPS23753A bias loading. The incremental resistance of the input diode bridge may be hundreds of ohms at the very low currents drawn when 2.7 V is applied to the PI. The input bridge resistance is partially cancelled by the effective resistance of the TPS23753A during detection.
Hardware classification allows a PSE to determine the power requirements of a PD before starting, and helps with power management once power is applied. The maximum power entries in Table 1 determine the class the PD must advertise. A Type 1 PD may not advertise Class 4. The PSE may disconnect a PD if it draws more than its stated Class power. The standard permits the PD to draw limited current peaks; however, the average power requirement always applies.
Voltage from 14.5 V to 20.5 V is applied to the PD for up to 75 ms during hardware classification. A fixed output voltage is sourced by the CLS pin, causing a fixed current to be drawn from VDD through RCLS. The total current drawn from the PSE during classification is the sum of bias and RCLS currents. PD current is measured and decoded by the PSE to determine which of the five available classes is advertised (see Table 1). The TPS23753A disables classification above VCU_OFF to avoid excessive power dissipation. CLS voltage is turned off during PD thermal limit or when APD or DEN are active. The CLS output is inherently current-limited, but should not be shorted to VSS for long periods of time.
The MPS is an electrical signature presented by the PD to assure the PSE that it is still present after operating voltage is applied. A valid MPS consists of a minimum DC current of 10 mA (at a duty cycle of at least 75 ms on every 225 ms) and an AC impedance lower than 26.25 kΩ in parallel with 0.05 μF. The AC impedance is usually accomplished by the minimum CIN requirement of 5 μF. When APD or DEN are used to force the hotswap switch off, the DC MPS is not met. A PSE that monitors the DC MPS will remove power from the PD when this occurs. A PSE that monitors only the AC MPS may remove power from the PD.
The internal PoE undervoltage lockout (UVLO) circuit holds the hotswap switch off before the PSE provides full voltage to the PD. This prevents the converter circuits from loading the PoE input during detection and classification. The converter circuits discharges CIN, CVC, and CVB while the PD is unpowered. Thus VRTN-VDD will be a small voltage just after full voltage is applied to the PD, as seen in Figure 16.
The PSE drives the PI voltage to the operating range once it has decided to power up the PD. When VDD rises above the UVLO turnon threshold (VUVLO-R, approximately 35 V) with RTN high, the TPS23753A enables the hotswap MOSFET with an approximately 140-mA (inrush) current limit. See the waveforms of Figure 17 for an example. Converter switching is disabled while CIN charges and VRTN falls from VDD to nearly VSS; however, the converter start-up circuit is allowed to charge CVC. Once the inrush current falls about 10% below the inrush current limit, the PD control switches to the operational level (approximately 450 mA) and converter switching is permitted.
Converter switching is allowed if the PD is not in inrush and the VC UVLO circuit permits it. Continuing the start-up sequence shown in Figure 17, VVC rises as the start-up current source charges CVC and M1 switching is inhibited by the status of the VC UVLO. The VB regulator powers the internal converter circuits as VVC rises. Start-up current is turned off, converter switching is enabled, and a soft-start cycle starts when VVC exceeds UVLO1 (approximately 9 V). VVC falls as it powers both the internal circuits and the switching MOSFET gate. If the converter control-bias output rises to support VVC before it falls to UVLO1 – UVLO1H (approximately 5.5 V), a successful start-up occurs. Figure 17 shows a small droop in VVC while the output voltage rises smoothly and a successful start-up occurs.
If VVDD-VSS drops below the lower PoE UVLO (UVLOR – UVLOH, approximately 30.5 V), the hotswap MOSFET is turned off, but the converter still runs. The converter stops if VVC falls below the converter UVLO (UVLO1 – UVLOH, approximately 5.5 V), the hotswap is in inrush current limit, or 0% duty cycle is demanded by VCTL (VCTL < VZDC, approximately 1.5 V), or the converter is in thermal shutdown.
The PD section has the following self-protection functions.
The internal hotswap MOSFET is protected against output faults with a current limit and deglitched foldback. The PSE output cannot be relied on to protect the PD MOSFET against transient conditions, requiring the PD to provide fault protection. High stress conditions include converter output shorts, shorts from VDD1 to RTN, or transients on the input line. An overload on the pass MOSFET engages the current limit, with VRTN-VSS rising as a result. If VRTN rises above approximately 12 V for longer than approximately 400 μs, the current limit reverts to the inrush limit, and turns the converter off. The 400-μs deglitch feature prevents momentary transients from causing a PD reset, provided that recovery lies within the bounds of the hotswap and PSE protection. Figure 18 shows an example of recovery from a 15-V PSE rising voltage step. The hotswap MOSFET goes into current limit, overshooting to a relatively low current, recovers to 420-mA, full-current limit, and charges the input capacitor while the converter continues to run. The MOSFET did not go into foldback because VRTN-VSS was below 12 V after the 400-μs deglitch.
The PD control has a thermal sensor that protects the internal hotswap MOSFET. Conditions like start-up or operation into a VDD to RTN short cause high power dissipation in the MOSFET. An overtemperature shutdown (OTSD) turns off the hotswap MOSFET and class regulator, which are restarted after the device cools. The PD restarts in inrush current limit when exiting from a PD overtemperature event.
Pulling DEN to VSS during powered operation causes the internal hotswap MOSFET to turn off. This feature allows a PD with secondary-side adapter ORing to achieve adapter priority. Take care with synchronous converter topologies that can deliver power in both directions.
The hotswap switch is forced off under the following conditions:
The TPS23753A DC-DC controller implements a typical current-mode control as shown in Figure 19. Features include oscillator, overcurrent and PWM comparators, current-sense blanker, soft start, and gate driver. In addition, an internal current-compensation ramp generator, frequency synchronization logic, thermal shutdown, and start-up current source with control are provided.
The TPS23753A is optimized for isolated converters, and does not provide an internal error amplifier. Instead, the optocoupler feedback is directly fed to the CTL pin which serves as a current-demand control for the PWM and converter. There is an offset of VZDC (approximately 1.5 V) and 2:1 resistor divider between the CTL pin and the PWM. A VCTL below VZDC stops converter switching, while voltages above (VZDC + 2 × VCSMAX) does not increase the requested peak current in the switching MOSFET. Optocoupler biasing design is eased by this limited control range.
The internal start-up current source and control logic implement a bootstrap-type start-up. The start-up current source charges CVC from VDD1 when the converter is disabled (either by the PD control or the VC control), while operational power must come from a converter (bias winding) output. Loading on VC and VB must be minimal while CVC charges, otherwise the converter may never start. The optocoupler does not load VB when the converter is off. The converter shuts off when VC falls below its lower UVLO. This can happen when power is removed from the PD, or during a fault on a converter output rail. When one output is shorted, all the output voltages fall including the one that powers VC. The control circuit discharges VC until it hits the lower UVLO and turns off. A restart initiates as described in Start-Up and Converter Operation if the converter turns off and there is sufficient VDD1 voltage. This type of operation is sometimes referred to as hiccup mode, which provides robust output short protection by providing time-average heating reduction of the output rectifier.
Take care in the design of the transformer and VC bias circuit to obtain hiccup overload protection. Leading-edge voltage overshoot on the bias winding may cause VC to peak-charge, preventing the expected tracking with output voltage. RVC (Figure 25) is often required slow the peak charging. Good transformer bias-to-output-winding coupling results in reduced overshoot and better voltage tracking.
The start-up current source transitions to a resistance as (VDD1 – VC) falls below 7 V, but starts the converter from 12-V adapters within tST (VDD1 ≥ 10.2, tST approximately 85 ms). The converter starts from lower voltages, limited by the case when charge current equals the device bias current at voltage below the upper VC UVLO. The bootstrap source provides reliable start-up from widely varying input voltages, and eliminates the continual power loss of external resistors. The start-up current source does not charge above the maximum recommended VVC if the converter is disabled and there is sufficient VDD1 to charge higher.
The peak current limit does not have duty cycle dependency unless RS is used as shown in Figure 20 to increase slope compensation. This makes it easier to design the current limit to a fixed value.
The TPS23753A blanker timing is precise enough that the traditional R-C filters on CS can be eliminated. This avoids current-sense waveform distortion, which tends to get worse at light output loads. While the internally set blanking period is relatively precise, almost all converters require their own blanking period. The TPS23753A provides the BLNK pin to allow this programming. There may be some situations or designers that prefer an R-C approach. The TPS23753A provides a pulldown on CS during the GATE OFF-time to improve sensing when an R-C filter must be used. The CS input signal must be protected from nearby noisy signals like GATE drive and the MOSFET drain.
Converters require a soft start on the voltage error amplifier to prevent output overshoot on start-up. Figure 19 shows a common implementation of a secondary-side soft start that works with the typical TL431 error amplifier shown in Figure 25. This secondary-side error amplifier does not become active until there is sufficient voltage on the secondary. The TPS23753A provides a primary-side soft start, which persists long enough (approximately 800 μs) for secondary side voltage-loop soft start to take over; however, the actual start-up is typically shorter than this. The primary-side current-loop soft-start controls the switching MOSFET peak current by applying a slowly rising ramp voltage to a second PWM control input. The lower of the CTL and soft-start ramps controls the PWM comparator. Figure 17 shows an exaggerated handoff between the primary and secondary-side soft start that is most easily seen in the IPI waveform. The output voltage rises in a smooth monotonic fashion with no overshoot. The soft-start handoff in this example could have been optimized by decreasing the secondary-side soft-start period.
The DC-DC controller has an OTSD that can be triggered by heat sources including the VB regulator, GATE driver, bootstrap current source, and bias currents. The controller OTSD turns off VB, the GATE driver, resets the soft-start generator, and forces the VC control into an undervoltage state.
Take special care in selecting the converter switching MOSFET. The TPS23753A converter section has minimum VC operating voltage of approximately 5.5 V, which is reflected in the applied gate voltage. This occurs during an output overload, or towards the end of a (failed) bootstrap start-up. The MOSFET must be able to carry the anticipated peak fault current at this gate voltage.
Sources of nearby local PCB heating must be considered during the thermal design. Typical calculations assume that the TPS23753A is the only heat source contributing to the PCB temperature rise. It is possible for a normally operating TPS23753A device to experience an OTSD event if it is excessively heated by a nearby device.
The TPS23753A BLNK feature permits programming of the blanking period with specified tolerance. Selection of the blanking period is often empirical because it is affected by parasitics and thermal effects of every device between the gate-driver and output capacitors.
There is a critical range of blanking period that is bounded on the short side by erratic operation, and on the long side by potentially harmful switching-MOSFET and output rectifier currents during a short circuit. The minimum blanking period prevents the current limit and PWM comparators from being falsely triggered by the inherent current spike that occurs when the switching MOSFET turns on. The maximum blanking period is bounded by the ability of the output rectifier to withstand the currents experienced during a converter output short.
The TPS23753A provides a choice between internal fixed and programmable blanking periods. The blanking period is specified as an increase in the minimum GATE on time over the inherent gate driver and comparator delays. The default period (see Electrical Characteristics: Controller Section Only and Electrical Characteristics: PoE and Control) is selected by connecting BLNK to RTN, and the programmable period is set with a resistor from BLNK to RTN using Equation 5.
For example, a 100-ns period is programmed by a 100-kΩ resistor. For a brand-new design, TI recommends designing an initial blanking period of 125 ns. This period must be turned when the converter is operational.
Current-mode control requires addition of a compensation ramp to the sensed inductor (flyback transformer) current for stability at duty cycles near and over 50%. The TPS23753A has a maximum duty cycle limit of 78%, permitting the design of wide input-range flyback converters with a lower voltage stress on the output rectifiers. While the maximum duty cycle is 78%, converters may be designed that run at duty cycles well below this for a narrower, 36-V to 57-V range. The TPS23753A provides a fixed internal compensation ramp that suffices for most applications. RS (see Figure 20) may be used if the internally provided slope compensation is not enough. It works with ramp current (IPK = ISL-EX, approximately 40 μA) that flows out of the CS pin when the MOSFET is on. The IPK specification does not include the approximately 3-μA fixed current that flows out of the CS pin.
Most current-mode control papers and application notes define the slope values in terms of VPP/TS (peak ramp voltage / switching period); however, Electrical Characteristics: Controller Section Only specifies the slope peak (VSLOPE) based on the maximum duty cycle. Assuming that the desired slope, VSLOPE-D (in mV/period), is based on the full period, compute RS per Equation 6 where VSLOPE, DMAX, and ISL-EX are from Electrical Characteristics: Controller Section Only with voltages in mV, current in μA, and the duty cycle is unitless (for example, DMAX = 0.78).
CS may be required if the presence of RS causes increased noise, due to adjacent signals like the gate drive, to appear at the CS pin. The TPS23753A has an internal pulldown on CS ( approximately 400 Ω maximum) while the MOSFET is OFF to reduce cycle-to-cycle carry-over voltage on CS.
The FRS pin programs the (free-running) oscillator frequency, and may also be used to synchronize the TPS23753A converter to a higher frequency. The internal oscillator sets the maximum duty cycle and controls the current-compensation ramp circuit, making the ramp height independent of frequency. RFRS must be selected per Equation 7.
The TPS23753A may be synchronized to an external clock to eliminate beat frequencies from a sampled system, or to place emission spectrum away from an RF input frequency. Synchronization may be accomplished by applying a short pulse ( > 25 ns) of magnitude VSYNC to FRS as shown in Figure 21. RFRS must be chosen so that the maximum free-running frequency is just below the desired synchronization frequency. The synchronization pulse terminates the potential ON-time period, and the OFF-time period does not begin until the pulse terminates. A short pulse is preferred to avoid reducing the potential ON-time.
Figure 21 shows examples of nonisolated and transformer-coupled synchronization circuits RT reduces noise susceptibility for the isolation transformer implementation. The FRS node must be protected from noise because it is high impedance.
Many PoE-capable devices are designed to operate from either a wall adapter or PoE power. A local power solution adds cost and complexity, but allows a product to be used if PoE is not available in a particular installation. While most applications only require that the PD operate when both sources are present, the TPS23753A supports forced operation from either of the power sources. Figure 22 illustrates three options for diode ORing external power into a PD. Only one option would be used in any particular design. Option 1 applies power to the TPS23753A PoE input, option 2 applies power between the TPS23753A PoE section and the power circuit, and option 3 applies power to the output side of the converter. Each of these options has advantages and disadvantages. A detailed discussion of the TPS23753A and ORing solutions is covered in application note Advanced Adapter ORing Solutions using the TPS23753, (SLVA306).
Preference of one power source presents a number of challenges. Combinations of adapter output voltage (nominal and tolerance), power insertion point, and which source is preferred determine solution complexity. Several factors contributing to the complexity are the natural high-voltage selection of diode ORing (the simplest method of combining sources), the current limit implicit in the PSE, PD inrush, and protection circuits (necessary for operation and reliability). Creating simple and seamless solutions is difficult if not impossible for many of the combinations. However, the TPS23753A offers several built-in features that simplify some combinations.
Several examples demonstrate the limitations inherent in ORing solutions. Diode ORing a 48-V adapter with PoE (option 1) presents the problem that either source might be higher. A blocking switch would be required to assure which source was active. A second example is combining a 12-V adapter with PoE using option 2. The converter draws approximately four times the current at 12 V from the adapter than it does from PoE at 48 V. Transition from adapter power to PoE may demand more current than can be supplied by the PSE. The converter must be turned off while CIN capacitance charges, with a subsequent converter restart at the higher voltage and lower input current. A third example is use of a 12-V adapter with ORing option 1. The PD hotswap would have to handle four times the current, and have 1/16 the resistance (be 16 times larger) to dissipate equal power. A fourth example is that MPS is lost when running from the adapter, causing the PSE to remove power from the PD. If adapter power is then lost, the PD stops operating until the PSE detects and powers the PD.
The most popular preferential ORing scheme is option 2 with adapter priority. The hotswap MOSFET is disabled when the adapter is used to pull APD high, blocking the PoE source from powering the output. This solution works well with a wide range of adapter voltages, is simple, and requires few external parts. When the AC power fails, or the adapter is removed, the hotswap switch is enabled. In the simplest implementation, the PD momentarily loses power until the PSE completes its start-up cycle.
The DEN pin can be used to disable the PoE input when ORing with option 3. This is an adapter priority implementation. Pulling DEN low, while creating an invalid detection signature, disables the hotswap MOSFET, and prevents the PD from redetecting. This would typically be accomplished with an optocoupler that is driven from the secondary side of the converter.
The least popular technique is PoE priority. It is implemented by placing a diode between the PD supply voltage, VDD, and the DC-DC controller bias voltage, VDD1. The diode prevents reverse biasing of the PoE input diode bridges when option 2 adapter ORing is used. The PSE may then detect, classify, and provide power to the PD while a live adapter is connected. As long as the PoE voltage is greater than the adapter voltage, the PSE powers the load. The APD function is not used in this technique.
The IEEE standards require that the PI conductors be electrically isolated from ground and all other system potentials not part of the PI interface. The adapter must meet a minimum 1500-Vac dielectric withstand test between the output and all other connections for options 1 and 2. The adapter only needs this isolation for option 3 if it is not provided by the converter.
Adapter ORing diodes are shown for all the options to protect against a reverse-voltage adapter, a short on the adapter input pins, and damage to a low-voltage adapter. ORing is sometimes accomplished with a MOSFET in option 3.
A TVS across the rectified PoE voltage per Figure 25 must be used. For general indoor applications, TI recommends an SMAJ58A or a part with equal to or better performance. If an adapter is connected from VDD1 to RTN, as in ORing option 2 above, voltage transients caused by the input cable inductance ringing with the internal PD capacitance can occur. Adequate capacitive filtering or a TVS must limit this voltage to be within the Absolute Maximum Ratings. Configurations that use DVDD as in Figure 23 may require additional protection against ESD transients that would turn DVDD off and force all the voltage to appear across the internal hotswap MOSFET. CVDD and DRTN per Figure 23 provide this additional protection.
Outdoor applications require more extensive protection to lightning standards.
The international standard CISPR 22 (and adopted versions) is often used as a requirement for conducted emissions. Ethernet cables are covered as a telecommunication port under section 5.2 for conducted emissions. Meeting EMI requirements is often a challenge, with the lower limits of Class B being especially hard. Circuit board layout, filtering, and snubbing various nodes in the power circuit are the first layer of control techniques. A more detailed discussion of EMI control is presented in Practical Guidelines to Designing an EMI Compliant PoE Powered Device With Isolated Flyback, SLUA469. Additionally, IEEE 802.3at sections 33.3 and 33.4 have requirements for noise injected onto the Ethernet cable based on compatibility with data transmission.
Occasionally, a technique referred to as frequency dithering is used to provide additional EMI measurement reduction. The switching frequency is modulated to spread the narrowband individual harmonics across a wider bandwidth, thus lowering peak measurements. The circuit of Figure 24 modulates the switching frequency by feeding a small AC signal into the FRS pin. These values may be adapted to suit individual needs.